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68 files changed, 4813 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/console/console-uart4.c b/bsps/arm/stm32h7/console/console-uart4.c new file mode 100644 index 0000000000..40536d61cf --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart4.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_uart4_config = { + .gpio = { + .regs = GPIOH, + .config = { + .Pin = GPIO_PIN_13 | GPIO_PIN_14, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF6_UART4 + } + }, + .irq = UART4_IRQn, + .device_index = 3 +}; + +stm32h7_uart_context stm32h7_uart4_instance = { + .uart = { + .Instance = UART4, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_uart4_config +}; diff --git a/bsps/arm/stm32h7/console/console-uart5.c b/bsps/arm/stm32h7/console/console-uart5.c new file mode 100644 index 0000000000..45b1c04b7c --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart5.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_uart5_config = { + .gpio = { + .regs = GPIOD, + .config = { + .Pin = GPIO_PIN_1 | GPIO_PIN_2, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF8_UART5 + } + }, + .irq = UART5_IRQn, + .device_index = 4 +}; + +stm32h7_uart_context stm32h7_uart5_instance = { + .uart = { + .Instance = UART5, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_uart5_config +}; diff --git a/bsps/arm/stm32h7/console/console-uart7.c b/bsps/arm/stm32h7/console/console-uart7.c new file mode 100644 index 0000000000..eadf7723c6 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart7.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_uart7_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_3 | GPIO_PIN_4, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_UART7 + } + }, + .irq = UART7_IRQn, + .device_index = 6 +}; + +stm32h7_uart_context stm32h7_uart7_instance = { + .uart = { + .Instance = UART7, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_uart7_config +}; diff --git a/bsps/arm/stm32h7/console/console-uart8.c b/bsps/arm/stm32h7/console/console-uart8.c new file mode 100644 index 0000000000..5daa0e3635 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart8.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_uart8_config = { + .gpio = { + .regs = GPIOE, + .config = { + .Pin = GPIO_PIN_0 | GPIO_PIN_1, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF8_UART8 + } + }, + .irq = UART8_IRQn, + .device_index = 7 +}; + +stm32h7_uart_context stm32h7_uart8_instance = { + .uart = { + .Instance = UART8, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_uart8_config +}; diff --git a/bsps/arm/stm32h7/console/console-uart9.c b/bsps/arm/stm32h7/console/console-uart9.c new file mode 100644 index 0000000000..821bc11bcc --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart9.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#ifdef UART9 + +static const stm32h7_uart_config stm32h7_uart9_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_15 | GPIO_PIN_14, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_UART9 + } + }, + .irq = UART9_IRQn, + .device_index = 8 +}; + +stm32h7_uart_context stm32h7_uart9_instance = { + .uart = { + .Instance = UART9, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_uart9_config +}; + +#endif /* UART9 */ diff --git a/bsps/arm/stm32h7/console/console-usart1.c b/bsps/arm/stm32h7/console/console-usart1.c new file mode 100644 index 0000000000..6dec753d7d --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart1.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_usart1_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_14 | GPIO_PIN_15, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF4_USART1 + } + }, + .irq = USART1_IRQn, + .device_index = 0 +}; + +stm32h7_uart_context stm32h7_usart1_instance = { + .uart = { + .Instance = USART1, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_usart1_config +}; diff --git a/bsps/arm/stm32h7/console/console-usart10.c b/bsps/arm/stm32h7/console/console-usart10.c new file mode 100644 index 0000000000..b73346e2cf --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart10.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#ifdef USART10 + +static const stm32h7_uart_config stm32h7_usart10_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_15 | GPIO_PIN_14, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_USART10 + } + }, + .irq = USART10_IRQn, + .device_index = 9 +}; + +stm32h7_uart_context stm32h7_usart10_instance = { + .uart = { + .Instance = USART10, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_usart10_config +}; + +#endif /* USART10 */ diff --git a/bsps/arm/stm32h7/console/console-usart2.c b/bsps/arm/stm32h7/console/console-usart2.c new file mode 100644 index 0000000000..291dbc044d --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart2.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_usart2_config = { + .gpio = { + .regs = GPIOA, + .config = { + .Pin = GPIO_PIN_2 | GPIO_PIN_3, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART2 + } + }, + .irq = USART2_IRQn, + .device_index = 1 +}; + +stm32h7_uart_context stm32h7_usart2_instance = { + .uart = { + .Instance = USART2, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_usart2_config +}; diff --git a/bsps/arm/stm32h7/console/console-usart3.c b/bsps/arm/stm32h7/console/console-usart3.c new file mode 100644 index 0000000000..6e0a10fe46 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart3.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_usart3_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_9 | GPIO_PIN_10, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART3 + } + }, + .irq = USART3_IRQn, + .device_index = 2 +}; + +stm32h7_uart_context stm32h7_usart3_instance = { + .uart = { + .Instance = USART3, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_usart3_config +}; diff --git a/bsps/arm/stm32h7/console/console-usart6.c b/bsps/arm/stm32h7/console/console-usart6.c new file mode 100644 index 0000000000..d43d8dfbf5 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart6.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_uart_config stm32h7_usart6_config = { + .gpio = { + .regs = GPIOC, + .config = { + .Pin = GPIO_PIN_6 | GPIO_PIN_7, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART6 + } + }, + .irq = USART6_IRQn, + .device_index = 5 +}; + +stm32h7_uart_context stm32h7_usart6_instance = { + .uart = { + .Instance = USART6, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }, + .config = &stm32h7_usart6_config +}; diff --git a/bsps/arm/stm32h7/console/console.c b/bsps/arm/stm32h7/console/console.c new file mode 100644 index 0000000000..35b701a655 --- /dev/null +++ b/bsps/arm/stm32h7/console/console.c @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/fatal.h> +#include <rtems/console.h> + +#include <inttypes.h> +#include <stdio.h> +#include <unistd.h> + +static stm32h7_uart_context * const stm32h7_uart_instances[] = { +#ifdef STM32H7_CONSOLE_ENABLE_USART1 + &stm32h7_usart1_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_USART2 + &stm32h7_usart2_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_USART3 + &stm32h7_usart3_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_UART4 + &stm32h7_uart4_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_UART5 + &stm32h7_uart5_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_USART6 + &stm32h7_usart6_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_UART7 + &stm32h7_uart7_instance, +#endif +#ifdef STM32H7_CONSOLE_ENABLE_UART8 + &stm32h7_uart8_instance, +#endif +#if defined(STM32H7_CONSOLE_ENABLE_UART9) && defined(UART9) + &stm32h7_uart9_instance, +#endif +#if defined(STM32H7_CONSOLE_ENABLE_USART10) && defined(USART10) + &stm32h7_usart10_instance +#endif +}; + +static bool stm32h7_uart_set_attributes( + rtems_termios_device_context *base, + const struct termios *term +) +{ + stm32h7_uart_context *ctx; + uint32_t previous_baud; + uint32_t previous_stop_bits; + uint32_t previous_parity; + uint32_t previous_mode; + HAL_StatusTypeDef status; + + if ((term->c_cflag & CSIZE) != CS8) { + return false; + } + + ctx = stm32h7_uart_get_context(base); + + previous_baud = ctx->uart.Init.BaudRate; + ctx->uart.Init.BaudRate = rtems_termios_baud_to_number(term->c_ospeed); + + previous_stop_bits = ctx->uart.Init.StopBits; + if ((term->c_cflag & CSTOPB) != 0) { + ctx->uart.Init.StopBits = UART_STOPBITS_2; + } else { + ctx->uart.Init.StopBits = UART_STOPBITS_1; + } + + previous_parity = ctx->uart.Init.Parity; + if ((term->c_cflag & PARENB) != 0) { + if ((term->c_cflag & PARODD) != 0) { + ctx->uart.Init.Parity = UART_PARITY_ODD; + } else { + ctx->uart.Init.Parity = UART_PARITY_EVEN; + } + } else { + ctx->uart.Init.Parity = UART_PARITY_NONE; + } + + previous_mode = ctx->uart.Init.Mode; + if ((term->c_cflag & CREAD) != 0) { + ctx->uart.Init.Mode = UART_MODE_TX_RX; + } else { + ctx->uart.Init.Mode = UART_MODE_RX; + } + + status = UART_SetConfig(&ctx->uart); + if (status != HAL_OK) { + ctx->uart.Init.BaudRate = previous_baud; + ctx->uart.Init.StopBits = previous_stop_bits; + ctx->uart.Init.Parity = previous_parity; + ctx->uart.Init.Mode = previous_mode; + return false; + } + + return true; +} + +#ifdef BSP_CONSOLE_USE_INTERRUPTS +static void stm32h7_uart_interrupt(void *arg) +{ + rtems_termios_tty *tty; + rtems_termios_device_context *base; + stm32h7_uart_context *ctx; + USART_TypeDef *regs; + uint32_t isr; + + tty = arg; + base = rtems_termios_get_device_context(tty); + ctx = stm32h7_uart_get_context(base); + regs = ctx->uart.Instance; + isr = regs->ISR; + + while ((isr & USART_ISR_RXNE_RXFNE) != 0) { + char c; + + c = (uint8_t) regs->RDR; + rtems_termios_enqueue_raw_characters(tty, &c, 1); + + isr = regs->ISR; + } + + if (ctx->transmitting && (isr & USART_ISR_TXE_TXFNF) != 0) { + rtems_termios_dequeue_characters(tty, 1); + } + + regs->ICR = USART_ICR_ORECF; +} +#endif + +static bool stm32h7_uart_first_open( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + struct termios *term, + rtems_libio_open_close_args_t *args +) +{ + stm32h7_uart_context *ctx; + UART_HandleTypeDef *uart; +#ifdef BSP_CONSOLE_USE_INTERRUPTS + rtems_status_code sc; +#endif + + ctx = stm32h7_uart_get_context(base); + uart = &ctx->uart; + + rtems_termios_set_initial_baud(tty, BSP_CONSOLE_BAUD); + + (void) HAL_UART_Init(uart); + (void) HAL_UARTEx_SetTxFifoThreshold(uart, UART_TXFIFO_THRESHOLD_1_8); + (void) HAL_UARTEx_SetRxFifoThreshold(uart, UART_RXFIFO_THRESHOLD_1_8); + (void) HAL_UARTEx_EnableFifoMode(uart); + +#ifdef BSP_CONSOLE_USE_INTERRUPTS + sc = rtems_interrupt_handler_install( + ctx->config->irq, + "UART", + RTEMS_INTERRUPT_SHARED, + stm32h7_uart_interrupt, + tty + ); + if (sc != RTEMS_SUCCESSFUL) { + return false; + } + + ctx->uart.Instance->CR1 |= USART_CR1_RXNEIE_RXFNEIE; +#endif + + stm32h7_uart_set_attributes(base, term); + + return true; +} + +static void stm32h7_uart_last_close( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + rtems_libio_open_close_args_t *args +) +{ +#ifdef BSP_CONSOLE_USE_INTERRUPTS + stm32h7_uart_context *ctx; + + ctx = stm32h7_uart_get_context(base); + + (void) rtems_interrupt_handler_remove( + ctx->config->irq, + stm32h7_uart_interrupt, + tty + ); +#endif +} + +static void stm32h7_uart_write( + rtems_termios_device_context *base, + const char *buf, + size_t len +) +{ +#ifdef BSP_CONSOLE_USE_INTERRUPTS + stm32h7_uart_context *ctx; + USART_TypeDef *regs; + + ctx = stm32h7_uart_get_context(base); + regs = ctx->uart.Instance; + + if (len > 0) { + ctx->transmitting = true; + regs->TDR = (uint8_t) buf[0]; + regs->CR1 |= USART_CR1_TXEIE_TXFNFIE; + } else { + ctx->transmitting = false; + regs->CR1 &= ~USART_CR1_TXEIE_TXFNFIE; + } +#else + size_t i; + + for (i = 0; i < len; ++i) { + stm32h7_uart_polled_write(base, buf[i]); + } +#endif +} + +static const rtems_termios_device_handler stm32h7_uart_handler = { + .first_open = stm32h7_uart_first_open, + .last_close = stm32h7_uart_last_close, + .write = stm32h7_uart_write, + .set_attributes = stm32h7_uart_set_attributes, +#ifdef BSP_CONSOLE_USE_INTERRUPTS + .mode = TERMIOS_IRQ_DRIVEN +#else + .poll_read = stm32h7_uart_polled_read, + .mode = TERMIOS_POLLED +#endif +}; + +rtems_status_code console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + size_t i; + + rtems_termios_initialize(); + + for (i = 0; i < RTEMS_ARRAY_SIZE(stm32h7_uart_instances); ++i) { + stm32h7_uart_context *ctx; + char path[sizeof("/dev/ttySXXX")]; + + ctx = stm32h7_uart_instances[i]; + snprintf(path, sizeof(path), "/dev/ttyS%" PRIu8, ctx->config->device_index); + + rtems_termios_device_install( + path, + &stm32h7_uart_handler, + NULL, + &ctx->device + ); + + if (ctx == &STM32H7_PRINTK_INSTANCE) { + link(path, CONSOLE_DEVICE_NAME); + } + } + + return RTEMS_SUCCESSFUL; +} diff --git a/bsps/arm/stm32h7/console/printk-support.c b/bsps/arm/stm32h7/console/printk-support.c new file mode 100644 index 0000000000..e663c10d89 --- /dev/null +++ b/bsps/arm/stm32h7/console/printk-support.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <bsp.h> +#include <rtems/bspIo.h> +#include <rtems/sysinit.h> + +#include <stm32h7/hal.h> + +static void stm32h7_output_char(char c) +{ + stm32h7_uart_polled_write(&STM32H7_PRINTK_INSTANCE.device, c); +} + +static void stm32h7_output_char_init(void) +{ + UART_HandleTypeDef *uart; + + uart = &STM32H7_PRINTK_INSTANCE.uart; + (void) HAL_UART_Init(uart); + (void) HAL_UARTEx_SetTxFifoThreshold(uart, UART_TXFIFO_THRESHOLD_1_8); + (void) HAL_UARTEx_SetRxFifoThreshold(uart, UART_RXFIFO_THRESHOLD_1_8); + (void) HAL_UARTEx_EnableFifoMode(uart); + + BSP_output_char = stm32h7_output_char; +} + +static void stm32h7_output_char_init_early(char c) +{ + stm32h7_output_char_init(); + stm32h7_output_char(c); +} + +static int stm32h7_poll_char(void) +{ + return stm32h7_uart_polled_read(&STM32H7_PRINTK_INSTANCE.device); +} + +BSP_output_char_function_type BSP_output_char = stm32h7_output_char_init_early; + +BSP_polling_getchar_function_type BSP_poll_char = stm32h7_poll_char; + +RTEMS_SYSINIT_ITEM( + stm32h7_output_char_init, + RTEMS_SYSINIT_BSP_START, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/arm/stm32h7/include/bsp.h b/bsps/arm/stm32h7/include/bsp.h new file mode 100644 index 0000000000..06c4e678aa --- /dev/null +++ b/bsps/arm/stm32h7/include/bsp.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32H7_BSP_H +#define LIBBSP_ARM_STM32H7_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY stm32h7_systick_frequency() + +uint32_t stm32h7_systick_frequency(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_STM32H7_BSP_H */ diff --git a/bsps/arm/stm32h7/include/bsp/irq.h b/bsps/arm/stm32h7/include/bsp/irq.h new file mode 100644 index 0000000000..b3ff7a9621 --- /dev/null +++ b/bsps/arm/stm32h7/include/bsp/irq.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32H7_IRQ_H +#define LIBBSP_ARM_STM32H7_IRQ_H + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#endif /* ASM */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX 239 + +#endif /* LIBBSP_ARM_STM32H7_IRQ_H */ diff --git a/bsps/arm/stm32h7/include/chip.h b/bsps/arm/stm32h7/include/chip.h new file mode 100644 index 0000000000..26b067a3b7 --- /dev/null +++ b/bsps/arm/stm32h7/include/chip.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32H7_CHIP_H +#define LIBBSP_ARM_STM32H7_CHIP_H + +#include <stm32h7xx.h> +#include <core_cm7.h> + +#endif /* LIBBSP_ARM_STM32H7_CHIP_H */ diff --git a/bsps/arm/stm32h7/include/stm32h7/hal.h b/bsps/arm/stm32h7/include/stm32h7/hal.h new file mode 100644 index 0000000000..fe37f03c04 --- /dev/null +++ b/bsps/arm/stm32h7/include/stm32h7/hal.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32H7_STM32H7_HAL_H +#define LIBBSP_ARM_STM32H7_STM32H7_HAL_H + +#include <stm32h7xx_hal.h> + +#include <rtems/termiostypes.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + STM32H7_MODULE_INVALID, + STM32H7_MODULE_GPIOA, + STM32H7_MODULE_GPIOB, + STM32H7_MODULE_GPIOC, + STM32H7_MODULE_GPIOD, + STM32H7_MODULE_GPIOE, + STM32H7_MODULE_GPIOF, + STM32H7_MODULE_GPIOG, + STM32H7_MODULE_GPIOH, + STM32H7_MODULE_GPIOI, + STM32H7_MODULE_GPIOJ, + STM32H7_MODULE_GPIOK, + STM32H7_MODULE_USART1, + STM32H7_MODULE_USART2, + STM32H7_MODULE_USART3, + STM32H7_MODULE_UART4, + STM32H7_MODULE_UART5, + STM32H7_MODULE_USART6, + STM32H7_MODULE_UART7, + STM32H7_MODULE_UART8, + STM32H7_MODULE_UART9, + STM32H7_MODULE_USART10, + STM32H7_MODULE_RNG, + STM32H7_MODULE_ETH1MAC, + STM32H7_MODULE_ETH1TX, + STM32H7_MODULE_ETH1RX, + STM32H7_MODULE_USB1_OTG, + STM32H7_MODULE_USB1_OTG_ULPI, + STM32H7_MODULE_USB2_OTG, + STM32H7_MODULE_USB2_OTG_ULPI +} stm32h7_module_index; + +stm32h7_module_index stm32h7_get_module_index(const void *regs); + +void stm32h7_clk_enable(stm32h7_module_index index); + +void stm32h7_clk_disable(stm32h7_module_index index); + +void stm32h7_clk_low_power_enable(stm32h7_module_index index); + +void stm32h7_clk_low_power_disable(stm32h7_module_index index); + +typedef struct { + GPIO_TypeDef *regs; + GPIO_InitTypeDef config; +} stm32h7_gpio_config; + +void stm32h7_gpio_init(const stm32h7_gpio_config *config); + +typedef struct { + stm32h7_gpio_config gpio; + rtems_vector_number irq; + uint8_t device_index; +} stm32h7_uart_config; + +typedef struct { + UART_HandleTypeDef uart; + bool transmitting; + rtems_termios_device_context device; + const stm32h7_uart_config *config; +} stm32h7_uart_context; + +static inline stm32h7_uart_context *stm32h7_uart_get_context( + rtems_termios_device_context *base +) +{ + return RTEMS_CONTAINER_OF(base, stm32h7_uart_context, device); +} + +void stm32h7_uart_polled_write(rtems_termios_device_context *base, char c); + +int stm32h7_uart_polled_read(rtems_termios_device_context *base); + +extern stm32h7_uart_context stm32h7_usart1_instance; + +extern stm32h7_uart_context stm32h7_usart2_instance; + +extern stm32h7_uart_context stm32h7_usart3_instance; + +extern stm32h7_uart_context stm32h7_uart4_instance; + +extern stm32h7_uart_context stm32h7_uart5_instance; + +extern stm32h7_uart_context stm32h7_usart6_instance; + +extern stm32h7_uart_context stm32h7_uart7_instance; + +extern stm32h7_uart_context stm32h7_uart8_instance; + +extern stm32h7_uart_context stm32h7_uart9_instance; + +extern stm32h7_uart_context stm32h7_usart10_instance; + +extern const uint32_t stm32h7_config_pwr_regulator_voltagescaling; + +extern const RCC_OscInitTypeDef stm32h7_config_oscillator; + +extern const RCC_ClkInitTypeDef stm32h7_config_clocks; + +extern const uint32_t stm32h7_config_flash_latency; + +extern const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks; + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_STM32H7_STM32H7_HAL_H */ diff --git a/bsps/arm/stm32h7/include/stm32h7/memory.h b/bsps/arm/stm32h7/include/stm32h7/memory.h new file mode 100644 index 0000000000..27f57fd6a6 --- /dev/null +++ b/bsps/arm/stm32h7/include/stm32h7/memory.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SMEMORYL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32H7_STM32H7_MEMORY_H +#define LIBBSP_ARM_STM32H7_STM32H7_MEMORY_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern char stm32h7_memory_null_begin[]; +extern char stm32h7_memory_null_end[]; +extern char stm32h7_memory_null_size[]; + +extern char stm32h7_memory_itcm_begin[]; +extern char stm32h7_memory_itcm_end[]; +extern char stm32h7_memory_itcm_size[]; + +extern char stm32h7_memory_flash_begin[]; +extern char stm32h7_memory_flash_end[]; +extern char stm32h7_memory_flash_size[]; + +extern char stm32h7_memory_dtcm_begin[]; +extern char stm32h7_memory_dtcm_end[]; +extern char stm32h7_memory_dtcm_size[]; + +extern char stm32h7_memory_sram_axi_begin[]; +extern char stm32h7_memory_sram_axi_end[]; +extern char stm32h7_memory_sram_axi_size[]; + +extern char stm32h7_memory_sram_1_begin[]; +extern char stm32h7_memory_sram_1_end[]; +extern char stm32h7_memory_sram_1_size[]; + +extern char stm32h7_memory_sram_2_begin[]; +extern char stm32h7_memory_sram_2_end[]; +extern char stm32h7_memory_sram_2_size[]; + +extern char stm32h7_memory_sram_3_begin[]; +extern char stm32h7_memory_sram_3_end[]; +extern char stm32h7_memory_sram_3_size[]; + +extern char stm32h7_memory_sram_4_begin[]; +extern char stm32h7_memory_sram_4_end[]; +extern char stm32h7_memory_sram_4_size[]; + +extern char stm32h7_memory_sram_backup_begin[]; +extern char stm32h7_memory_sram_backup_end[]; +extern char stm32h7_memory_sram_backup_size[]; + +extern char stm32h7_memory_peripheral_begin[]; +extern char stm32h7_memory_peripheral_end[]; +extern char stm32h7_memory_peripheral_size[]; + +extern char stm32h7_memory_nor_begin[]; +extern char stm32h7_memory_nor_end[]; +extern char stm32h7_memory_nor_size[]; + +extern char stm32h7_memory_sdram_1_begin[]; +extern char stm32h7_memory_sdram_1_end[]; +extern char stm32h7_memory_sdram_1_size[]; + +extern char stm32h7_memory_nand_begin[]; +extern char stm32h7_memory_nand_end[]; +extern char stm32h7_memory_nand_size[]; + +extern char stm32h7_memory_quadspi_begin[]; +extern char stm32h7_memory_quadspi_end[]; +extern char stm32h7_memory_quadspi_size[]; + +extern char stm32h7_memory_sdram_2_begin[]; +extern char stm32h7_memory_sdram_2_end[]; +extern char stm32h7_memory_sdram_2_size[]; + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_STM32H7_STM32H7_MEMORY_H */ diff --git a/bsps/arm/stm32h7/include/stm32h7xx.h b/bsps/arm/stm32h7/include/stm32h7xx.h index f6296181be..36d3012af4 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx.h +++ b/bsps/arm/stm32h7/include/stm32h7xx.h @@ -38,6 +38,9 @@ #ifndef STM32H7xx_H
#define STM32H7xx_H
+#ifdef __rtems__
+#include <bspopts.h>
+#endif /* __rtems__ */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h new file mode 100644 index 0000000000..d423e4f782 --- /dev/null +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -0,0 +1,493 @@ +/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OTFDEC_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HRTIM_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+#define HAL_GFXMMU_MODULE_ENABLED
+#define HAL_JPEG_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+#define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SWPMI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+#define HAL_JPEG_MODULE_ENABLED
+#define HAL_MDIOS_MODULE_ENABLED
+#define HAL_PSSI_MODULE_ENABLED
+#define HAL_DTS_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal oscillator (CSI) default value.
+ * This value is the default CSI value after Reset.
+ */
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0
+#define USE_HAL_DTS_REGISTER_CALLBACKS 0
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0
+#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0
+#define USE_HAL_JPEG_REGISTER_CALLBACKS 0
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0
+#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0
+#define USE_HAL_OSPI_REGISTER_CALLBACKS 0
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0
+#define USE_HAL_SD_REGISTER_CALLBACKS 0
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0
+#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0
+#define USE_HAL_UART_REGISTER_CALLBACKS 0
+#define USE_HAL_USART_REGISTER_CALLBACKS 0
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0 ((uint8_t)0x02)
+#define ETH_MAC_ADDR1 ((uint8_t)0x00)
+#define ETH_MAC_ADDR2 ((uint8_t)0x00)
+#define ETH_MAC_ADDR3 ((uint8_t)0x00)
+#define ETH_MAC_ADDR4 ((uint8_t)0x00)
+#define ETH_MAC_ADDR5 ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+ #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+ #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsps/arm/stm32h7/include/system_stm32h7xx.h b/bsps/arm/stm32h7/include/system_stm32h7xx.h index dd75af67ff..ca0f335f7e 100644 --- a/bsps/arm/stm32h7/include/system_stm32h7xx.h +++ b/bsps/arm/stm32h7/include/system_stm32h7xx.h @@ -85,6 +85,9 @@ extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers ta extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
+#ifdef __rtems__
+extern void SystemInit_ExtMemCtl(void);
+#endif /* __rtems__ */
/**
* @}
*/
diff --git a/bsps/arm/stm32h7/include/tm27.h b/bsps/arm/stm32h7/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/arm/stm32h7/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/arm/stm32h7/start/bsp_specs b/bsps/arm/stm32h7/start/bsp_specs new file mode 100644 index 0000000000..47dd31d46b --- /dev/null +++ b/bsps/arm/stm32h7/start/bsp_specs @@ -0,0 +1,9 @@ +%rename endfile old_endfile +%rename startfile old_startfile + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}} + +*endfile: +%{!qrtems: %(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s} diff --git a/bsps/arm/stm32h7/start/bspstart.c b/bsps/arm/stm32h7/start/bspstart.c new file mode 100644 index 0000000000..2fc8133cca --- /dev/null +++ b/bsps/arm/stm32h7/start/bspstart.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/bootcard.h> +#include <bsp/irq-generic.h> +#include <bsp/linker-symbols.h> + +#include <stm32h7xx_hal.h> + +uint32_t HAL_GetTick(void) +{ + return 0; +} + +uint32_t stm32h7_systick_frequency(void) +{ + return SystemCoreClock; +} + +void bsp_start(void) +{ + bsp_interrupt_initialize(); + rtems_cache_coherent_add_area( + bsp_section_nocacheheap_begin, + (uintptr_t) bsp_section_nocacheheap_size + ); +} diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c b/bsps/arm/stm32h7/start/bspstarthooks.c new file mode 100644 index 0000000000..565bd6876a --- /dev/null +++ b/bsps/arm/stm32h7/start/bspstarthooks.c @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/bootcard.h> +#include <bsp/linker-symbols.h> +#include <bsp/start.h> +#include <stm32h7/hal.h> +#include <stm32h7/memory.h> +#include <rtems/score/armv7m.h> + +#include <string.h> + +void HAL_MspInit(void) +{ + __HAL_RCC_SYSCFG_CLK_ENABLE(); +} + +static void init_power(void) +{ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + __HAL_PWR_VOLTAGESCALING_CONFIG(stm32h7_config_pwr_regulator_voltagescaling); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) { + /* Wait */ + } +} + +static void init_oscillator(void) +{ + HAL_StatusTypeDef status; + + status = HAL_RCC_OscConfig(&stm32h7_config_oscillator); + if (status != HAL_OK) { + bsp_reset(); + } +} + +static void init_clocks(void) +{ + HAL_StatusTypeDef status; + + status = HAL_RCC_ClockConfig( + &stm32h7_config_clocks, + stm32h7_config_flash_latency + ); + if (status != HAL_OK) { + bsp_reset(); + } +} + +static void init_peripheral_clocks(void) +{ + HAL_StatusTypeDef status; + + status = HAL_RCCEx_PeriphCLKConfig(&stm32h7_config_peripheral_clocks); + if (status != HAL_OK) { + bsp_reset(); + } +} + +static uint32_t get_region_size(uintptr_t size) +{ + if ((size & (size - 1)) == 0) { + return ARMV7M_MPU_RASR_SIZE(30 - __builtin_clz(size)); + } else { + return ARMV7M_MPU_RASR_SIZE(31 - __builtin_clz(size)); + } +} + +static void set_region( + volatile ARMV7M_MPU *mpu, + uint32_t region, + uint32_t rasr, + const void *begin, + const void *end +) +{ + uintptr_t size; + uint32_t rbar; + + RTEMS_OBFUSCATE_VARIABLE(begin); + RTEMS_OBFUSCATE_VARIABLE(end); + size = (uintptr_t) end - (uintptr_t) begin; + + if ( size > 0 ) { + rbar = (uintptr_t) begin | region | ARMV7M_MPU_RBAR_VALID; + rasr |= get_region_size(size); + } else { + rbar = region; + rasr = 0; + } + + mpu->rbar = rbar; + mpu->rasr = rasr; +} + +static void init_mpu(void) +{ + volatile ARMV7M_MPU *mpu; + volatile ARMV7M_SCB *scb; + uint32_t region_count; + uint32_t region; + + mpu = _ARMV7M_MPU; + scb = _ARMV7M_SCB; + + region_count = ARMV7M_MPU_TYPE_DREGION_GET(mpu->type); + + for (region = 0; region < region_count; ++region) { + mpu->rbar = ARMV7M_MPU_RBAR_VALID | region; + mpu->rasr = 0; + } + + set_region( + mpu, + 0, + ARMV7M_MPU_RASR_XN + | ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + stm32h7_memory_sram_axi_begin, + stm32h7_memory_sram_axi_end + ); + set_region( + mpu, + 1, + ARMV7M_MPU_RASR_XN + | ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + stm32h7_memory_sdram_1_begin, + stm32h7_memory_sdram_1_end + ); + set_region( + mpu, + 2, + ARMV7M_MPU_RASR_AP(0x5) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + bsp_section_start_begin, + bsp_section_text_end + ); + set_region( + mpu, + 3, + ARMV7M_MPU_RASR_XN + | ARMV7M_MPU_RASR_AP(0x5) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + bsp_section_rodata_begin, + bsp_section_rodata_end + ); + set_region( + mpu, + 4, + ARMV7M_MPU_RASR_XN + | ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x2) + | ARMV7M_MPU_RASR_ENABLE, + bsp_section_nocache_begin, + bsp_section_nocachenoload_end + ); + set_region( + mpu, + region - 1, + ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_ENABLE, + stm32h7_memory_null_begin, + stm32h7_memory_null_end + ); + + mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA; + scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA; + + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); +} + +void bsp_start_hook_0(void) +{ + if ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0) { + /* + * Only perform the low-level initialization if necessary. An initialized + * FMC indicates that a boot loader already performed the low-level + * initialization. + */ + SystemInit(); + init_power(); + init_oscillator(); + init_clocks(); + init_peripheral_clocks(); + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); + HAL_Init(); + SystemInit_ExtMemCtl(); + } + + if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) { + SCB_EnableICache(); + } + + if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) { + SCB_EnableDCache(); + } + + init_mpu(); +} + +void bsp_start_hook_1(void) +{ + bsp_start_copy_sections_compact(); + SCB_CleanDCache(); + SCB_InvalidateICache(); + bsp_start_clear_bss(); +} diff --git a/bsps/arm/stm32h7/start/ext-mem-ctl.c b/bsps/arm/stm32h7/start/ext-mem-ctl.c new file mode 100644 index 0000000000..4088010696 --- /dev/null +++ b/bsps/arm/stm32h7/start/ext-mem-ctl.c @@ -0,0 +1,473 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include <stm32h7xx_hal.h>
+
+#define DATA_IN_ExtSRAM
+#define DATA_IN_ExtSDRAM
+
+void SystemInit_ExtMemCtl(void)
+{
+
+ #define FMC_BMAP_Value 0x02000000 /* FMC Bank Mapping 2 (SDRAM Bank2 remapped) */
+
+ __IO uint32_t tmp = 0;
+
+
+ /********** SDRAM + SRAM ***********************************************************************/
+
+ #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /*-- I/O Ports Configuration ------------------------------------------------------*/
+
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB4ENR |= 0x000001F8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAAFAFA;
+ /* Configure PDx pins speed to VERY_HIGH */
+ GPIOD->OSPEEDR = 0xFFFFFF0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x55550505;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABEBA;
+ /* Configure PEx pins speed to VERY_HIGH */
+ GPIOE->OSPEEDR = 0xFFFFFFFF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554145;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCCC000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAABFFAAA;
+ /* Configure PFx pins speed to VERY_HIGH */
+ GPIOF->OSPEEDR = 0xFFC00FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55400555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0xC0000C0C;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xBFEEFAAA;
+ /* Configure PGx pins speed to VERY_HIGH */
+ GPIOG->OSPEEDR = 0xC0330FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x40110555;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0xCCC00000;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAAABFF;
+ /* Configure PHx pins speed to VERY_HIGH */
+ GPIOH->OSPEEDR = 0xFFFFFC00;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* Configure PHx pins in Pull-up */
+ GPIOH->PUPDR = 0x55555400;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0xFFEBAAAA;
+ /* Configure PIx pins speed to VERY_HIGH */
+ GPIOI->OSPEEDR = 0x003CFFFF;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* Configure PIx pins in Pull-up */
+ GPIOI->PUPDR = 0x00145555;
+
+ /*-- FMC Configuration ------------------------------------------------------*/
+
+ /* Enable the FMC/FSMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1_R->BTCR[4] = 0x00001091;
+ FMC_Bank1_R->BTCR[5] = 0x00110212;
+ FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
+
+ /* SDRAM Timing and access interface configuration */
+
+ /*SDBank = FMC_SDRAM_BANK2
+
+ ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9 CC
+ RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 RR
+ MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32 MM
+ InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 N
+ CASLatency = FMC_SDRAM_CAS_LATENCY_2 LL // 2 oder 3, s.u.
+ WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE W
+ SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 KK
+ ReadBurst = FMC_SDRAM_RBURST_ENABLE B
+ ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0 PP
+
+ LoadToActiveDelay = 2 -> 1 LLLL TMRD
+ ExitSelfRefreshDelay = 6 -> 5 EEEE TXSR
+ SelfRefreshTime = 4 -> 3 SSSS TRAS
+ RowCycleDelay = 6 -> 5 RRRR TRC
+ WriteRecoveryTime = 2 -> 1 WWWW TWR
+ RPDelay = 2 -> 1 PPPP TRP
+ RCDDelay = 2 -> 1 CCCC TRCD */
+
+ FMC_Bank5_6_R->SDCR[0] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 1
+ // PPB KKWL LNMM RRCC
+ FMC_Bank5_6_R->SDCR[1] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 2 // CAS Latency = 2
+ // WL LNMM RRCC
+
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000; // 0000 0000 0001 0000 0101 0000 0000 0000 Bank 1 // Original,
+ // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 2 (s.o.)
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351; // 0000 0001 0000 0001 0000 0011 0101 0001 Bank 2
+ // CCCC WWWW SSSS EEEE LLLL
+ #if 0
+ FMC_Bank5_6_R->SDTR[0] = 0x00206000; // 0000 0000 0010 0000 0110 0000 0000 0000 Bank 1 // Original + 1 bei allen Werten,
+ // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
+ FMC_Bank5_6_R->SDTR[1] = 0x02020462; // 0000 0010 0000 0010 0000 0100 0110 0010 Bank 2
+ // CCCC WWWW SSSS EEEE LLLL
+ #endif
+
+ #if 0
+ FMC_Bank5_6_R->SDTR[0] = 0x00209000; // 0000 0000 0010 0000 1001 0000 0000 0000 Bank 1 // Versuch anhand ISSI-Datenblatt,
+ // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
+ FMC_Bank5_6_R->SDTR[1] = 0x020306B1; // 0000 0010 0000 0011 0000 0110 1011 0001 Bank 2
+ // CCCC WWWW SSSS EEEE LLLL
+ #endif
+
+ /* SDRAM initialization sequence */
+
+ /* Clock enable command */
+ FMC_Bank5_6_R->SDCMR = 0x00000009;
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index=0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6_R->SDCMR = 0x0000000A;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x000000EB;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x0004400C;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6_R->SDRTR;
+ FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603 << 1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6_R->SDCR[1];
+ FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
+
+ /* Configure FMC Bank Mapping */
+ FMC_Bank1_R->BTCR[0] |= FMC_BMAP_Value;
+
+ /* FMC controller Enable */
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+
+ /********** SDRAM only *************************************************************************/
+
+ #elif defined (DATA_IN_ExtSDRAM)
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /*-- I/O Ports Configuration ------------------------------------------------------*/
+
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB4ENR |= 0x000001F8;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAFEAFFFA;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xF03F000F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x50150005;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABFFA;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554005;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCCC000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAABFFAAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFFC00FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55400555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0xC000000C;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xBFFEFAAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0xC0030FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x40010555;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0xCCC00000;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAAABFF;
+ /* Configure PHx pins speed to 100 MHz */
+ GPIOH->OSPEEDR = 0xFFFFFC00;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* Configure PHx pins in Pull-up */
+ GPIOH->PUPDR = 0x55555400;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0xFFEBAAAA;
+ /* Configure PIx pins speed to 100 MHz */
+ GPIOI->OSPEEDR = 0x003CFFFF;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* Configure PIx pins in Pull-up */
+ GPIOI->PUPDR = 0x00145555;
+
+ /*-- FMC Configuration ------------------------------------------------------*/
+
+ /* Enable the FMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+
+ /* SDRAM Timing and access interface configuration */
+
+ /*LoadToActiveDelay = 2
+ ExitSelfRefreshDelay = 6
+ SelfRefreshTime = 4
+ RowCycleDelay = 6
+ WriteRecoveryTime = 2
+ RPDelay = 2
+ RCDDelay = 2
+ SDBank = FMC_SDRAM_BANK2
+ ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
+ RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
+ MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
+ InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
+ CASLatency = FMC_SDRAM_CAS_LATENCY_2
+ WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
+ SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
+ ReadBurst = FMC_SDRAM_RBURST_ENABLE
+ ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
+
+ FMC_Bank5_6_R->SDCR[0] = 0x00001800;
+ FMC_Bank5_6_R->SDCR[1] = 0x00000165;
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000;
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6_R->SDCMR = 0x00000009;
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index=0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6_R->SDCMR = 0x0000000A;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x000000EB;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x0004400C;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6_R->SDRTR;
+ FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6_R->SDCR[1];
+ FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
+
+ /* FMC controller Enable */
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+ /********** SRAM only **************************************************************************/
+
+ #elif defined(DATA_IN_ExtSRAM)
+
+ /*-- I/O Ports Configuration -----------------------------------------------------*/
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB4ENR |= 0x00000078;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAAFABA;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0F0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x55550505;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABEBA;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554145;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAAFFFAAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55000555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x00000C00;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xFFEFFAAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x00300FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x00100555;
+
+ /*-- FMC/FSMC Configuration --------------------------------------------------*/
+
+ /* Enable the FMC/FSMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1_R->BTCR[4] = 0x00001091;
+ FMC_Bank1_R->BTCR[5] = 0x00110212;
+ FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
+
+ /* FMC controller Enable */
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+ #endif /* DATA_IN_ExtSRAM */
+
+ (void)(tmp);
+
+}
diff --git a/bsps/arm/stm32h7/start/getentropy-rng.c b/bsps/arm/stm32h7/start/getentropy-rng.c new file mode 100644 index 0000000000..7f75c2e915 --- /dev/null +++ b/bsps/arm/stm32h7/start/getentropy-rng.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stm32h7/hal.h> + +#include <rtems.h> +#include <rtems/sysinit.h> + +#include <sys/param.h> +#include <unistd.h> +#include <string.h> + +static RNG_HandleTypeDef stm32h7_rng_instance = { + .Instance = RNG, + .Init.ClockErrorDetection = RNG_CED_DISABLE +}; + +static void stm32h7_rng_enable(void) +{ + stm32h7_clk_enable(STM32H7_MODULE_RNG); + HAL_RNG_Init(&stm32h7_rng_instance); +} + +int getentropy(void *ptr, size_t n) +{ + while (n > 0) { + rtems_interrupt_level level; + uint32_t random; + bool ok; + size_t copy; + + do { + rtems_interrupt_disable(level); + + ok = (RNG->SR & RNG_FLAG_DRDY) != 0; + if (ok) { + random = RNG->DR; + } + + rtems_interrupt_enable(level); + } while (!ok); + + copy = MIN(sizeof(random), n); + ptr = memcpy(ptr, &random, copy); + n -= copy; + ptr += copy; + } + + return 0; +} + +RTEMS_SYSINIT_ITEM( + stm32h7_rng_enable, + RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c new file mode 100644 index 0000000000..874ad047db --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const uint32_t stm32h7_config_pwr_regulator_voltagescaling = + PWR_REGULATOR_VOLTAGE_SCALE0; + +const RCC_OscInitTypeDef stm32h7_config_oscillator = { + .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, + .HSEState = RCC_HSE_ON, + .LSEState = RCC_LSE_ON, + .HSIState = RCC_HSI_DIV1, + .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT, + .HSI48State = RCC_HSI48_ON, + .PLL.PLLState = RCC_PLL_ON, + .PLL.PLLSource = RCC_PLLSOURCE_HSE, + .PLL.PLLM = 5, + .PLL.PLLN = 192, + .PLL.PLLP = 2, + .PLL.PLLQ = 12, + .PLL.PLLR = 2, + .PLL.PLLRGE = RCC_PLL1VCIRANGE_2, + .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, + .PLL.PLLFRACN = 0 +}; + +const RCC_ClkInitTypeDef stm32h7_config_clocks = { + .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, + .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, + .SYSCLKDivider = RCC_SYSCLK_DIV1, + .AHBCLKDivider = RCC_HCLK_DIV2, + .APB3CLKDivider = RCC_APB3_DIV2, + .APB1CLKDivider = RCC_APB1_DIV2, + .APB2CLKDivider = RCC_APB2_DIV2, + .APB4CLKDivider = RCC_APB4_DIV2 +}; + +const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; + +const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { + .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 + | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, + .PLL2.PLL2M = 3, + .PLL2.PLL2N = 48, + .PLL2.PLL2P = 1, + .PLL2.PLL2Q = 2, + .PLL2.PLL2R = 2, + .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, + .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, + .PLL2.PLL2FRACN = 0, + .PLL3.PLL3M = 25, + .PLL3.PLL3N = 192, + .PLL3.PLL3P = 2, + .PLL3.PLL3Q = 4, + .PLL3.PLL3R = 2, + .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, + .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, + .PLL3.PLL3FRACN = 0, + .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, + .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, + .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, + .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, + .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, + .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, + .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, + .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-hal-eth.c b/bsps/arm/stm32h7/start/stm32h7-hal-eth.c new file mode 100644 index 0000000000..46475f4316 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-hal-eth.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +static const stm32h7_gpio_config gpiog = { + .regs = GPIOG, + .config = { + .Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_ETH + } +}; + +static const stm32h7_gpio_config gpioc = { + .regs = GPIOC, + .config = { + .Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_ETH + } +}; + +static const stm32h7_gpio_config gpioa = { + .regs = GPIOA, + .config = { + .Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_ETH + } +}; + +void +HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + stm32h7_clk_enable(STM32H7_MODULE_ETH1MAC); + stm32h7_clk_enable(STM32H7_MODULE_ETH1TX); + stm32h7_clk_enable(STM32H7_MODULE_ETH1RX); + stm32h7_gpio_init(&gpiog); + stm32h7_gpio_init(&gpioc); + stm32h7_gpio_init(&gpioa); +} diff --git a/bsps/arm/stm32h7/start/stm32h7-hal-uart.c b/bsps/arm/stm32h7/start/stm32h7-hal-uart.c new file mode 100644 index 0000000000..1cc94b22e3 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-hal-uart.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +void HAL_UART_MspInit(UART_HandleTypeDef *uart) +{ + stm32h7_uart_context *ctx; + const stm32h7_uart_config *config; + stm32h7_module_index index; + + ctx = (stm32h7_uart_context *) uart; + config = ctx->config; + index = stm32h7_get_module_index(ctx->uart.Instance); + stm32h7_clk_enable(index); + stm32h7_gpio_init(&config->gpio); +} diff --git a/bsps/arm/stm32h7/start/stm32h7-hal.c b/bsps/arm/stm32h7/start/stm32h7-hal.c new file mode 100644 index 0000000000..3dcc3098f4 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-hal.c @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#include <rtems.h> + +stm32h7_module_index stm32h7_get_module_index(const void *regs) +{ + switch ((uintptr_t) regs) { + case GPIOA_BASE: + return STM32H7_MODULE_GPIOA; + case GPIOB_BASE: + return STM32H7_MODULE_GPIOB; + case GPIOC_BASE: + return STM32H7_MODULE_GPIOC; + case GPIOD_BASE: + return STM32H7_MODULE_GPIOD; + case GPIOE_BASE: + return STM32H7_MODULE_GPIOE; + case GPIOF_BASE: + return STM32H7_MODULE_GPIOF; + case GPIOG_BASE: + return STM32H7_MODULE_GPIOG; + case GPIOH_BASE: + return STM32H7_MODULE_GPIOH; + case GPIOI_BASE: + return STM32H7_MODULE_GPIOI; + case GPIOJ_BASE: + return STM32H7_MODULE_GPIOJ; + case GPIOK_BASE: + return STM32H7_MODULE_GPIOK; + case USART1_BASE: + return STM32H7_MODULE_USART1; + case USART2_BASE: + return STM32H7_MODULE_USART2; + case USART3_BASE: + return STM32H7_MODULE_USART3; + case UART4_BASE: + return STM32H7_MODULE_UART4; + case UART5_BASE: + return STM32H7_MODULE_UART5; + case USART6_BASE: + return STM32H7_MODULE_USART6; + case UART7_BASE: + return STM32H7_MODULE_UART7; + case UART8_BASE: + return STM32H7_MODULE_UART8; +#ifdef UART9_BASE + case UART9_BASE: + return STM32H7_MODULE_UART9; +#endif +#ifdef USART10_BASE + case USART10_BASE: + return STM32H7_MODULE_USART10; +#endif + case RNG_BASE: + return STM32H7_MODULE_RNG; + } + + return STM32H7_MODULE_INVALID; +} + +typedef struct { + __IO uint32_t *enr; + uint32_t enable_bit; +} stm32h7_clk_info; + +static const stm32h7_clk_info stm32h7_clk[] = { + [STM32H7_MODULE_INVALID] = { NULL, 0 }, + [STM32H7_MODULE_GPIOA] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN }, + [STM32H7_MODULE_GPIOB] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN }, + [STM32H7_MODULE_GPIOC] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN }, + [STM32H7_MODULE_GPIOD] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN }, + [STM32H7_MODULE_GPIOE] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN }, + [STM32H7_MODULE_GPIOF] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN }, + [STM32H7_MODULE_GPIOG] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN }, + [STM32H7_MODULE_GPIOH] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN }, + [STM32H7_MODULE_GPIOI] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN }, + [STM32H7_MODULE_GPIOJ] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN }, + [STM32H7_MODULE_GPIOK] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN }, + [STM32H7_MODULE_USART1] = { &RCC->APB2ENR, RCC_APB2ENR_USART1EN }, + [STM32H7_MODULE_USART2] = { &RCC->APB1LENR, RCC_APB1LENR_USART2EN }, + [STM32H7_MODULE_USART3] = { &RCC->APB1LENR, RCC_APB1LENR_USART3EN }, + [STM32H7_MODULE_UART4] = { &RCC->APB1LENR, RCC_APB1LENR_UART4EN }, + [STM32H7_MODULE_UART5] = { &RCC->APB1LENR, RCC_APB1LENR_UART5EN }, + [STM32H7_MODULE_USART6] = { &RCC->APB2ENR, RCC_APB2ENR_USART6EN }, + [STM32H7_MODULE_UART7] = { &RCC->APB1LENR, RCC_APB1LENR_UART7EN }, + [STM32H7_MODULE_UART8] = { &RCC->APB1LENR, RCC_APB1LENR_UART8EN }, +#ifdef UART9_BASE + [STM32H7_MODULE_UART9] = { &RCC->APB2ENR, RCC_APB2ENR_UART9EN }, +#else + [STM32H7_MODULE_UART9] = { NULL, 0 }, +#endif +#ifdef USART10_BASE + [STM32H7_MODULE_USART10] = { &RCC->APB2ENR, RCC_APB2ENR_USART10EN }, +#else + [STM32H7_MODULE_USART10] = { NULL, 0 }, +#endif + [STM32H7_MODULE_RNG] = { &RCC->AHB2ENR, RCC_AHB2ENR_RNGEN }, + [STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN }, + [STM32H7_MODULE_ETH1TX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN }, + [STM32H7_MODULE_ETH1RX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN }, + [STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN }, + [STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN }, + [STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN }, + [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN } +}; + +void stm32h7_clk_enable(stm32h7_module_index index) +{ + __IO uint32_t *enr; + uint32_t enable_bit; + rtems_interrupt_level level; + + enr = stm32h7_clk[index].enr; + enable_bit = stm32h7_clk[index].enable_bit; + + rtems_interrupt_disable(level); + SET_BIT(*enr, enable_bit); + /* Delay after an RCC peripheral clock enabling */ + *enr; + rtems_interrupt_enable(level); +} + +void stm32h7_clk_disable(stm32h7_module_index index) +{ + __IO uint32_t *enr; + uint32_t enable_bit; + rtems_interrupt_level level; + + enr = stm32h7_clk[index].enr; + enable_bit = stm32h7_clk[index].enable_bit; + + rtems_interrupt_disable(level); + CLEAR_BIT(*enr, enable_bit); + rtems_interrupt_enable(level); +} + +static const stm32h7_clk_info stm32h7_clk_low_power[] = { + [STM32H7_MODULE_INVALID] = { NULL, 0 }, + [STM32H7_MODULE_GPIOA] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN }, + [STM32H7_MODULE_GPIOB] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN }, + [STM32H7_MODULE_GPIOC] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN }, + [STM32H7_MODULE_GPIOD] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN }, + [STM32H7_MODULE_GPIOE] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN }, + [STM32H7_MODULE_GPIOF] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN }, + [STM32H7_MODULE_GPIOG] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN }, + [STM32H7_MODULE_GPIOH] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN }, + [STM32H7_MODULE_GPIOI] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOILPEN }, + [STM32H7_MODULE_GPIOJ] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOJLPEN }, + [STM32H7_MODULE_GPIOK] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOKLPEN }, + [STM32H7_MODULE_USART1] = { &RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN }, + [STM32H7_MODULE_USART2] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN }, + [STM32H7_MODULE_USART3] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN }, + [STM32H7_MODULE_UART4] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN }, + [STM32H7_MODULE_UART5] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN }, + [STM32H7_MODULE_USART6] = { &RCC->APB2LPENR, RCC_APB2LPENR_USART6LPEN }, + [STM32H7_MODULE_UART7] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN }, + [STM32H7_MODULE_UART8] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN }, +#ifdef UART9_BASE + [STM32H7_MODULE_UART9] = { &RCC->APB2LPENR, RCC_APB2LPENR_UART9LPEN }, +#else + [STM32H7_MODULE_UART9] = { NULL, 0 }, +#endif +#ifdef USART10_BASE + [STM32H7_MODULE_USART10] = { &RCC->APB2LPENR, RCC_APB2LPENR_USART10LPEN }, +#else + [STM32H7_MODULE_USART10] = { NULL, 0 }, +#endif + [STM32H7_MODULE_RNG] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN }, + [STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN }, + [STM32H7_MODULE_ETH1TX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN }, + [STM32H7_MODULE_ETH1RX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN }, + [STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSLPEN }, + [STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSULPILPEN }, + [STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSLPEN }, + [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN } +}; + +void stm32h7_clk_low_power_enable(stm32h7_module_index index) +{ + __IO uint32_t *enr; + uint32_t enable_bit; + rtems_interrupt_level level; + + enr = stm32h7_clk_low_power[index].enr; + enable_bit = stm32h7_clk_low_power[index].enable_bit; + + rtems_interrupt_disable(level); + SET_BIT(*enr, enable_bit); + /* Delay after an RCC peripheral clock enabling */ + *enr; + rtems_interrupt_enable(level); +} + +void stm32h7_clk_low_power_disable(stm32h7_module_index index) +{ + __IO uint32_t *enr; + uint32_t enable_bit; + rtems_interrupt_level level; + + enr = stm32h7_clk_low_power[index].enr; + enable_bit = stm32h7_clk_low_power[index].enable_bit; + + rtems_interrupt_disable(level); + CLEAR_BIT(*enr, enable_bit); + rtems_interrupt_enable(level); +} + +void stm32h7_gpio_init(const stm32h7_gpio_config *config) +{ + stm32h7_module_index index; + + index = stm32h7_get_module_index(config->regs); + stm32h7_clk_enable(index); + HAL_GPIO_Init(config->regs, &config->config); +} + +void stm32h7_uart_polled_write(rtems_termios_device_context *base, char c) +{ + stm32h7_uart_context *ctx; + USART_TypeDef *regs; + + ctx = stm32h7_uart_get_context(base); + regs = ctx->uart.Instance; + + while ((regs->ISR & USART_ISR_TXE_TXFNF) == 0) { + /* Wait */ + } + + regs->TDR = (uint8_t) c; +} + +int stm32h7_uart_polled_read(rtems_termios_device_context *base) +{ + stm32h7_uart_context *ctx; + USART_TypeDef *regs; + + ctx = stm32h7_uart_get_context(base); + regs = ctx->uart.Instance; + + if ((regs->ISR & USART_ISR_RXNE_RXFNE) == 0) { + return -1; + } + + return (uint8_t) regs->RDR; +} diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c b/bsps/arm/stm32h7/start/system_stm32h7xx.c new file mode 100644 index 0000000000..092d853720 --- /dev/null +++ b/bsps/arm/stm32h7/start/system_stm32h7xx.c @@ -0,0 +1,416 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+#ifdef __rtems__
+#include <bsp/linker-symbols.h>
+#endif /* __rtems__ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+#ifndef __rtems__
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+#else /* __rtems__ */
+ RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
+ RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
+#endif /* __rtems__ */
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+#if defined(D3_SRAM_BASE)
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+#else
+ /* Reset CDCFGR1 register */
+ RCC->CDCFGR1 = 0x00000000;
+
+ /* Reset CDCFGR2 register */
+ RCC->CDCFGR2 = 0x00000000;
+
+ /* Reset SRDCFGR register */
+ RCC->SRDCFGR = 0x00000000;
+#endif
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x00000000;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x00000000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x00000000;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x00000000;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x00000000;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+ /* dual core CM7 or single core line */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+#endif
+
+#ifndef __rtems__
+#if defined (DATA_IN_D2_SRAM)
+ /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+ RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+ tmpreg = RCC->AHB2ENR;
+ (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+#else /* __rtems__ */
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+ RCC->AHB2ENR;
+#endif /* __rtems__ */
+
+#ifndef __rtems__
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+ /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+#else
+ SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#endif /*DUAL_CORE && CORE_CM4*/
+#else /* __rtems__ */
+ SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
+#endif /* __rtems__ */
+
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = CSI_VALUE;
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+ tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/spec/build/bsps/arm/stm32h7/.doorstop.yml b/spec/build/bsps/arm/stm32h7/.doorstop.yml new file mode 100644 index 0000000000..16950ce80f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/.doorstop.yml @@ -0,0 +1,6 @@ +settings: + digits: 3 + parent: RTEMS-BUILD-BSP-ARM + prefix: RTEMS-BUILD-BSP-ARM-STM32H7 + sep: '-' +attributes: !include ../../../attributes.inc diff --git a/spec/build/bsps/arm/stm32h7/abi.yml b/spec/build/bsps/arm/stm32h7/abi.yml new file mode 100644 index 0000000000..697220b1b1 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/abi.yml @@ -0,0 +1,20 @@ +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +default: +- -mthumb +- -mcpu=cortex-m7 +- -mfpu=fpv5-d16 +- -mfloat-abi=hard +default-by-variant: [] +enabled-by: true +links: [] +name: ABI_FLAGS +description: | + ABI flags +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml new file mode 100644 index 0000000000..9fb7d3611f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -0,0 +1,415 @@ +arch: arm +bsp: stm32h7 +build-type: bsp +cflags: [] +cppflags: [] +enabled-by: true +family: stm32h7 +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/stm32h7/include/bsp.h + - bsps/arm/stm32h7/include/tm27.h + - bsps/arm/stm32h7/include/chip.h + - bsps/arm/stm32h7/include/stm32_assert_template.h + - bsps/arm/stm32h7/include/stm32h742xx.h + - bsps/arm/stm32h7/include/stm32h743xx.h + - bsps/arm/stm32h7/include/stm32h745xx.h + - bsps/arm/stm32h7/include/stm32h747xx.h + - bsps/arm/stm32h7/include/stm32h750xx.h + - bsps/arm/stm32h7/include/stm32h753xx.h + - bsps/arm/stm32h7/include/stm32h755xx.h + - bsps/arm/stm32h7/include/stm32h757xx.h + - bsps/arm/stm32h7/include/stm32h7a3xx.h + - bsps/arm/stm32h7/include/stm32h7a3xxq.h + - bsps/arm/stm32h7/include/stm32h7b0xx.h + - bsps/arm/stm32h7/include/stm32h7b0xxq.h + - bsps/arm/stm32h7/include/stm32h7b3xx.h + - bsps/arm/stm32h7/include/stm32h7b3xxq.h + - bsps/arm/stm32h7/include/stm32h7/hal.h + - bsps/arm/stm32h7/include/stm32h7xx.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_adc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_adc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cec.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_comp.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_conf_template.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cortex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_crc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_crc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cryp_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cryp.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dac_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dac.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dcmi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_def.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dma2d.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dma_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dma.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dsi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dts.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_eth_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_eth.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_exti.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_fdcan.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_flash.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_gfxmmu.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_gpio_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_gpio.h + - bsps/arm/stm32h7/include/stm32h7xx_hal.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hash_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hash.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hcd.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hrtim.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hsem.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2c_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2c.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2s_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2s.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_irda_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_irda.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_iwdg.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_jpeg.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_lptim.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mdios.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mdma.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mmc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mmc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_nand.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_nor.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_opamp_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_opamp.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_otfdec.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pcd_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pcd.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pssi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pwr_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_qspi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ramecc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rcc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rcc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rng_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rng.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rtc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rtc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sai_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sai.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sd_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sd.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sdram.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_smbus.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_spdifrx.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_spi_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sram.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_swpmi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_tim_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_tim.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_uart_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_usart_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_usart.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_wwdg.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_bdma.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_bus.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_comp.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_crc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_crs.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dac.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_delayblock.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dma2d.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dmamux.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_exti.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_gpio.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_hrtim.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_hsem.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_i2c.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_iwdg.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_lptim.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_lpuart.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_mdma.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_opamp.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_rcc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_rng.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_rtc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_sdmmc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_swpmi.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_system.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_tim.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_usart.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_usb.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_utils.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_wwdg.h + - bsps/arm/stm32h7/include/system_stm32h7xx.h +- destination: ${BSP_INCLUDEDIR}/Legacy + source: + - bsps/arm/stm32h7/include/Legacy/stm32_hal_legacy.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/stm32h7/include/bsp/irq.h +- destination: ${BSP_INCLUDEDIR}/stm32h7 + source: + - bsps/arm/stm32h7/include/stm32h7/hal.h + - bsps/arm/stm32h7/include/stm32h7/memory.h +- destination: ${BSP_LIBDIR} + source: + - bsps/arm/stm32h7/start/bsp_specs +links: +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: abi +- role: build-dependency + uid: optenmpualign +- role: build-dependency + uid: optenuart4 +- role: build-dependency + uid: optenuart5 +- role: build-dependency + uid: optenuart7 +- role: build-dependency + uid: optenuart8 +- role: build-dependency + uid: optenuart9 +- role: build-dependency + uid: optenusart10 +- role: build-dependency + uid: optenusart1 +- role: build-dependency + uid: optenusart2 +- role: build-dependency + uid: optenusart3 +- role: build-dependency + uid: optenusart6 +- role: build-dependency + uid: optlinkcmds +- role: build-dependency + uid: optmemdtcmsz +- role: build-dependency + uid: optmemflashsz +- role: build-dependency + uid: optmemitcmsz +- role: build-dependency + uid: optmemnandsz +- role: build-dependency + uid: optmemnorsz +- role: build-dependency + uid: optmemnullsz +- role: build-dependency + uid: optmemperipheralsz +- role: build-dependency + uid: optmemquadspisz +- role: build-dependency + uid: optmemsdram1sz +- role: build-dependency + uid: optmemsdram2sz +- role: build-dependency + uid: optmemsram1sz +- role: build-dependency + uid: optmemsram2sz +- role: build-dependency + uid: optmemsram3sz +- role: build-dependency + uid: optmemsram4sz +- role: build-dependency + uid: optmemsramaxisz +- role: build-dependency + uid: optmemsrambackupsz +- role: build-dependency + uid: optprintkinstance +- role: build-dependency + uid: optvariant +- role: build-dependency + uid: ../../optconsolebaud +- role: build-dependency + uid: ../../optconsoleirq +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: linkcmdsflash +- role: build-dependency + uid: linkcmdsmemory +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: linkcmdssdram +- role: build-dependency + uid: ../../bspopts +source: +- bsps/arm/shared/cache/cache-v7m.c +- bsps/arm/shared/clock/clock-armv7m.c +- bsps/arm/shared/cpucounter/cpucounter-armv7m.c +- bsps/arm/shared/irq/irq-armv7m.c +- bsps/arm/shared/irq/irq-dispatch-armv7m.c +- bsps/arm/shared/start/bspreset-armv7m.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/stm32h7/console/console.c +- bsps/arm/stm32h7/console/console-uart4.c +- bsps/arm/stm32h7/console/console-uart5.c +- bsps/arm/stm32h7/console/console-uart7.c +- bsps/arm/stm32h7/console/console-uart8.c +- bsps/arm/stm32h7/console/console-uart9.c +- bsps/arm/stm32h7/console/console-usart10.c +- bsps/arm/stm32h7/console/console-usart1.c +- bsps/arm/stm32h7/console/console-usart2.c +- bsps/arm/stm32h7/console/console-usart3.c +- bsps/arm/stm32h7/console/console-usart6.c +- bsps/arm/stm32h7/console/printk-support.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_adc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_adc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cec.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_comp.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cortex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_crc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_crc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cryp.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cryp_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dac.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dac_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dcmi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dfsdm.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dfsdm_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dma2d.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dma.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dma_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dsi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dts.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_eth.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_eth_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_exti.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_fdcan.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_flash.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_gfxmmu.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_gpio.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hash.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hash_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hcd.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hrtim.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hsem.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2c.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2c_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2s.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2s_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_irda.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_iwdg.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_jpeg.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_lptim.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ltdc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ltdc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mdios.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mdma.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mmc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mmc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_nand.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_nor.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_opamp.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_opamp_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ospi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_otfdec.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pcd.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pcd_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pssi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pwr.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pwr_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_qspi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ramecc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rcc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rcc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rng.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rng_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rtc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rtc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sai.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sai_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sd.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sd_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sdram.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_smartcard.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_smartcard_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_smbus.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_spdifrx.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_spi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_spi_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sram.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_swpmi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_tim.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_tim_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_uart.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_uart_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_usart.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_usart_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_wwdg.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_adc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_bdma.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_comp.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_crc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_crs.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_dac.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_delayblock.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_dma2d.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_dma.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_exti.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_fmc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_gpio.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_hrtim.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_i2c.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_lptim.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_lpuart.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_mdma.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_opamp.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_pwr.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_rng.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_rtc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_sdmmc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_spi.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_swpmi.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_tim.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_usart.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_usb.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_utils.c +- bsps/arm/stm32h7/start/bspstart.c +- bsps/arm/stm32h7/start/bspstarthooks.c +- bsps/arm/stm32h7/start/ext-mem-ctl.c +- bsps/arm/stm32h7/start/getentropy-rng.c +- bsps/arm/stm32h7/start/stm32h7-config.c +- bsps/arm/stm32h7/start/stm32h7-hal.c +- bsps/arm/stm32h7/start/stm32h7-hal-eth.c +- bsps/arm/stm32h7/start/stm32h7-hal-uart.c +- bsps/arm/stm32h7/start/system_stm32h7xx.c +- bsps/shared/dev/btimer/btimer-stub.c +- bsps/shared/dev/rtc/rtc-support.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/bspgetworkarea-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmds.yml b/spec/build/bsps/arm/stm32h7/linkcmds.yml new file mode 100644 index 0000000000..95f31bbedb --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmds.yml @@ -0,0 +1,11 @@ +build-type: config-file +content: | + INCLUDE ${STM32H7_DEFAULT_LINKCMDS} +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsflash.yml b/spec/build/bsps/arm/stm32h7/linkcmdsflash.yml new file mode 100644 index 0000000000..405c6e6d20 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmdsflash.yml @@ -0,0 +1,49 @@ +build-type: script +do-build: | + bld.install_as("${BSP_LIBDIR}/linkcmds.flash", "linkcmds.flash") +do-configure: | + content = """INCLUDE linkcmds.memory + + REGION_ALIAS ("REGION_START", FLASH); + REGION_ALIAS ("REGION_VECTOR", FLASH); + REGION_ALIAS ("REGION_TEXT", FLASH); + REGION_ALIAS ("REGION_TEXT_LOAD", FLASH); + REGION_ALIAS ("REGION_RODATA", FLASH); + REGION_ALIAS ("REGION_RODATA_LOAD", FLASH); + REGION_ALIAS ("REGION_DATA", SRAM_AXI); + REGION_ALIAS ("REGION_DATA_LOAD", FLASH); + REGION_ALIAS ("REGION_FAST_TEXT", ITCM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ITCM); + REGION_ALIAS ("REGION_FAST_DATA", DTCM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", DTCM); + REGION_ALIAS ("REGION_BSS", SRAM_AXI); + REGION_ALIAS ("REGION_WORK", SRAM_AXI); + REGION_ALIAS ("REGION_STACK", SRAM_AXI); + REGION_ALIAS ("REGION_NOCACHE", SRAM_1); + REGION_ALIAS ("REGION_NOCACHE_LOAD", FLASH); + + bsp_vector_table_in_start_section = 1; + """ + + if conf.env.STM32H7_ENABLE_MPU_ALIGNMENT: + content += """ + bsp_section_do_mpu_align = 1; + """ + + content += """ + INCLUDE linkcmds.armv7m + """ + f = conf.bldnode.make_node( + conf.env.VARIANT + "/linkcmds.flash" + ) + f.parent.mkdir() + f.write(content) + conf.env.append_value("cfg_files", f.abspath()) +enabled-by: true +links: [] +prepare-build: null +prepare-configure: null +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml new file mode 100644 index 0000000000..7ff7f3da5e --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml @@ -0,0 +1,92 @@ +build-type: config-file +content: | + MEMORY { + NULL : ORIGIN = 0x00000000, LENGTH = ${STM32H7_MEMORY_NULL_SIZE:#010x} + ITCM : ORIGIN = ${STM32H7_MEMORY_NULL_SIZE:#010x}, LENGTH = ${STM32H7_MEMORY_ITCM_SIZE:#010x} + FLASH : ORIGIN = 0x08000000, LENGTH = ${STM32H7_MEMORY_FLASH_SIZE:#010x} + DTCM : ORIGIN = 0x20000000, LENGTH = ${STM32H7_MEMORY_DTCM_SIZE:#010x} + SRAM_AXI : ORIGIN = 0x24000000, LENGTH = ${STM32H7_MEMORY_SRAM_AXI_SIZE:#010x} + SRAM_1 : ORIGIN = 0x30000000, LENGTH = ${STM32H7_MEMORY_SRAM_1_SIZE:#010x} + SRAM_2 : ORIGIN = 0x30020000, LENGTH = ${STM32H7_MEMORY_SRAM_2_SIZE:#010x} + SRAM_3 : ORIGIN = 0x30040000, LENGTH = ${STM32H7_MEMORY_SRAM_3_SIZE:#010x} + SRAM_4 : ORIGIN = 0x38000000, LENGTH = ${STM32H7_MEMORY_SRAM_4_SIZE:#010x} + SRAM_BACKUP : ORIGIN = 0x38800000, LENGTH = ${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x} + PERIPHERAL : ORIGIN = 0x40000000, LENGTH = ${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x} + NOR : ORIGIN = 0x60000000, LENGTH = ${STM32H7_MEMORY_NOR_SIZE:#010x} + SDRAM_1 : ORIGIN = 0x70000000, LENGTH = ${STM32H7_MEMORY_SDRAM_1_SIZE:#010x} + NAND : ORIGIN = 0x80000000, LENGTH = ${STM32H7_MEMORY_NAND_SIZE:#010x} + QUADSPI : ORIGIN = 0x90000000, LENGTH = ${STM32H7_MEMORY_QUADSPI_SIZE:#010x} + SDRAM_2 : ORIGIN = 0xd0000000, LENGTH = ${STM32H7_MEMORY_SDRAM_2_SIZE:#010x} + } + + stm32h7_memory_null_begin = ORIGIN (NULL); + stm32h7_memory_null_end = ORIGIN (NULL) + LENGTH (NULL); + stm32h7_memory_null_size = LENGTH (NULL); + + stm32h7_memory_itcm_begin = ORIGIN (ITCM); + stm32h7_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM); + stm32h7_memory_itcm_size = LENGTH (ITCM); + + stm32h7_memory_flash_begin = ORIGIN (FLASH); + stm32h7_memory_flash_end = ORIGIN (FLASH) + LENGTH (FLASH); + stm32h7_memory_flash_size = LENGTH (FLASH); + + stm32h7_memory_dtcm_begin = ORIGIN (DTCM); + stm32h7_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM); + stm32h7_memory_dtcm_size = LENGTH (DTCM); + + stm32h7_memory_sram_axi_begin = ORIGIN (SRAM_AXI); + stm32h7_memory_sram_axi_end = ORIGIN (SRAM_AXI) + LENGTH (SRAM_AXI); + stm32h7_memory_sram_axi_size = LENGTH (SRAM_AXI); + + stm32h7_memory_sram_1_begin = ORIGIN (SRAM_1); + stm32h7_memory_sram_1_end = ORIGIN (SRAM_1) + LENGTH (SRAM_1); + stm32h7_memory_sram_1_size = LENGTH (SRAM_1); + + stm32h7_memory_sram_2_begin = ORIGIN (SRAM_2); + stm32h7_memory_sram_2_end = ORIGIN (SRAM_2) + LENGTH (SRAM_2); + stm32h7_memory_sram_2_size = LENGTH (SRAM_2); + + stm32h7_memory_sram_3_begin = ORIGIN (SRAM_3); + stm32h7_memory_sram_3_end = ORIGIN (SRAM_3) + LENGTH (SRAM_3); + stm32h7_memory_sram_3_size = LENGTH (SRAM_3); + + stm32h7_memory_sram_4_begin = ORIGIN (SRAM_4); + stm32h7_memory_sram_4_end = ORIGIN (SRAM_4) + LENGTH (SRAM_4); + stm32h7_memory_sram_4_size = LENGTH (SRAM_4); + + stm32h7_memory_sram_backup_begin = ORIGIN (SRAM_BACKUP); + stm32h7_memory_sram_backup_end = ORIGIN (SRAM_BACKUP) + LENGTH (SRAM_BACKUP); + stm32h7_memory_sram_backup_size = LENGTH (SRAM_BACKUP); + + stm32h7_memory_peripheral_begin = ORIGIN (PERIPHERAL); + stm32h7_memory_peripheral_end = ORIGIN (PERIPHERAL) + LENGTH (PERIPHERAL); + stm32h7_memory_peripheral_size = LENGTH (PERIPHERAL); + + stm32h7_memory_nor_begin = ORIGIN (NOR); + stm32h7_memory_nor_end = ORIGIN (NOR) + LENGTH (NOR); + stm32h7_memory_nor_size = LENGTH (NOR); + + stm32h7_memory_sdram_1_begin = ORIGIN (SDRAM_1); + stm32h7_memory_sdram_1_end = ORIGIN (SDRAM_1) + LENGTH (SDRAM_1); + stm32h7_memory_sdram_1_size = LENGTH (SDRAM_1); + + stm32h7_memory_nand_begin = ORIGIN (NAND); + stm32h7_memory_nand_end = ORIGIN (NAND) + LENGTH (NAND); + stm32h7_memory_nand_size = LENGTH (NAND); + + stm32h7_memory_quadspi_begin = ORIGIN (QUADSPI); + stm32h7_memory_quadspi_end = ORIGIN (QUADSPI) + LENGTH (QUADSPI); + stm32h7_memory_quadspi_size = LENGTH (QUADSPI); + + stm32h7_memory_sdram_2_begin = ORIGIN (SDRAM_2); + stm32h7_memory_sdram_2_end = ORIGIN (SDRAM_2) + LENGTH (SDRAM_2); + stm32h7_memory_sdram_2_size = LENGTH (SDRAM_2); +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds.memory +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmdssdram.yml b/spec/build/bsps/arm/stm32h7/linkcmdssdram.yml new file mode 100644 index 0000000000..c017610cff --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmdssdram.yml @@ -0,0 +1,49 @@ +build-type: script +do-build: | + bld.install_as("${BSP_LIBDIR}/linkcmds.sdram", "linkcmds.sdram") +do-configure: | + content = """INCLUDE linkcmds.memory + + REGION_ALIAS ("REGION_START", SDRAM_1); + REGION_ALIAS ("REGION_VECTOR", SDRAM_1); + REGION_ALIAS ("REGION_TEXT", SDRAM_1); + REGION_ALIAS ("REGION_TEXT_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_RODATA", SDRAM_1); + REGION_ALIAS ("REGION_RODATA_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_DATA", SDRAM_1); + REGION_ALIAS ("REGION_DATA_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_FAST_TEXT", ITCM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_FAST_DATA", DTCM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_BSS", SDRAM_1); + REGION_ALIAS ("REGION_WORK", SDRAM_1); + REGION_ALIAS ("REGION_STACK", SRAM_AXI); + REGION_ALIAS ("REGION_NOCACHE", SRAM_1); + REGION_ALIAS ("REGION_NOCACHE_LOAD", SDRAM_1); + + bsp_vector_table_in_start_section = 1; + """ + + if conf.env.STM32H7_ENABLE_MPU_ALIGNMENT: + content += """ + bsp_section_do_mpu_align = 1; + """ + + content += """ + INCLUDE linkcmds.armv7m + """ + f = conf.bldnode.make_node( + conf.env.VARIANT + "/linkcmds.sdram" + ) + f.parent.mkdir() + f.write(content) + conf.env.append_value("cfg_files", f.abspath()) +enabled-by: true +links: [] +prepare-build: null +prepare-configure: null +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenmpualign.yml b/spec/build/bsps/arm/stm32h7/optenmpualign.yml new file mode 100644 index 0000000000..4005485940 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenmpualign.yml @@ -0,0 +1,20 @@ +actions: +- get-boolean: null +- env-assign: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_ENABLE_MPU_ALIGNMENT +description: | + Enable the alignment of the size of the combined start and text sections and + the rodata section to meet MPU region alignment requirements. This increases + the memory footprint. It enables a write-protection of the start, text, and + rodata sections. It makes the data sections non-executable. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart4.yml b/spec/build/bsps/arm/stm32h7/optenuart4.yml new file mode 100644 index 0000000000..cd5fd31370 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart4.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART4 +description: | + Enable UART4 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart5.yml b/spec/build/bsps/arm/stm32h7/optenuart5.yml new file mode 100644 index 0000000000..f124d72113 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart5.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART5 +description: | + Enable UART5 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart7.yml b/spec/build/bsps/arm/stm32h7/optenuart7.yml new file mode 100644 index 0000000000..7310cef713 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart7.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART7 +description: | + Enable UART7 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart8.yml b/spec/build/bsps/arm/stm32h7/optenuart8.yml new file mode 100644 index 0000000000..f0407f6510 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart8.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART8 +description: | + Enable UART8 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart9.yml b/spec/build/bsps/arm/stm32h7/optenuart9.yml new file mode 100644 index 0000000000..1a3ef49459 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart9.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART9 +description: | + Enable UART9 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart1.yml b/spec/build/bsps/arm/stm32h7/optenusart1.yml new file mode 100644 index 0000000000..a4f478f753 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart1.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART1 +description: | + Enable USART1 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart10.yml b/spec/build/bsps/arm/stm32h7/optenusart10.yml new file mode 100644 index 0000000000..659d1a96b6 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart10.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART10 +description: | + Enable USART10 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart2.yml b/spec/build/bsps/arm/stm32h7/optenusart2.yml new file mode 100644 index 0000000000..0bbec65278 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart2.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART2 +description: | + Enable USART2 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart3.yml b/spec/build/bsps/arm/stm32h7/optenusart3.yml new file mode 100644 index 0000000000..09e673ff7f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart3.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART3 +description: | + Enable USART3 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart6.yml b/spec/build/bsps/arm/stm32h7/optenusart6.yml new file mode 100644 index 0000000000..e6524fd40d --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart6.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART6 +description: | + Enable USART6 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml new file mode 100644 index 0000000000..d0bb033cef --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml @@ -0,0 +1,17 @@ +actions: +- get-string: null +- env-assign: null +build-type: option +default: linkcmds.sdram +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_DEFAULT_LINKCMDS +description: | + The default linker command file. Must be either linkcmds.flash or + linkcmds.sdram. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml b/spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml new file mode 100644 index 0000000000..e7c1a2bdf6 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_DTCM_SIZE +description: | + Size of the Data Tightly Coupled Memory (DTCM) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemflashsz.yml b/spec/build/bsps/arm/stm32h7/optmemflashsz.yml new file mode 100644 index 0000000000..627543f9a8 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemflashsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x200000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_FLASH_SIZE +description: | + Size of the internal flash in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemitcmsz.yml b/spec/build/bsps/arm/stm32h7/optmemitcmsz.yml new file mode 100644 index 0000000000..610de5f074 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemitcmsz.yml @@ -0,0 +1,18 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0xff00 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_ITCM_SIZE +description: | + Size of the Instruction Tightly Coupled Memory (ITCM) in bytes. The size + must take the NULL pointer protection memory area into account + (STM32H7_MEMORY_NULL_SIZE). +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemnandsz.yml b/spec/build/bsps/arm/stm32h7/optmemnandsz.yml new file mode 100644 index 0000000000..0bfbcc4623 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemnandsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_NAND_SIZE +description: | + Size of the NAND flash in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemnorsz.yml b/spec/build/bsps/arm/stm32h7/optmemnorsz.yml new file mode 100644 index 0000000000..d41d4e9e49 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemnorsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_NOR_SIZE +description: | + Size of the NOR flash or PSRAM in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemnullsz.yml b/spec/build/bsps/arm/stm32h7/optmemnullsz.yml new file mode 100644 index 0000000000..a31169adb1 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemnullsz.yml @@ -0,0 +1,17 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 256 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_NULL_SIZE +description: | + Size of the NULL pointer protection area in bytes. This memory area reduces + the size of the ITCM available to the application (STM32H7_MEMORY_ITCM_SIZE). +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml b/spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml new file mode 100644 index 0000000000..0a1bd610e7 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_PERIPHERAL_SIZE +description: | + Size of the peripheral memory in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml b/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml new file mode 100644 index 0000000000..11e5f943e0 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_QUADSPI_SIZE +description: | + Size of the QUADSPI memory in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml new file mode 100644 index 0000000000..11228ddb92 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 33554432 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SDRAM_1_SIZE +description: | + Size of the SDRAM 1 in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml new file mode 100644 index 0000000000..5a1ffdcace --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SDRAM_2_SIZE +description: | + Size of the SDRAM 2 in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml new file mode 100644 index 0000000000..01e9dbe1cc --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_1_SIZE +description: | + Size of the SRAM 1 (D2 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml new file mode 100644 index 0000000000..2a4890730a --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_2_SIZE +description: | + Size of the SRAM 2 (D2 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml new file mode 100644 index 0000000000..eca335fd81 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x8000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_3_SIZE +description: | + Size of the SRAM 3 (D2 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml new file mode 100644 index 0000000000..cda2e722a4 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x10000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_4_SIZE +description: | + Size of the SRAM 4 (D3 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml b/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml new file mode 100644 index 0000000000..9cb05540b7 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x80000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_AXI_SIZE +description: | + Size of the AXI SRAM (D1 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml b/spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml new file mode 100644 index 0000000000..f1c5f60bac --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x1000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_BACKUP_SIZE +description: | + Size of backup SRAM in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optprintkinstance.yml b/spec/build/bsps/arm/stm32h7/optprintkinstance.yml new file mode 100644 index 0000000000..6eaf4a2011 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optprintkinstance.yml @@ -0,0 +1,16 @@ +actions: +- get-string: null +- define-unquoted: null +build-type: option +default: stm32h7_usart1_instance +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_PRINTK_INSTANCE +description: | + UART/USART instance used for printk() and getchark(). +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optvariant.yml b/spec/build/bsps/arm/stm32h7/optvariant.yml new file mode 100644 index 0000000000..586fa2052b --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optvariant.yml @@ -0,0 +1,29 @@ +actions: +- get-string: null +- script: | + variants = ["STM32H742xx", "STM32H743xx", "STM32H745xx", "STM32H747xx", + "STM32H750xx", "STM32H753xx", "STM32H755xx", "STM32H757xx", "STM32H7A3xx", + "STM32H7A3xxQ", "STM32H7B0xx", "STM32H7B0xxQ", "STM32H7B3xx", "STM32H7B3xxQ"] + if value not in variants: + conf.fatal( + "STM32H7 chip variant '{}' is not one of {}".format( + value, variants + ) + ) + conf.define_cond(value, True) +build-type: option +default: STM32H743xx +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_VARIANT +description: | + Select the STM32H7 series chip variant out of STM32H742xx, STM32H743xx, + STM32H745xx, STM32H747xx, STM32H750xx, STM32H753xx, STM32H755xx, STM32H757xx, + STM32H7A3xx, STM32H7A3xxQ, STM32H7B0xx, STM32H7B0xxQ, STM32H7B3xx, and + STM32H7B3xxQ. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) |