bsp/xm_tms570: New BSPxtratum-4.11

6 files changed, 71 insertions, 0 deletions

diff --git a/cpukit/score/cpu/arm/arm_exc_abort.S b/cpukit/score/cpu/arm/arm_exc_abort.S
index 0f5d414c42..45c86a042f 100644
--- a/cpukit/score/cpu/arm/arm_exc_abort.S
+++ b/cpukit/score/cpu/arm/arm_exc_abort.S
@@ -129,6 +129,9 @@ save_more_context:
 	add	sp, #20
 
 	/* Return from interrupt */
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#10
+#endif        
 	subs	pc, lr, #8
 
 #ifdef __thumb__
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S
index fcb1510b95..2a3a3723bd 100644
--- a/cpukit/score/cpu/arm/arm_exc_interrupt.S
+++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S
@@ -57,12 +57,21 @@ _ARMV4_Exception_interrupt:
 
 	/* Set exchange registers */
 	mov	EXCHANGE_LR, lr
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#4
+#endif
 	mrs	EXCHANGE_SPSR, SPSR
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#4
+#endif
 	mrs	EXCHANGE_CPSR, CPSR
 	sub	EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE
 
 	/* Switch to SVC mode */
 	orr	EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#5
+#endif
 	msr	CPSR_c, EXCHANGE_CPSR
 
 	/*
@@ -190,10 +199,16 @@ thread_dispatch_done:
 	add	sp, #CONTEXT_SIZE
 
 	/* Get INT mode program status register */
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#4
+#endif
 	mrs	r1, CPSR
 	bic	r1, r1, #0x1
 
 	/* Switch to INT mode */
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#5
+#endif
 	msr	CPSR_c, r1
 
 	/* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */
@@ -204,6 +219,9 @@ thread_dispatch_done:
 
 	/* Set return address and program status */
 	mov	lr, EXCHANGE_LR
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#5
+#endif
 	msr	SPSR_fsxc, EXCHANGE_SPSR
 
 	/* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */
@@ -237,6 +255,9 @@ thread_dispatch_done:
 #endif
 
 	/* Return from interrupt */
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf	#10
+#endif
 	subs	pc, lr, #4
 
 #endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S
index a10de301b0..763913b09e 100644
--- a/cpukit/score/cpu/arm/armv4-exception-default.S
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -103,21 +103,39 @@ _ARMV4_Exception_fiq_default:
 	 * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
 	 * (which we'll load into the CPSR in save_more_context).
 	 */
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf #4
+#endif
 	mrs r2, spsr
 	orr r2, #ARM_PSR_F
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf #5
+#endif
 	msr spsr_c, r2
 
 save_more_context:
 
 	/* Save more context */
 	mov	r2, lr
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf #4
+#endif
 	mrs	r3, spsr
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf #4
+#endif
 	mrs	r7, cpsr
 	orr	r5, r3, #ARM_PSR_I
 	bic	r5, #ARM_PSR_T
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf #5
+#endif
 	msr	cpsr, r5
 	mov	r0, sp
 	mov	r1, lr
+#ifdef RTEMS_PARAVIRT_XTRATUM
+	udf #5
+#endif
 	msr	cpsr, r7
 	mov	r5, #0
 	add	r6, sp, #ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index ddfc37d243..42c9eacfff 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -127,9 +127,15 @@ void _CPU_ISR_Set_level( uint32_t level )
 
   __asm__ volatile (
     ARM_SWITCH_TO_ARM
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #4\n"
+#endif
     "mrs %[arm_switch_reg], cpsr\n"
     "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( ARM_PSR_I ) "\n"
     "orr %[arm_switch_reg], %[level]\n"
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #5\n"
+#endif
     "msr cpsr, %0\n"
     ARM_SWITCH_BACK
     : [arm_switch_reg] "=&r" (arm_switch_reg)
@@ -144,6 +150,9 @@ uint32_t _CPU_ISR_Get_level( void )
 
   __asm__ volatile (
     ARM_SWITCH_TO_ARM
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #4\n"
+#endif
     "mrs %[level], cpsr\n"
     "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( ARM_PSR_I ) "\n"
     ARM_SWITCH_BACK
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h
index af32fc3150..9e953358e7 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -48,10 +48,12 @@ extern "C" {
   #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
 #endif
 
+#ifndef RTEMS_PARAVIRT_XTRATUM
 #if defined(__ARM_ARCH_7A__) \
   || defined(__ARM_ARCH_7R__)
   #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
 #endif
+#endif
 
 #if defined(__ARM_ARCH_7A__)
   #define ARM_MULTILIB_CACHE_LINE_MAX_64
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 69838c5bf8..67d6b16c6d 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -333,8 +333,14 @@ static inline uint32_t arm_interrupt_disable( void )
 
   __asm__ volatile (
     ARM_SWITCH_TO_ARM
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #4\n"
+#endif
     "mrs %[level], cpsr\n"
     "orr %[arm_switch_reg], %[level], #0x80\n"
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #5\n"
+#endif
     "msr cpsr, %[arm_switch_reg]\n"
     ARM_SWITCH_BACK
     : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
@@ -362,6 +368,9 @@ static inline void arm_interrupt_enable( uint32_t level )
 
   __asm__ volatile (
     ARM_SWITCH_TO_ARM
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #5\n"
+#endif
     "msr cpsr, %[level]\n"
     ARM_SWITCH_BACK
     : ARM_SWITCH_OUTPUT
@@ -383,8 +392,17 @@ static inline void arm_interrupt_flash( uint32_t level )
 
   __asm__ volatile (
     ARM_SWITCH_TO_ARM
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #4\n"
+#endif
     "mrs %[arm_switch_reg], cpsr\n"
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #5\n"
+#endif
     "msr cpsr, %[level]\n"
+#ifdef RTEMS_PARAVIRT_XTRATUM
+    "udf #5\n"
+#endif
     "msr cpsr, %[arm_switch_reg]\n"
     ARM_SWITCH_BACK
     : [arm_switch_reg] "=&r" (arm_switch_reg)