diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-03-24 08:02:28 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-08-10 09:36:30 +0200 |
| commit | f49a41d7802341d40f97dcbae02ff1b875477a67 (patch) | |
| tree | 16a26d73306969aec4ec911e7c1739097d1902be /cpukit/score/cpu/arm/armv4-exception-default.S | |
| parent | c070af754dca62adab27753ba80ca01d1bc4ce3e (diff) | |
bsp/xm_tms570: New BSPxtratum-4.11
Diffstat (limited to 'cpukit/score/cpu/arm/armv4-exception-default.S')
| -rw-r--r-- | cpukit/score/cpu/arm/armv4-exception-default.S | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S index a10de301b0..763913b09e 100644 --- a/cpukit/score/cpu/arm/armv4-exception-default.S +++ b/cpukit/score/cpu/arm/armv4-exception-default.S @@ -103,21 +103,39 @@ _ARMV4_Exception_fiq_default: * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR * (which we'll load into the CPSR in save_more_context). */ +#ifdef RTEMS_PARAVIRT_XTRATUM + udf #4 +#endif mrs r2, spsr orr r2, #ARM_PSR_F +#ifdef RTEMS_PARAVIRT_XTRATUM + udf #5 +#endif msr spsr_c, r2 save_more_context: /* Save more context */ mov r2, lr +#ifdef RTEMS_PARAVIRT_XTRATUM + udf #4 +#endif mrs r3, spsr +#ifdef RTEMS_PARAVIRT_XTRATUM + udf #4 +#endif mrs r7, cpsr orr r5, r3, #ARM_PSR_I bic r5, #ARM_PSR_T +#ifdef RTEMS_PARAVIRT_XTRATUM + udf #5 +#endif msr cpsr, r5 mov r0, sp mov r1, lr +#ifdef RTEMS_PARAVIRT_XTRATUM + udf #5 +#endif msr cpsr, r7 mov r5, #0 add r6, sp, #ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET |