diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-02-16 09:11:22 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-20 11:28:05 +0200 |
| commit | a157731ed50d30b10b569518e44eb906822fd9f7 (patch) | |
| tree | 47e245437e93863641e68cd24e7b8bdec4630559 | |
| parent | 3e94cf4b5e73880ec1106500cb4c650e15d1cdfb (diff) | |
bsps/grlib: Fix FTMCTRL - MCFG1 bit fields
There was an off by one error in all bit fields. Add the R flag.
Update #4842.
| -rw-r--r-- | bsps/include/grlib/ftmctrl-regs.h | 62 |
1 files changed, 34 insertions, 28 deletions
diff --git a/bsps/include/grlib/ftmctrl-regs.h b/bsps/include/grlib/ftmctrl-regs.h index ea4b3325f1..440f92e042 100644 --- a/bsps/include/grlib/ftmctrl-regs.h +++ b/bsps/include/grlib/ftmctrl-regs.h @@ -82,49 +82,55 @@ extern "C" { * @{ */ -#define FTMCTRL_MCFG1_PBRDY 0x80000000U +#define FTMCTRL_MCFG1_PBRDY 0x40000000U -#define FTMCTRL_MCFG1_ABRDY 0x40000000U +#define FTMCTRL_MCFG1_ABRDY 0x20000000U -#define FTMCTRL_MCFG1_IOBUSW 0x20000000U - -#define FTMCTRL_MCFG1_IBRDY_SHIFT 27 -#define FTMCTRL_MCFG1_IBRDY_MASK 0x18000000U -#define FTMCTRL_MCFG1_IBRDY_GET( _reg ) \ +#define FTMCTRL_MCFG1_IOBUSW_SHIFT 27 +#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U +#define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \ ( ( ( _reg ) >> 27 ) & 0x3U ) -#define FTMCTRL_MCFG1_IBRDY( _val ) ( ( _val ) << 27 ) +#define FTMCTRL_MCFG1_IOBUSW( _val ) ( ( _val ) << 27 ) -#define FTMCTRL_MCFG1_BEXCN 0x4000000U +#define FTMCTRL_MCFG1_IBRDY 0x4000000U -#define FTMCTRL_MCFG1_IO_WAITSTATES 0x1000000U +#define FTMCTRL_MCFG1_BEXCN 0x2000000U -#define FTMCTRL_MCFG1_IOEN_SHIFT 20 -#define FTMCTRL_MCFG1_IOEN_MASK 0xf00000U -#define FTMCTRL_MCFG1_IOEN_GET( _reg ) \ +#define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20 +#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U +#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \ ( ( ( _reg ) >> 20 ) & 0xfU ) -#define FTMCTRL_MCFG1_IOEN( _val ) ( ( _val ) << 20 ) +#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) ( ( _val ) << 20 ) + +#define FTMCTRL_MCFG1_IOEN 0x80000U -#define FTMCTRL_MCFG1_ROMBANKSZ 0x80000U +#define FTMCTRL_MCFG1_R 0x40000U -#define FTMCTRL_MCFG1_PWEN_SHIFT 14 -#define FTMCTRL_MCFG1_PWEN_MASK 0x3c000U -#define FTMCTRL_MCFG1_PWEN_GET( _reg ) \ +#define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14 +#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U +#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \ ( ( ( _reg ) >> 14 ) & 0xfU ) -#define FTMCTRL_MCFG1_PWEN( _val ) ( ( _val ) << 14 ) +#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) ( ( _val ) << 14 ) + +#define FTMCTRL_MCFG1_PWEN 0x800U -#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 12 -#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x3000U +#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8 +#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U #define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \ - ( ( ( _reg ) >> 12 ) & 0x3U ) -#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) ( ( _val ) << 12 ) + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) ( ( _val ) << 8 ) -#define FTMCTRL_MCFG1_PROM_WRITE_WS 0x800U +#define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4 +#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U +#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfU ) +#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) ( ( _val ) << 4 ) -#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 8 -#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0x300U +#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 0 +#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU #define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \ - ( ( ( _reg ) >> 8 ) & 0x3U ) -#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) ( ( _val ) << 8 ) + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) ( ( _val ) << 0 ) /** @} */ |