tc-intr

6 files changed, 437 insertions, 0 deletions

diff --git a/spec/build/testsuites/validation/validation-0.yml b/spec/build/testsuites/validation/validation-0.yml
index 8d6989fd1e..867cbef2a5 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -28,6 +28,7 @@ source:
 - testsuites/validation/tc-flsl.c
 - testsuites/validation/tc-futex-wait.c
 - testsuites/validation/tc-futex-wake.c
+- testsuites/validation/tc-intr.c
 - testsuites/validation/tc-intr-clear.c
 - testsuites/validation/tc-intr-entry-install.c
 - testsuites/validation/tc-intr-entry-remove.c
diff --git a/spec/build/testsuites/validation/validation-non-smp.yml b/spec/build/testsuites/validation/validation-non-smp.yml
index 193baf7cc0..784e041b5d 100644
--- a/spec/build/testsuites/validation/validation-non-smp.yml
+++ b/spec/build/testsuites/validation/validation-non-smp.yml
@@ -12,6 +12,7 @@ includes: []
 ldflags: []
 links: []
 source:
+- testsuites/validation/tc-intr-non-smp.c
 - testsuites/validation/tc-scheduler-non-smp.c
 - testsuites/validation/ts-validation-non-smp.c
 stlib: []
diff --git a/spec/build/testsuites/validation/validation-smp-only-0.yml b/spec/build/testsuites/validation/validation-smp-only-0.yml
index 750b3b39ac..be5d161a57 100644
--- a/spec/build/testsuites/validation/validation-smp-only-0.yml
+++ b/spec/build/testsuites/validation/validation-smp-only-0.yml
@@ -13,6 +13,7 @@ ldflags:
 links: []
 source:
 - testsuites/validation/tc-bsp-interrupt-spurious.c
+- testsuites/validation/tc-intr-smp-only.c
 - testsuites/validation/tc-scheduler-smp-only.c
 - testsuites/validation/tc-sched-smp.c
 - testsuites/validation/tc-sched-smp-edf-set-affinity.c
diff --git a/testsuites/validation/tc-intr-non-smp.c b/testsuites/validation/tc-intr-non-smp.c
new file mode 100644
index 0000000000..506f867c9d
--- /dev/null
+++ b/testsuites/validation/tc-intr-non-smp.c
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrValIntrNonSmp
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated.  If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual.  The manual is provided as a part of
+ * a release.  For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems.h>
+#include <rtems/irq-extension.h>
+
+#include "tx-support.h"
+
+#include <rtems/test.h>
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrValIntrNonSmp \
+ *   spec:/rtems/intr/val/intr-non-smp
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidationNonSmp
+ *
+ * @brief Tests some @ref RTEMSAPIClassicIntr directives.
+ *
+ * This test case performs the following actions:
+ *
+ * - Validate rtems_interrupt_local_disable() and
+ *   rtems_interrupt_local_enable().
+ *
+ *   - Check that maskable interrupts are enabled before the call to
+ *     rtems_interrupt_local_disable() and disabled afterwards.
+ *
+ *   - Check that maskable interrupts are disabled before the call to
+ *     rtems_interrupt_local_disable() and disabled afterwards.
+ *
+ *   - Check that maskable interrupt status is restored by the call to
+ *     rtems_interrupt_local_enable() according to the ``_isr_cookie``
+ *     parameter.  In this case maskable interrupts are still disabled
+ *     afterwards.
+ *
+ *   - Check that maskable interrupt status is restored by the call to
+ *     rtems_interrupt_local_enable() according to the ``_isr_cookie``
+ *     parameter.  In this case maskable interrupts are enabled afterwards.
+ *
+ * @{
+ */
+
+/**
+ * @brief Validate rtems_interrupt_local_disable() and
+ *   rtems_interrupt_local_enable().
+ */
+static void RtemsIntrValIntrNonSmp_Action_0( void )
+{
+  rtems_interrupt_level level;
+  rtems_interrupt_level level_2;
+
+  /*
+   * Check that maskable interrupts are enabled before the call to
+   * rtems_interrupt_local_disable() and disabled afterwards.
+   */
+  T_true( AreInterruptsEnabled() );
+  rtems_interrupt_local_disable( level );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupts are disabled before the call to
+   * rtems_interrupt_local_disable() and disabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_disable( level_2 );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupt status is restored by the call to
+   * rtems_interrupt_local_enable() according to the ``_isr_cookie`` parameter.
+   * In this case maskable interrupts are still disabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_enable( level_2 );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupt status is restored by the call to
+   * rtems_interrupt_local_enable() according to the ``_isr_cookie`` parameter.
+   * In this case maskable interrupts are enabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_enable( level );
+  T_true( AreInterruptsEnabled() );
+}
+
+/**
+ * @fn void T_case_body_RtemsIntrValIntrNonSmp( void )
+ */
+T_TEST_CASE( RtemsIntrValIntrNonSmp )
+{
+  RtemsIntrValIntrNonSmp_Action_0();
+}
+
+/** @} */
diff --git a/testsuites/validation/tc-intr-smp-only.c b/testsuites/validation/tc-intr-smp-only.c
new file mode 100644
index 0000000000..4448af7e5d
--- /dev/null
+++ b/testsuites/validation/tc-intr-smp-only.c
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrValIntrSmpOnly
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated.  If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual.  The manual is provided as a part of
+ * a release.  For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems.h>
+#include <rtems/irq-extension.h>
+
+#include "tx-support.h"
+
+#include <rtems/test.h>
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrValIntrSmpOnly \
+ *   spec:/rtems/intr/val/intr-smp-only
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidationSmpOnly0
+ *
+ * @brief Tests some @ref RTEMSAPIClassicIntr directives.
+ *
+ * This test case performs the following actions:
+ *
+ * - Validate rtems_interrupt_local_disable() and
+ *   rtems_interrupt_local_enable().
+ *
+ *   - Check that maskable interrupts are enabled before the call to
+ *     rtems_interrupt_local_disable() and disabled afterwards.
+ *
+ *   - Check that maskable interrupts are disabled before the call to
+ *     rtems_interrupt_local_disable() and disabled afterwards.
+ *
+ *   - Check that maskable interrupt status is restored by the call to
+ *     rtems_interrupt_local_enable() according to the ``_isr_cookie``
+ *     parameter.  In this case maskable interrupts are still disabled
+ *     afterwards.
+ *
+ *   - Check that maskable interrupt status is restored by the call to
+ *     rtems_interrupt_local_enable() according to the ``_isr_cookie``
+ *     parameter.  In this case maskable interrupts are enabled afterwards.
+ *
+ * @{
+ */
+
+/**
+ * @brief Validate rtems_interrupt_local_disable() and
+ *   rtems_interrupt_local_enable().
+ */
+static void RtemsIntrValIntrSmpOnly_Action_0( void )
+{
+  rtems_interrupt_level level;
+  rtems_interrupt_level level_2;
+
+  /*
+   * Check that maskable interrupts are enabled before the call to
+   * rtems_interrupt_local_disable() and disabled afterwards.
+   */
+  T_true( AreInterruptsEnabled() );
+  rtems_interrupt_local_disable( level );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupts are disabled before the call to
+   * rtems_interrupt_local_disable() and disabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_disable( level_2 );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupt status is restored by the call to
+   * rtems_interrupt_local_enable() according to the ``_isr_cookie`` parameter.
+   * In this case maskable interrupts are still disabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_enable( level_2 );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupt status is restored by the call to
+   * rtems_interrupt_local_enable() according to the ``_isr_cookie`` parameter.
+   * In this case maskable interrupts are enabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_enable( level );
+  T_true( AreInterruptsEnabled() );
+}
+
+/**
+ * @fn void T_case_body_RtemsIntrValIntrSmpOnly( void )
+ */
+T_TEST_CASE( RtemsIntrValIntrSmpOnly )
+{
+  RtemsIntrValIntrSmpOnly_Action_0();
+}
+
+/** @} */
diff --git a/testsuites/validation/tc-intr.c b/testsuites/validation/tc-intr.c
new file mode 100644
index 0000000000..7361140d6a
--- /dev/null
+++ b/testsuites/validation/tc-intr.c
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseRtemsIntrValIntr
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated.  If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual.  The manual is provided as a part of
+ * a release.  For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems.h>
+#include <rtems/irq-extension.h>
+
+#include "tx-support.h"
+
+#include <rtems/test.h>
+
+/**
+ * @defgroup RTEMSTestCaseRtemsIntrValIntr spec:/rtems/intr/val/intr
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @brief Tests some @ref RTEMSAPIClassicIntr directives.
+ *
+ * This test case performs the following actions:
+ *
+ * - Validate rtems_interrupt_local_disable() and
+ *   rtems_interrupt_local_enable().
+ *
+ *   - Check that maskable interrupts are enabled before the call to
+ *     rtems_interrupt_local_disable() and disabled afterwards.
+ *
+ *   - Check that maskable interrupts are disabled before the call to
+ *     rtems_interrupt_local_disable() and disabled afterwards.
+ *
+ *   - Check that maskable interrupt status is restored by the call to
+ *     rtems_interrupt_local_enable() according to the ``_isr_cookie``
+ *     parameter.  In this case maskable interrupts are still disabled
+ *     afterwards.
+ *
+ *   - Check that maskable interrupt status is restored by the call to
+ *     rtems_interrupt_local_enable() according to the ``_isr_cookie``
+ *     parameter.  In this case maskable interrupts are enabled afterwards.
+ *
+ * @{
+ */
+
+/**
+ * @brief Validate rtems_interrupt_local_disable() and
+ *   rtems_interrupt_local_enable().
+ */
+static void RtemsIntrValIntr_Action_0( void )
+{
+  rtems_interrupt_level level;
+  rtems_interrupt_level level_2;
+
+  /*
+   * Check that maskable interrupts are enabled before the call to
+   * rtems_interrupt_local_disable() and disabled afterwards.
+   */
+  T_true( AreInterruptsEnabled() );
+  rtems_interrupt_local_disable( level );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupts are disabled before the call to
+   * rtems_interrupt_local_disable() and disabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_disable( level_2 );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupt status is restored by the call to
+   * rtems_interrupt_local_enable() according to the ``_isr_cookie`` parameter.
+   * In this case maskable interrupts are still disabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_enable( level_2 );
+  T_false( AreInterruptsEnabled() );
+
+  /*
+   * Check that maskable interrupt status is restored by the call to
+   * rtems_interrupt_local_enable() according to the ``_isr_cookie`` parameter.
+   * In this case maskable interrupts are enabled afterwards.
+   */
+  T_false( AreInterruptsEnabled() );
+  rtems_interrupt_local_enable( level );
+  T_true( AreInterruptsEnabled() );
+}
+
+/**
+ * @fn void T_case_body_RtemsIntrValIntr( void )
+ */
+T_TEST_CASE( RtemsIntrValIntr )
+{
+  RtemsIntrValIntr_Action_0();
+}
+
+/** @} */