diff options
author | Jan Sommer <jan.sommer@dlr.de> | 2020-08-20 09:18:06 +0200 |
---|---|---|
committer | Chris Johns <chrisj@rtems.org> | 2020-08-22 17:29:25 +1000 |
commit | b87efa7599f33f56608da20567d77dbb06db98e1 (patch) | |
tree | bf9ba196fef5d000af8db7ec7b99f800757e3ab8 | |
parent | 1a506170ccc5031f6ee34c6a60a7dbf6e14eb052 (diff) |
bsp/xilinx-zynq: Flush TX-Buffer before initializing uart
Closes #4055
Closes #4056
-rw-r--r-- | bsps/arm/shared/serial/zynq-uart-polled.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/bsps/arm/shared/serial/zynq-uart-polled.c b/bsps/arm/shared/serial/zynq-uart-polled.c index 4e0ca46aca..e6f478ee07 100644 --- a/bsps/arm/shared/serial/zynq-uart-polled.c +++ b/bsps/arm/shared/serial/zynq-uart-polled.c @@ -122,6 +122,8 @@ void zynq_uart_initialize(rtems_termios_device_context *base) uint32_t brgr = 0x3e; uint32_t bauddiv = 0x6; + zynq_uart_reset_tx_flush(ctx); + zynq_cal_baud_rate(ZYNQ_UART_DEFAULT_BAUD, &brgr, &bauddiv, regs->mode); regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN); |