summaryrefslogtreecommitdiffstats
path: root/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml
blob: 7d69273eb2a91a1969f9a411af0e06d5358c629a (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-integer: null
- define: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 50000000
default-by-variant:
- value: 50000000
  variants:
  - arm/xilinx_zynq_zc702.*
- value: 50000000
  variants:
  - arm/xilinx_zynq_zedboard.*
description: |
  Zynq UART clock frequency in Hz
enabled-by: true
format: '{}'
links: []
name: ZYNQ_CLOCK_UART
type: build