summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu/mips/ChangeLog
blob: 5b3439971a8c1c08c88216858bc89b6bd9383510 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
2001-10-11	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* .cvsignore: Add autom4te.cache for autoconf > 2.52.
	* configure.in: Remove.
	* configure.ac: New file, generated from configure.in by autoupdate.

2001-09-23	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
	* Makefile.am: Use 'PREINSTALL_FILES ='.

2001-07-03	Joel Sherrill <joel@OARcorp.com>

	* cpu.c: Fixed typo.

2000-05-24	Joel Sherrill <joel@OARcorp.com>

	* rtems/score/mips.h: Added constants for MIPS exception numbers.
	All exceptions should be given low numbers and thus can be installed
	and processed in a uniform manner.  Variances between various MIPS
	ISA levels were not accounted for.

2001-05-24	Greg Menke <gregory.menke@gsfc.nasa.gov>

	* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
	* cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.

2001-05-22	Greg Menke <gregory.menke@gsfc.nasa.gov>

	* rtems/score/cpu.h: Add the interrupt stack structure and enhance
	the context initialization to account for floating point tasks.  
	* rtems/score/mips.h: Added the routines mips_set_cause(),
	mips_get_fcr31(), and mips_set_fcr31().
	* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.

2001-05-07	Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.S: Merged patches from Gregory Menke
	<Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
	stack usage and include nops in the delay slots.

2001-04-20	Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.S: Added code to save and restore SR and EPC to
	properly support nested interrupts.  Note that the ISR
	(not RTEMS) enables interrupts allowing the nesting to occur.

2001-03-14	Joel Sherrill <joel@OARcorp.com>

	* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
	Removed unused variable _CPU_Thread_dispatch_pointer
	and cleaned numerous comments.
	
2001-03-13	Joel Sherrill <joel@OARcorp.com>

	* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
	Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
	Also reimplemented some assembly routines in C further reducing
	the amount of assembly and increasing maintainability.

2001-02-04	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* Makefile.am, rtems/score/Makefile.am: 
	Apply include_*HEADERS instead of H_FILES.

2001-01-12	Joel Sherrill <joel@OARcorp.com>

	* rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
	register constraints from "general" to "register".

2001-01-09	Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
	to make it easier to conditionalize the code for various ISA levels.

2001-01-08	Joel Sherrill <joel@OARcorp.com>

	* idtcpu.h: Commented out definition of "wait".  It was stupid to
	use such a common word as a macro.
	* rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
	* rtems/score/mips.h: Added include of <idtcpu.h>.
	* rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.

2001-01-03	Joel Sherrill <joel@OARcorp.com>

	* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
	* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.

2000-12-19	Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
	Previous code resulting in the interrupted immediately returning
	to the caller of the routine it was inside.

2000-12-19	Joel Sherrill <joel@OARcorp.com>

	* cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
	because it has not been allocated yet.

2000-12-13	Joel Sherrill <joel@OARcorp.com>

	* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
	* cpu_asm.S: Removed assembly language to vector ISR handler
	on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
	* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
	longer a constant -- get the real value from libcpu.

2000-12-13	Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.h: Removed.
	* Makefile.am: Remove cpu_asm.h.
	* rtems/score/mips64orion.h: Renamed mips.h.
	* rtems/score/mips.h: New file, formerly mips64orion.h.
	Header rewritten.
	(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
	mips_disable_in_interrupt_mask): New macros.
	* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
	* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
	few defines that were in <cpu_asm.h>.
	* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
	MIPS ISA 3 is still in assembly for now.
	(_CPU_Thread_Idle_body): Rewrote in C.
	* cpu_asm.S: Rewrote file header. 
	(FRAME,ENDFRAME) now in asm.h.
	(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
	(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
	(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
	leaves other bits in SR alone on task switch.
	(mips_enable_interrupts,mips_disable_interrupts,
	mips_enable_global_interrupts,mips_disable_global_interrupts,
	disable_int, enable_int): Removed.
	(mips_get_sr): Rewritten as C macro.
	(_CPU_Thread_Idle_body): Rewritten in C.
	(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
	placed in libcpu.
	(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
	to libcpu/mips/shared/interrupts.
	(general): Cleaned up comment blocks and #if 0 areas.
	* idtcpu.h: Made ifdef report an error.
	* iregdef.h: Removed warning.
	* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
	number defined by libcpu.
	(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
	to access SR.
	(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
	(_CPU_Context_Initialize): Honor ISR level in task initialization.
	(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.

2000-12-06	Joel Sherrill <joel@OARcorp.com>

	* rtems/score/cpu.h: When mips ISA level is 1, registers in the
	context should be 32 not 64 bits.

2000-11-30	Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
	correct name of _CPU_Context_switch_restore.  Added dummy
	version of exc_utlb_code() so applications would link.

2000-11-09	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.

2000-11-02	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.

2000-10-25	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
        Switch to GNU canonicalization.

2000-10-24	Alan Cudmore <alanc@linuxstart.com> and
	Joel Sherrill <joel@OARcorp.com>

	* This is a major reworking of the mips64orion port to use 
	gcc predefines as much as possible and a big push to multilib
	the mips port.  The mips64orion port was copied/renamed to mips
	to be more like other GNU tools.  Alan did most of the technical
	work of determining how to map old macro names used by the mips64orion
	port to standard compiler macro definitions.  Joel did the merge
	with CVS magic to keep individual file history and did the BSP
	modifications. Details follow:
	* Makefile.am: idtmon.h in mips64orion port not present.
	* asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
	* cpu.c: Comments added.
	* cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
	First attempt at exception/interrupt processing for ISA level 1 
	and minus any use of IDT/MON added.
	* idtcpu.h: Conditionals changed to use gcc predefines.
	* iregdef.h: Ditto.
	* cpu_asm.h: No real change.  Merger required commit.
	* rtems/Makefile.am: Ditto.
	* rtems/score/Makefile.am: Ditto.
	* rtems/score/cpu.h: Change MIPS64ORION to MIPS.
	* rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
	from using RTEMS_CPU_MODEL to gcc predefines to figre things out.

2000-09-04	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

	* Makefile.am: Include compile.am.

2000-08-10	Joel Sherrill <joel@OARcorp.com>

	* ChangeLog: New file.