1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
|
/*
**************************************************************************
*
* Component =
*
* Synopsis = rdbg/m68k/rdbg_f.c
*
* $Id$
*
**************************************************************************
*/
#include <assert.h>
#include <errno.h>
#include <rdbg/reg.h>
#include <rdbg/remdeb.h>
#include <rdbg/rdbg.h>
#include <rtems/score/cpu.h>
#include <rtems/score/thread.h>
m68k_isr_entry set_vector(
rtems_isr_entry handler,
rtems_vector_number vector,
int type
);
void CtxToRegs (const CPU_Exception_frame * ctx, xdr_regs * regs)
{
regs->r_dreg[0] = ctx->d0;
regs->r_dreg[1] = ctx->d1;
regs->r_dreg[2] = ctx->d2;
regs->r_dreg[3] = ctx->d3;
regs->r_dreg[4] = ctx->d4;
regs->r_dreg[5] = ctx->d5;
regs->r_dreg[6] = ctx->d6;
regs->r_dreg[7] = ctx->d7;
regs->r_areg[0] = ctx->a0;
regs->r_areg[1] = ctx->a1;
regs->r_areg[2] = ctx->a2;
regs->r_areg[3] = ctx->a3;
regs->r_areg[4] = ctx->a4;
regs->r_areg[5] = ctx->a5;
regs->r_areg[6] = ctx->a6;
regs->r_areg[7] = ctx->a7;
regs->r_sr = ctx->sr;
regs->r_pc = ctx->pc;
regs->r_vec = ctx->vecnum;
}
void
RegsToCtx (const xdr_regs * regs, CPU_Exception_frame * ctx)
{
ctx->d0 = regs->r_dreg[0];
ctx->d1 = regs->r_dreg[1];
ctx->d2 = regs->r_dreg[2];
ctx->d3 = regs->r_dreg[3];
ctx->d4 = regs->r_dreg[4];
ctx->d5 = regs->r_dreg[5];
ctx->d6 = regs->r_dreg[6];
ctx->d7 = regs->r_dreg[7];
ctx->a0 = regs->r_areg[0];
ctx->a1 = regs->r_areg[1];
ctx->a2 = regs->r_areg[2];
ctx->a3 = regs->r_areg[3];
ctx->a4 = regs->r_areg[4];
ctx->a5 = regs->r_areg[5];
ctx->a6 = regs->r_areg[6];
ctx->a7 = regs->r_areg[7];
ctx->sr = regs->r_sr;
ctx->pc = regs->r_pc;
ctx->vecnum = regs->r_vec;
}
void
get_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx)
{
/*
* ISR stores d0-d1/a0-a1, calls _Thread_Dispatch
* _Thread_Dispatch calls _Context_Switch == _CPU_Context_switch
* _CPU_Context_switch stores/restores sr,d2-d7,a2-a7
* so if my reasoning is correct, *sp points to a location in
* _Thread_Dispatch
*/
ctx->vecnum = 0xdeadbeef;
ctx->sr = thread->Registers.sr;
ctx->pc = *(unsigned32 *) thread->Registers.a7_msp;
ctx->d0 = 0xdeadbeef;
ctx->d1 = 0xdeadbeef;
ctx->a0 = 0xdeadbeef;
ctx->a1 = 0xdeadbeef;
ctx->a2 = (unsigned32) thread->Registers.a2;
ctx->a3 = (unsigned32) thread->Registers.a3;
ctx->a4 = (unsigned32) thread->Registers.a4;
ctx->a5 = (unsigned32) thread->Registers.a5;
ctx->a6 = (unsigned32) thread->Registers.a6;
ctx->a7 = (unsigned32) thread->Registers.a7_msp;
ctx->d2 = thread->Registers.d2;
ctx->d3 = thread->Registers.d3;
ctx->d4 = thread->Registers.d4;
ctx->d5 = thread->Registers.d5;
ctx->d6 = thread->Registers.d6;
ctx->d7 = thread->Registers.d7;
}
void
set_ctx_thread (Thread_Control * thread, CPU_Exception_frame * ctx)
{
thread->Registers.sr = ctx->sr;
thread->Registers.d2 = ctx->d2;
thread->Registers.d3 = ctx->d3;
thread->Registers.d4 = ctx->d4;
thread->Registers.d5 = ctx->d5;
thread->Registers.d6 = ctx->d6;
thread->Registers.d7 = ctx->d7;
thread->Registers.a2 = (void *) ctx->a2;
thread->Registers.a3 = (void *) ctx->a3;
thread->Registers.a4 = (void *) ctx->a4;
thread->Registers.a5 = (void *) ctx->a5;
thread->Registers.a6 = (void *) ctx->a6;
thread->Registers.a7_msp = (void *) ctx->a7;
}
int
Single_Step (CPU_Exception_frame * ctx)
{
if ((ctx->sr & (1 << 15)) != 0 || ExitForSingleStep != 0) {
/*
* Check coherency
*/
assert ((ctx->sr & (1 << 15)) != 0);
assert (ExitForSingleStep != 0);
return 0;
}
ctx->sr |= 1 << 15;
++ExitForSingleStep;
return 0;
}
int
CheckForSingleStep (CPU_Exception_frame * ctx)
{
if (ExitForSingleStep) {
ctx->sr &= ~(1 << 15);
ExitForSingleStep = 0;
return 1;
}
return 0;
}
void
CancelSingleStep (CPU_Exception_frame * ctx)
{
/*
* Cancel scheduled SS
*/
ctx->sr &= ~(1 << 15);
ExitForSingleStep--;
}
extern rtems_isr excHandler ();
void
connect_rdbg_exception (void)
{
set_vector (excHandler, 9, 0);
set_vector (excHandler, 47, 0);
set_vector (excHandler, 36, 0);
}
void
disconnect_rdbg_exception (void)
{
}
|
