blob: ff0464c8f27d2a48a95a123d7f8642072c2e7a2c (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
/* ckinit.c
*
* This file provides a template for the clock device driver initialization.
*
* Modified for sun4v - niagara
*/
/*
* Copyright (c) 2010 Gedare Bloom.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <stdlib.h>
#include <rtems.h>
#include <bsp.h>
#include <bspopts.h>
#include <boot/ofw.h>
/* This is default frequency for simics simulator of niagara. Use the
* get_Frequency function to determine the CPU clock frequency at runtime.
*/
#define CPU_FREQ (5000000)
uint64_t sparc64_cycles_per_tick;
/* TICK_CMPR and STICK_CMPR trigger soft interrupt 14 */
#define CLOCK_VECTOR SPARC_SYNCHRONOUS_TRAP(0x4E)
static unsigned int get_Frequency(void)
{
phandle root = ofw_find_device("/");
unsigned int freq;
if (ofw_get_property(root, "clock-frequency", &freq, sizeof(freq)) <= 0) {
printk("Unable to determine frequency, default: 0x%x\n",CPU_FREQ);
return CPU_FREQ;
}
return freq;
}
static void Clock_driver_support_at_tick(void)
{
uint64_t tick_reg;
int bit_mask;
uint64_t pil_reg;
bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
sparc64_clear_interrupt_bits(bit_mask);
sparc64_get_pil(pil_reg);
if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */
pil_reg--;
sparc64_set_pil(pil_reg); /* enable the next timer interrupt */
}
/* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which
* does not currently have tick_cmpr implemented */
/* TODO: this could be more efficiently implemented as a single assembly
* inline */
#if defined (SUN4U)
sparc64_read_tick(tick_reg);
#elif defined (SUN4V)
sparc64_read_stick(tick_reg);
#endif
tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
tick_reg += sparc64_cycles_per_tick;
#if defined (SUN4U)
sparc64_write_tick_cmpr(tick_reg);
#elif defined (SUN4V)
sparc64_write_stick_cmpr(tick_reg);
#endif
}
#define Clock_driver_support_install_isr(_new, _old) \
do { \
_old = set_vector( _new, CLOCK_VECTOR, 1 ); \
} while ( 0 )
static void Clock_driver_support_initialize_hardware(void)
{
uint64_t tick_reg;
int bit_mask;
bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
sparc64_clear_interrupt_bits(bit_mask);
sparc64_cycles_per_tick =
rtems_configuration_get_microseconds_per_tick()*(get_Frequency()/1000000);
#if defined (SUN4U)
sparc64_read_tick(tick_reg);
#elif defined (SUN4V)
sparc64_read_stick(tick_reg);
#endif
tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
tick_reg += sparc64_cycles_per_tick;
#if defined (SUN4U)
sparc64_write_tick_cmpr(tick_reg);
#elif defined (SUN4V)
sparc64_write_stick_cmpr(tick_reg);
#endif
}
#define Clock_driver_support_shutdown_hardware( ) \
do { \
\
} while ( 0 )
#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
#include "../../../shared/clockdrv_shell.h"
|
