1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
/**
* @file
*
* @ingroup RTEMSBSPsPowerPCMPC55XX
*
* @brief EBI chip-select configuration.
*/
/*
* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/mpc55xx-config.h>
#ifdef MPC55XX_HAS_EBI
const struct EBI_CS_tag mpc55xx_start_config_ebi_cs [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
/* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
{
{
.B.BA = 0x20000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 1,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 1,
.B.BSCY = 0
}
},
/* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
{
{
.B.BA = 0x22000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 3,
.B.BSCY = 0
}
},
/* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
{
{
.B.BA = 0x22800000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 1,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 1,
.B.BSCY = 0
}
},
{ /* CS3: MOST Companion. */
{
.B.BA = 0x23000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 1,
.B.BSCY = 0
}
}
#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
/* CS0: External flash. */
{
{ .R = 0x20000003 }, /* Base 0x2000000, Burst Inhibit, Valid */
{ .R = 0xff000050 }
},
/* CS1: External synchronous burst mode SRAM. */
{
{ .R = 0x21000051 }, /* Base 0x2100000, 4-word Burst Enabled, Valid */
{ .R = 0xff000000 } /* No wait states. */
},
/* CS2: External LAN91C111 */
{
{ .R = 0x22000003 }, /* Base 0x22000000, Burst inhibit, valid */
{ .R = 0xff000010 }
},
/* CS3: External FPGA */
{
{ .R = 0x23000003 }, /* Base 0x23000000, Burst inhibit, valid. */
{ .R = 0xff000020 }
}
#elif defined(MPC55XX_BOARD_MPC5566EVB)
/* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
{
{
.B.BA = 0,
.B.PS = 1,
.B.BL = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1, /* TODO: Enable burst */
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 0,
.B.BSCY = 0
}
},
{ { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */
{ { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */
{ /* CS3: ethernet? */
{
.B.BA = 0x7fff,
.B.PS = 1,
.B.BL = 0,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 1,
.B.BSCY = 0
}
}
#endif
};
const size_t mpc55xx_start_config_ebi_cs_count [] = {
RTEMS_ARRAY_SIZE(mpc55xx_start_config_ebi_cs)
};
#endif /* MPC55XX_HAS_EBI */
|
