1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
|
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* FIXME: Compilation should be automated.
*
* Compile this file with the following commands:
* export BSP_DIR="${RTEMS_SRC_DIR}/bsps/arm/imxrt/"
* arm-rtems6-cpp -P -x assembler-with-cpp -I "${BSP_DIR}/include/" -include "${BSP_DIR}/dts/imxrt1050-evkb.dts" /dev/null | \
* dtc -@ -O dtb -o "${BSP_DIR}/dts/imxrt1050-evkb.dtb" -b 0 -p 1024
* rtems-bin2c -C -N imxrt_dtb "${BSP_DIR}/dts/imxrt1050-evkb.dtb" "${BSP_DIR}/dts/imxrt1050-evkb.c"
*/
#include <imxrt/imxrt1050-pinfunc.h>
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen: chosen {};
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
};
nvic: interrupt-controller@e000e100 {
compatible = "arm,armv7m-nvic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xe000e100 0xc00>;
};
systick: timer@e000e010 {
compatible = "arm,armv7m-systick";
reg = <0xe000e010 0x10>;
status = "disabled";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&nvic>;
ranges;
aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x00100000>;
ranges;
gpio5: gpio@400c0000 {
compatible = "fsl,imxrt-gpio",
"fsl,imx6ul-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <88>, <89>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
aips-bus@40100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40100000 0x00100000>;
ranges;
gpio4: gpio@401c4000 {
compatible = "fsl,imxrt-gpio",
"fsl,imx6ul-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <86>, <87>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@401c0000 {
compatible = "fsl,imxrt-gpio",
"fsl,imx6ul-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <84>, <85>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@401bc000 {
compatible = "fsl,imxrt-gpio",
"fsl,imx6ul-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <82>, <83>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@401b8000 {
compatible = "fsl,imxrt-gpio",
"fsl,imx6ul-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <80>, <81>, <72>, <73>, <74>,
<75>, <76>, <77>, <78>, <79>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
lpuart1: uart@40184000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <20>;
status = "disabled";
rtems,path = "/dev/ttyS1";
};
lpuart2: uart@40188000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x40188000 0x4000>;
interrupts = <21>;
status = "disabled";
rtems,path = "/dev/ttyS2";
};
lpuart3: uart@4018c000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x4018c000 0x4000>;
interrupts = <22>;
status = "disabled";
rtems,path = "/dev/ttyS3";
};
lpuart4: uart@40190000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x40190000 0x4000>;
interrupts = <23>;
status = "disabled";
rtems,path = "/dev/ttyS4";
};
lpuart5: uart@40194000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x40194000 0x4000>;
interrupts = <24>;
status = "disabled";
rtems,path = "/dev/ttyS5";
};
lpuart6: uart@40198000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x40198000 0x4000>;
interrupts = <25>;
status = "disabled";
rtems,path = "/dev/ttyS6";
};
lpuart7: uart@4019c000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x4019c000 0x4000>;
interrupts = <26>;
status = "disabled";
rtems,path = "/dev/ttyS7";
};
lpuart8: uart@401a0000 {
compatible = "nxp,imxrt-lpuart";
reg = <0x401a0000 0x4000>;
interrupts = <27>;
status = "disabled";
rtems,path = "/dev/ttyS8";
};
iomuxc: pinctrl@401f8000 {
compatible = "nxp,imxrt1050-iomuxc";
reg = <0x401f8000 0x4000>;
};
};
aips-bus@40200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40200000 0x00100000>;
ranges;
fec1: ethernet@402d8000 {
compatible = "fsl,imxrt-fec", "fsl,imx6ul-fec";
reg = <0x402d8000 0x4000>;
interrupt-names = "int0", "pps";
interrupts = <114>, <115>;
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
phy-mode = "rmii";
status = "disabled";
};
};
aips-bus@40300000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40300000 0x00100000>;
ranges;
lpspi1: lpspi@40394000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpspi";
reg = <0x40394000 0x4000>;
interrupts = <32>;
status = "disabled";
rtems,path = "/dev/spi1";
};
lpspi2: lpspi@40398000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpspi";
reg = <0x40398000 0x4000>;
interrupts = <33>;
status = "disabled";
rtems,path = "/dev/spi2";
};
lpspi3: lpspi@4039c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpspi";
reg = <0x4039c000 0x4000>;
interrupts = <34>;
status = "disabled";
rtems,path = "/dev/spi3";
};
lpspi4: lpspi@403a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpspi";
reg = <0x403a0000 0x4000>;
interrupts = <35>;
status = "disabled";
rtems,path = "/dev/spi4";
};
lpi2c1: lpi2c@403f0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpi2c";
reg = <0x403f0000 0x4000>;
interrupts = <28>;
status = "disabled";
rtems,path = "/dev/i2c1";
};
lpi2c2: lpi2c@403f4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpi2c";
reg = <0x403f4000 0x4000>;
interrupts = <29>;
status = "disabled";
rtems,path = "/dev/i2c2";
};
lpi2c3: lpi2c@403f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpi2c";
reg = <0x403f8000 0x4000>;
interrupts = <30>;
status = "disabled";
rtems,path = "/dev/i2c3";
};
lpi2c4: lpi2c@403fc000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imxrt-lpi2c";
reg = <0x403fc000 0x4000>;
interrupts = <31>;
status = "disabled";
rtems,path = "/dev/i2c4";
};
};
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&chosen {
stdout-path = &lpuart1;
};
&lpuart3 {
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&lpspi1 {
pinctrl-0 = <&pinctrl_lpspi1>;
status = "okay";
};
&lpi2c1 {
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
};
&lpi2c1 {
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
};
&fec1 {
pinctrl-0 = <&pinctrl_fec1>;
phy-reset-gpios = <&gpio1 9 1>;
rtems,phy-interrupt-gpios = <&gpio1 10 1>;
status = "okay";
};
&iomuxc {
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_B0_12__LPUART1_TX 0x8
IMXRT_PAD_GPIO_AD_B0_13__LPUART1_RX 0x13000
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_B1_06__LPUART3_TX 0x8
IMXRT_PAD_GPIO_AD_B1_07__LPUART3_RX 0x13000
>;
};
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <
IMXRT_PAD_GPIO_SD_B0_01__LPSPI1_PCS0 0x8
IMXRT_PAD_GPIO_SD_B0_02__LPSPI1_SDO 0x8
IMXRT_PAD_GPIO_SD_B0_03__LPSPI1_SDI 0x1b000
IMXRT_PAD_GPIO_SD_B0_00__LPSPI1_SCK 0x8
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_B1_00__LPI2C1_SCL 0x4000f830
IMXRT_PAD_GPIO_AD_B1_01__LPI2C1_SDA 0x4000f830
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMXRT_PAD_GPIO_EMC_41__ENET_enet_mdio 0xb829
IMXRT_PAD_GPIO_EMC_40__ENET_enet_mdc 0xb0e9
IMXRT_PAD_GPIO_B1_04__ENET_enet_rx_data0 0xb0e9
IMXRT_PAD_GPIO_B1_05__ENET_enet_rx_data1 0xb0e9
IMXRT_PAD_GPIO_B1_06__ENET_enet_rx_en 0xb0e9
IMXRT_PAD_GPIO_B1_07__ENET_enet_tx_data0 0xb0e9
IMXRT_PAD_GPIO_B1_08__ENET_enet_tx_data1 0xb0e9
IMXRT_PAD_GPIO_B1_09__ENET_enet_tx_en 0xb0e9
IMXRT_PAD_GPIO_B1_10__ENET_enet_ref_clk 0x40000031
IMXRT_PAD_GPIO_B1_11__ENET_enet_rx_er 0xb0e9
/* ENET_RST */
IMXRT_PAD_GPIO_AD_B0_09__GPIO1_gpio_io09 0x810
/* ENET_INT */
IMXRT_PAD_GPIO_AD_B0_10__GPIO1_gpio_io10 0xb0a9
>;
};
};
|
