@ifinfo @node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top @end ifinfo @chapter Interrupt Processing @ifinfo @menu * Interrupt Processing Introduction:: * Interrupt Processing Vectoring of Interrupt Handler:: * Interrupt Processing Interrupt Stack Frame:: * Interrupt Processing Interrupt Levels:: * Interrupt Processing Disabling of Interrupts by RTEMS:: * Interrupt Processing Interrupt Stack:: @end menu @end ifinfo @ifinfo @node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing @end ifinfo @section Introduction Different types of processors respond to the occurrence of an interrupt in their own unique fashion. In addition, each processor type provides a control mechanism to allow the proper handling of an interrupt. The processor dependent response to the interrupt modifies the execution state and results in the modification of the execution stream. This modification usually requires that an interrupt handler utilize the provided control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the the processor's response and control mechanisms as they pertain to RTEMS. @ifinfo @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Stack Frame, Interrupt Processing Introduction, Interrupt Processing @end ifinfo @section Vectoring of Interrupt Handler Although the i386 supports multiple privilege levels, RTEMS and all user software executes at privilege level 0. This decision was made by the RTEMS designers to enhance compatibility with processors which do not provide sophisticated protection facilities like those of the i386. This decision greatly simplifies the discussion of i386 processing, as one need only consider interrupts without privilege transitions. Upon receipt of an interrupt the i386 automatically performs the following actions: @itemize @bullet @item pushes the EFLAGS register @item pushes the far address of the interrupted instruction @item vectors to the interrupt service routine (ISR). @end itemize A nested interrupt is processed similarly by the i386. @ifinfo @node Interrupt Processing Interrupt Stack Frame, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing @end ifinfo @section Interrupt Stack Frame The structure of the Interrupt Stack Frame for the i386 which is placed on the interrupt stack by the processor in response to an interrupt is as follows: @ifset use-ascii @example @group +----------------------+ | Old EFLAGS Register | ESP+8 +----------+-----------+ | UNUSED | Old CS | ESP+4 +----------+-----------+ | Old EIP | ESP +----------------------+ @end group @end example @end ifset @ifset use-tex @sp 1 @tex \centerline{\vbox{\offinterlineskip\halign{ \strut\vrule#& \hbox to 1.00in{\enskip\hfil#\hfil}& \vrule#& \hbox to 1.00in{\enskip\hfil#\hfil}& \vrule#& \hbox to 0.75in{\enskip\hfil#\hfil} \cr \multispan{4}\hrulefill\cr & \multispan{3} Old EFLAGS Register\quad&&ESP+8\cr \multispan{4}\hrulefill\cr &UNUSED &&Old CS &&ESP+4\cr \multispan{4}\hrulefill\cr & \multispan{3} Old EIP && ESP\cr \multispan{4}\hrulefill\cr }}\hfil} @end tex @end ifset @ifset use-html @html
Old EFLAGS Register | 0x0 | |
UNUSED | Old CS | 0x2 |
Old EIP | 0x4 |