@c @c COPYRIGHT (c) 1988-2002. @c On-Line Applications Research Corporation (OAR). @c All rights reserved. @c @c $Id$ @c @ifinfo @end ifinfo @chapter M68xxx and Coldfire Specific Information This chapter discusses the Freescale (formerly Motorola) MC68xxx and Coldfire architectural dependencies. The MC68xxx family has a wide variety of CPU models within it based upon different CPU core implementations. Ignoring the Coldfire parts, the part numbers for these models are generally divided into MC680xx and MC683xx. The MC680xx models are more general purpose processors with no integrated peripherals. The MC683xx models, on the other hand, are more specialized and have a variety of peripherals on chip including sophisticated timers and serial communications controllers. @subheading Architecture Documents For information on the MC68xxx and Coldfire architecture, refer to the following documents available from Freescale website (@file{http//www.freescale.com/}): @itemize @bullet @item @cite{M68000 Family Reference, Motorola, FR68K/D}. @item @cite{MC68020 User's Manual, Motorola, MC68020UM/AD}. @item @cite{MC68881/MC68882 Floating-Point Coprocessor User's Manual, Motorola, MC68881UM/AD}. @end itemize @c @c @c @section CPU Model Dependent Features This section presents the set of features which vary across m68k/Coldfire implementations that are of importance to RTEMS. The set of CPU model feature macros are defined in the file @code{cpukit/score/cpu/m68k/m68k.h} based upon the particular CPU model selected on the compilation command line. @subsection BFFFO Instruction The macro @code{M68K_HAS_BFFFO} is set to 1 to indicate that this CPU model has the bfffo instruction. @subsection Vector Base Register The macro @code{M68K_HAS_VBR} is set to 1 to indicate that this CPU model has a vector base register (vbr). @subsection Separate Stacks The macro @code{M68K_HAS_SEPARATE_STACKS} is set to 1 to indicate that this CPU model has separate interrupt, user, and supervisor mode stacks. @subsection Pre-Indexing Address Mode The macro @code{M68K_HAS_PREINDEXING} is set to 1 to indicate that this CPU model has the pre-indexing address mode. @subsection Extend Byte to Long Instruction The macro @code{M68K_HAS_EXTB_L} is set to 1 to indicate that this CPU model has the extb.l instruction. This instruction is supposed to be available in all models based on the cpu32 core as well as mc68020 and up models. @c @c @c @section Calling Conventions The MC68xxx architecture supports a simple yet effective call and return mechanism. A subroutine is invoked via the branch to subroutine (@code{bsr}) or the jump to subroutine (@code{jsr}) instructions. These instructions push the return address on the current stack. The return from subroutine (@code{rts}) instruction pops the return address off the current stack and transfers control to that instruction. It is is important to note that the MC68xxx call and return mechanism does not automatically save or restore any registers. It is the responsibility of the high-level language compiler to define the register preservation and usage convention. @subsection Calling Mechanism All RTEMS directives are invoked using either a @code{bsr} or @code{jsr} instruction and return to the user application via the rts instruction. @subsection Register Usage As discussed above, the @code{bsr} and @code{jsr} instructions do not automatically save any registers. RTEMS uses the registers D0, D1, A0, and A1 as scratch registers. These registers are not preserved by RTEMS directives therefore, the contents of these registers should not be assumed upon return from any RTEMS directive. @subsection Parameter Passing RTEMS assumes that arguments are placed on the current stack before the directive is invoked via the bsr or jsr instruction. The first argument is assumed to be closest to the return address on the stack. This means that the first argument of the C calling sequence is pushed last. The following pseudo-code illustrates the typical sequence used to call a RTEMS directive with three (3) arguments: @example @group push third argument push second argument push first argument invoke directive remove arguments from the stack @end group @end example The arguments to RTEMS are typically pushed onto the stack using a move instruction with a pre-decremented stack pointer as the destination. These arguments must be removed from the stack after control is returned to the caller. This removal is typically accomplished by adding the size of the argument list in bytes to the current stack pointer. @c @c @c @section Memory Model The MC68xxx family supports a flat 32-bit address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a 32-bit value and is byte addressable. The address may be used to reference a single byte, word (2-bytes), or long word (4 bytes). Memory accesses within this address space are performed in big endian fashion by the processors in this family. Some of the MC68xxx family members such as the MC68020, MC68030, and MC68040 support virtual memory and segmentation. The MC68020 requires external hardware support such as the MC68851 Paged Memory Management Unit coprocessor which is typically used to perform address translations for these systems. RTEMS does not support virtual memory or segmentation on any of the MC68xxx family members. @c @c @c @section Interrupt Processing Discussed in this section are the MC68xxx's interrupt response and control mechanisms as they pertain to RTEMS. @subsection Vectoring of an Interrupt Handler Depending on whether or not the particular CPU supports a separate interrupt stack, the MC68xxx family has two different interrupt handling models. @subsubsection Models Without Separate Interrupt Stacks Upon receipt of an interrupt the MC68xxx family members without separate interrupt stacks automatically perform the following actions: @itemize @bullet @item To Be Written @end itemize @subsubsection Models With Separate Interrupt Stacks Upon receipt of an interrupt the MC68xxx family members with separate interrupt stacks automatically perform the following actions: @itemize @bullet @item saves the current status register (SR), @item clears the master/interrupt (M) bit of the SR to indicate the switch from master state to interrupt state, @item sets the privilege mode to supervisor, @item suppresses tracing, @item sets the interrupt mask level equal to the level of the interrupt being serviced, @item pushes an interrupt stack frame (ISF), which includes the program counter (PC), the status register (SR), and the format/exception vector offset (FVO) word, onto the supervisor and interrupt stacks, @item switches the current stack to the interrupt stack and vectors to an interrupt service routine (ISR). If the ISR was installed with the interrupt_catch directive, then the RTEMS interrupt handler will begin execution. The RTEMS interrupt handler saves all registers which are not preserved according to the calling conventions and invokes the application's ISR. @end itemize A nested interrupt is processed similarly by these CPU models with the exception that only a single ISF is placed on the interrupt stack and the current stack need not be switched. The FVO word in the Interrupt Stack Frame is examined by RTEMS to determine when an outer most interrupt is being exited. Since the FVO is used by RTEMS for this purpose, the user application code MUST NOT modify this field. The following shows the Interrupt Stack Frame for MC68xxx CPU models with separate interrupt stacks: @ifset use-ascii @example @group +----------------------+ | Status Register | 0x0 +----------------------+ | Program Counter High | 0x2 +----------------------+ | Program Counter Low | 0x4 +----------------------+ | Format/Vector Offset | 0x6 +----------------------+ @end group @end example @end ifset @ifset use-tex @sp 1 @tex \centerline{\vbox{\offinterlineskip\halign{ \strut\vrule#& \hbox to 2.00in{\enskip\hfil#\hfil}& \vrule#& \hbox to 0.50in{\enskip\hfil#\hfil} \cr \multispan{3}\hrulefill\cr & Status Register && 0x0\cr \multispan{3}\hrulefill\cr & Program Counter High && 0x2\cr \multispan{3}\hrulefill\cr & Program Counter Low && 0x4\cr \multispan{3}\hrulefill\cr & Format/Vector Offset && 0x6\cr \multispan{3}\hrulefill\cr }}\hfil} @end tex @end ifset @ifset use-html @html
Status Register | 0x0 |
Program Counter High | 0x2 |
Program Counter Low | 0x4 |
Format/Vector Offset | 0x6 |