@c @c COPYRIGHT (c) 1988-2002. @c On-Line Applications Research Corporation (OAR). @c All rights reserved. @ifinfo @end ifinfo @chapter Intel/AMD x86 Specific Information This chapter discusses the Intel x86 architecture dependencies in this port of RTEMS. This family has multiple implementations from multiple vendors and suffers more from having evolved rather than being designed for growth. For information on the i386 processor, refer to the following documents: @itemize @bullet @item @cite{386 Programmer's Reference Manual, Intel, Order No. 230985-002}. @item @cite{386 Microprocessor Hardware Reference Manual, Intel, Order No. 231732-003}. @item @cite{80386 System Software Writer's Guide, Intel, Order No. 231499-001}. @item @cite{80387 Programmer's Reference Manual, Intel, Order No. 231917-001}. @end itemize @c @c @c @section CPU Model Dependent Features This section presents the set of features which vary across i386 implementations and are of importance to RTEMS. The set of CPU model feature macros are defined in the file @code{cpukit/score/cpu/i386/i386.h} based upon the particular CPU model specified on the compilation command line. @subsection bswap Instruction The macro @code{I386_HAS_BSWAP} is set to 1 to indicate that this CPU model has the @code{bswap} instruction which endian swaps a thirty-two bit quantity. This instruction appears to be present in all CPU models i486's and above. @c @c @c @section Calling Conventions @subsection Processor Background The i386 architecture supports a simple yet effective call and return mechanism. A subroutine is invoked via the call (@code{call}) instruction. This instruction pushes the return address on the stack. The return from subroutine (@code{ret}) instruction pops the return address off the current stack and transfers control to that instruction. It is is important to note that the i386 call and return mechanism does not automatically save or restore any registers. It is the responsibility of the high-level language compiler to define the register preservation and usage convention. @subsection Calling Mechanism All RTEMS directives are invoked using a call instruction and return to the user application via the ret instruction. @subsection Register Usage As discussed above, the call instruction does not automatically save any registers. RTEMS uses the registers EAX, ECX, and EDX as scratch registers. These registers are not preserved by RTEMS directives therefore, the contents of these registers should not be assumed upon return from any RTEMS directive. @subsection Parameter Passing RTEMS assumes that arguments are placed on the current stack before the directive is invoked via the call instruction. The first argument is assumed to be closest to the return address on the stack. This means that the first argument of the C calling sequence is pushed last. The following pseudo-code illustrates the typical sequence used to call a RTEMS directive with three (3) arguments: @example push third argument push second argument push first argument invoke directive remove arguments from the stack @end example The arguments to RTEMS are typically pushed onto the stack using a push instruction. These arguments must be removed from the stack after control is returned to the caller. This removal is typically accomplished by adding the size of the argument list in bytes to the stack pointer. @c @c @c @section Memory Model @subsection Flat Memory Model RTEMS supports the i386 protected mode, flat memory model with paging disabled. In this mode, the i386 automatically converts every address from a logical to a physical address each time it is used. The i386 uses information provided in the segment registers and the Global Descriptor Table to convert these addresses. RTEMS assumes the existence of the following segments: @itemize @bullet @item a single code segment at protection level (0) which contains all application and executive code. @item a single data segment at protection level zero (0) which contains all application and executive data. @end itemize The i386 segment registers and associated selectors must be initialized when the initialize_executive directive is invoked. RTEMS treats the segment registers as system registers and does not modify or context switch them. This i386 memory model supports a flat 32-bit address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a 32-bit value and is byte addressable. The address may be used to reference a single byte, half-word (2-bytes), or word (4 bytes). @c @c @c @section Interrupt Processing Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the the processor's response and control mechanisms as they pertain to RTEMS. @subsection Vectoring of Interrupt Handler Although the i386 supports multiple privilege levels, RTEMS and all user software executes at privilege level 0. This decision was made by the RTEMS designers to enhance compatibility with processors which do not provide sophisticated protection facilities like those of the i386. This decision greatly simplifies the discussion of i386 processing, as one need only consider interrupts without privilege transitions. Upon receipt of an interrupt the i386 automatically performs the following actions: @itemize @bullet @item pushes the EFLAGS register @item pushes the far address of the interrupted instruction @item vectors to the interrupt service routine (ISR). @end itemize A nested interrupt is processed similarly by the i386. @subsection Interrupt Stack Frame The structure of the Interrupt Stack Frame for the i386 which is placed on the interrupt stack by the processor in response to an interrupt is as follows: @ifset use-ascii @example @group +----------------------+ | Old EFLAGS Register | ESP+8 +----------+-----------+ | UNUSED | Old CS | ESP+4 +----------+-----------+ | Old EIP | ESP +----------------------+ @end group @end example @end ifset @ifset use-tex @sp 1 @tex \centerline{\vbox{\offinterlineskip\halign{ \strut\vrule#& \hbox to 1.00in{\enskip\hfil#\hfil}& \vrule#& \hbox to 1.00in{\enskip\hfil#\hfil}& \vrule#& \hbox to 0.75in{\enskip\hfil#\hfil} \cr \multispan{4}\hrulefill\cr & \multispan{3} Old EFLAGS Register\quad&&ESP+8\cr \multispan{4}\hrulefill\cr &UNUSED &&Old CS &&ESP+4\cr \multispan{4}\hrulefill\cr & \multispan{3} Old EIP && ESP\cr \multispan{4}\hrulefill\cr }}\hfil} @end tex @end ifset @ifset use-html @html
Old EFLAGS Register | 0x0 | |
UNUSED | Old CS | 0x2 |
Old EIP | 0x4 |