/** * @file * * @ingroup bsp_interrupt * * @brief interrupt definitions. */ /* * COPYRIGHT (c) 1989-2012. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.org/license/LICENSE. */ #ifndef LIBBSP_MIPS_MONGOOSEV_IRQ_H #define LIBBSP_MIPS_MONGOOSEV_IRQ_H #ifndef ASM #include #include #include #include #endif /** * @addtogroup bsp_interrupt * * @{ */ /* * Interrupt Vector Numbers * * NOTE: IRQ INT5 is logical or of peripheral cause register * per p. 5-22 of Mongoose-V manual. */ #define BSP_INTERRUPT_VECTOR_MIN 0 #define MONGOOSEV_IRQ_INT0 MIPS_INTERRUPT_BASE+0 #define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0 #define MONGOOSEV_IRQ_INT1 MIPS_INTERRUPT_BASE+1 #define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1 #define MONGOOSEV_IRQ_INT2 MIPS_INTERRUPT_BASE+2 #define MONGOOSEV_IRQ_INT3 MIPS_INTERRUPT_BASE+3 #define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3 #define MONGOOSEV_IRQ_INT4 MIPS_INTERRUPT_BASE+4 /* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */ #define MONGOOSEV_IRQ_PERIPHERAL_BASE MIPS_INTERRUPT_BASE+5 #define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0 #define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1 #define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2 #define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3 #define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4 #define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5 #define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6 #define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7 #define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8 #define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9 #define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10 #define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11 #define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12 #define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13 #define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14 #define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15 #define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16 #define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17 #define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18 #define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19 #define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20 #define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21 #define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22 #define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23 #define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24 #define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25 #define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26 #define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27 #define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28 #define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29 #define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30 #define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31 #define MONGOOSEV_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+37 #define MONGOOSEV_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+38 #define MONGOOSEV_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+39 #define BSP_INTERRUPT_VECTOR_MAX MONGOOSEV_MAXIMUM_VECTORS /** @} */ #endif /* LIBBSP_MIPS_MONGOOSEV_IRQ_H */