/** * @file bspstart.c * * @ingroup tms570 * * @brief Startup code. */ /* * Copyright (c) 2014 Premysl Houdek * * Google Summer of Code 2014 at * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * * Based on LPC24xx and LPC1768 BSP * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.org/license/LICENSE. */ #include #include #include #include #include #include #include void bsp_start( void ) { #if BYTE_ORDER == BIG_ENDIAN /* * If CPU is big endian (TMS570 family variant) * set the CPU mode to supervisor and big endian. * Do not set mode if CPU is little endian * (RM48 family variant) for which default mode 0x13 * defined in cpukit/score/cpu/arm/cpu.c * is right. */ arm_cpu_mode = 0x213; #endif tms570_initialize_and_clear(); /* * If RTEMS image does not start at address 0x00000000 * then first level exception table at memory begin has * to be replaced to point to RTEMS handlers addresses. * * There is no VBAR or other option because Cortex-R * does provides only fixed address 0x00000000 for exceptions * (0xFFFF0000-0xFFFF001C alternative SCTLR.V = 1 cannot * be used because target area corersponds to PMM peripheral * registers on TMS570). * * Alternative is to use jumps over SRAM based trampolines * but that is not compatible with * Check TCRAM1 ECC error detection logic * which intentionally introduces data abort during startup * to check SRAM and if exception processing goes through * SRAM then it leads to CPU error halt. * * So use of POM to replace jumps to vectors target * addresses seems to be the best option. */ if ( (uintptr_t)bsp_start_vector_table_begin != 0 ) { tms570_pom_remap(); } /* Interrupts */ bsp_interrupt_initialize(); }