From 32e472a7656d1eaebc22b22e99859e1247a89041 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 7 Sep 2021 13:56:42 +0200 Subject: validation: Test Signal Manager The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716. --- spec/build/testsuites/validation/validation-one-cpu-0.yml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'spec/build/testsuites/validation/validation-one-cpu-0.yml') diff --git a/spec/build/testsuites/validation/validation-one-cpu-0.yml b/spec/build/testsuites/validation/validation-one-cpu-0.yml index d6518c33cd..bcea57fee9 100644 --- a/spec/build/testsuites/validation/validation-one-cpu-0.yml +++ b/spec/build/testsuites/validation/validation-one-cpu-0.yml @@ -19,6 +19,8 @@ source: - testsuites/validation/tc-ratemon-timeout.c - testsuites/validation/tc-sem-delete.c - testsuites/validation/tc-sem-uni.c +- testsuites/validation/tc-signal-catch.c +- testsuites/validation/tc-signal-send.c - testsuites/validation/tc-score-fatal.c - testsuites/validation/ts-validation-one-cpu-0.c stlib: [] -- cgit v1.2.3