From 6b0d3c987349d188b65e9fc8229daeba247928c5 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 19 Sep 2022 18:30:26 +0530 Subject: bsps/riscv: Add Microchip PolarFire SoC BSP variant The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART. --- spec/build/bsps/riscv/optextirqmax.yml | 5 ++++- spec/build/bsps/riscv/optrambegin.yml | 5 ++++- spec/build/bsps/riscv/optramsize.yml | 5 ++++- spec/build/bsps/riscv/riscv/abi.yml | 6 ++++++ spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml | 19 +++++++++++++++++++ spec/build/bsps/riscv/riscv/grp.yml | 6 ++++++ spec/build/bsps/riscv/riscv/optmpfs.yml | 18 ++++++++++++++++++ spec/build/bsps/riscv/riscv/optns16550max.yml | 3 +++ 8 files changed, 64 insertions(+), 3 deletions(-) create mode 100644 spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml create mode 100644 spec/build/bsps/riscv/riscv/optmpfs.yml (limited to 'spec/build/bsps') diff --git a/spec/build/bsps/riscv/optextirqmax.yml b/spec/build/bsps/riscv/optextirqmax.yml index ffa84748b6..84dbbb7705 100644 --- a/spec/build/bsps/riscv/optextirqmax.yml +++ b/spec/build/bsps/riscv/optextirqmax.yml @@ -6,7 +6,10 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 64 -default-by-variant: [] +default-by-variant: +- value: 187 + variants: + - riscv/mpfs64.* description: | maximum number of external interrupts supported by the BSP (default 64) enabled-by: true diff --git a/spec/build/bsps/riscv/optrambegin.yml b/spec/build/bsps/riscv/optrambegin.yml index 4a867a1921..90133411cf 100644 --- a/spec/build/bsps/riscv/optrambegin.yml +++ b/spec/build/bsps/riscv/optrambegin.yml @@ -1,7 +1,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause actions: - get-integer: null -- assert-uint32: null +- assert-uint64: null - assert-aligned: 1048576 - env-assign: null - format-and-define: null @@ -22,6 +22,9 @@ default-by-variant: - value: 1073741824 variants: - riscv/griscv +- value: 68719476736 + variants: + - riscv/mpfs64.* description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/riscv/optramsize.yml b/spec/build/bsps/riscv/optramsize.yml index cd58dbd504..316cc906de 100644 --- a/spec/build/bsps/riscv/optramsize.yml +++ b/spec/build/bsps/riscv/optramsize.yml @@ -1,7 +1,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause actions: - get-integer: null -- assert-uint32: null +- assert-uint64: null - assert-aligned: 1048576 - env-assign: null - format-and-define: null @@ -16,6 +16,9 @@ default-by-variant: - value: 16777216 variants: - riscv/griscv +- value: 268435456 + variants: + - riscv/mpfs64.* description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/riscv/riscv/abi.yml b/spec/build/bsps/riscv/riscv/abi.yml index e975b87c4c..3ef8b0681d 100644 --- a/spec/build/bsps/riscv/riscv/abi.yml +++ b/spec/build/bsps/riscv/riscv/abi.yml @@ -10,6 +10,12 @@ default: - -march=rv32imac - -mabi=ilp32 default-by-variant: +- value: + - -march=rv64imafdc + - -mabi=lp64d + - -mcmodel=medany + variants: + - riscv/mpfs64imafdc - value: - -march=rv64imafdc - -mabi=lp64d diff --git a/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml new file mode 100644 index 0000000000..c12703d79b --- /dev/null +++ b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: mpfs64imafdc +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/riscv/riscv/grp.yml b/spec/build/bsps/riscv/riscv/grp.yml index 7f773d91ee..713c15509a 100644 --- a/spec/build/bsps/riscv/riscv/grp.yml +++ b/spec/build/bsps/riscv/riscv/grp.yml @@ -44,10 +44,16 @@ links: uid: ../../optfdtro - role: build-dependency uid: ../../optfdtuboot +- role: build-dependency + uid: ../../optdtb +- role: build-dependency + uid: ../../optdtbheaderpath - role: build-dependency uid: optfrdme310arty - role: build-dependency uid: opthtif +- role: build-dependency + uid: optmpfs - role: build-dependency uid: optns16550max - role: build-dependency diff --git a/spec/build/bsps/riscv/riscv/optmpfs.yml b/spec/build/bsps/riscv/riscv/optmpfs.yml new file mode 100644 index 0000000000..17614567e3 --- /dev/null +++ b/spec/build/bsps/riscv/riscv/optmpfs.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: false +default-by-variant: +- value: true + variants: + - riscv/mpfs64.* +description: | + enables support Microchip PolarFire SoC if defined to a non-zero value,otherwise it is disabled (disabled by default) +enabled-by: true +links: [] +name: RISCV_ENABLE_MPFS_SUPPORT +type: build diff --git a/spec/build/bsps/riscv/riscv/optns16550max.yml b/spec/build/bsps/riscv/riscv/optns16550max.yml index 7e385a57b7..66189cfdfd 100644 --- a/spec/build/bsps/riscv/riscv/optns16550max.yml +++ b/spec/build/bsps/riscv/riscv/optns16550max.yml @@ -10,6 +10,9 @@ default-by-variant: - value: null variants: - riscv/frdme310arty.* +- value: 1 + variants: + - riscv/mpfs64.* description: | maximum number of NS16550 devices supported by the console driver (2 by default) enabled-by: true -- cgit v1.2.3