From 6b0d3c987349d188b65e9fc8229daeba247928c5 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 19 Sep 2022 18:30:26 +0530 Subject: bsps/riscv: Add Microchip PolarFire SoC BSP variant The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART. --- spec/build/bsps/riscv/optrambegin.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'spec/build/bsps/riscv/optrambegin.yml') diff --git a/spec/build/bsps/riscv/optrambegin.yml b/spec/build/bsps/riscv/optrambegin.yml index 4a867a1921..90133411cf 100644 --- a/spec/build/bsps/riscv/optrambegin.yml +++ b/spec/build/bsps/riscv/optrambegin.yml @@ -1,7 +1,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause actions: - get-integer: null -- assert-uint32: null +- assert-uint64: null - assert-aligned: 1048576 - env-assign: null - format-and-define: null @@ -22,6 +22,9 @@ default-by-variant: - value: 1073741824 variants: - riscv/griscv +- value: 68719476736 + variants: + - riscv/mpfs64.* description: '' enabled-by: true format: '{:#010x}' -- cgit v1.2.3