From f3f0370f1054f4e49aa8f5ea70485d673e8e94b6 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 19 Jul 2019 13:09:43 +0200 Subject: build: Alternative build system based on waf Update #3818. --- spec/build/bsps/arm/xilinx-zynq/abi.yml | 21 +++++++ spec/build/bsps/arm/xilinx-zynq/bspqemu.yml | 19 +++++++ spec/build/bsps/arm/xilinx-zynq/bspzc702.yml | 19 +++++++ spec/build/bsps/arm/xilinx-zynq/bspzc706.yml | 19 +++++++ spec/build/bsps/arm/xilinx-zynq/bspzedboard.yml | 19 +++++++ spec/build/bsps/arm/xilinx-zynq/grp.yml | 64 ++++++++++++++++++++++ spec/build/bsps/arm/xilinx-zynq/linkcmds.yml | 46 ++++++++++++++++ spec/build/bsps/arm/xilinx-zynq/obj.yml | 47 ++++++++++++++++ spec/build/bsps/arm/xilinx-zynq/objsmp.yml | 16 ++++++ spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml | 22 ++++++++ spec/build/bsps/arm/xilinx-zynq/optcachedata.yml | 18 ++++++ spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml | 18 ++++++ spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml | 22 ++++++++ spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml | 18 ++++++ spec/build/bsps/arm/xilinx-zynq/optclkuart.yml | 22 ++++++++ spec/build/bsps/arm/xilinx-zynq/optconirq.yml | 15 +++++ spec/build/bsps/arm/xilinx-zynq/optconminor.yml | 15 +++++ spec/build/bsps/arm/xilinx-zynq/optint0len.yml | 17 ++++++ spec/build/bsps/arm/xilinx-zynq/optint0ori.yml | 17 ++++++ spec/build/bsps/arm/xilinx-zynq/optint1len.yml | 17 ++++++ spec/build/bsps/arm/xilinx-zynq/optint1ori.yml | 17 ++++++ spec/build/bsps/arm/xilinx-zynq/optnocachelen.yml | 18 ++++++ spec/build/bsps/arm/xilinx-zynq/optramlen.yml | 30 ++++++++++ spec/build/bsps/arm/xilinx-zynq/optramori.yml | 21 +++++++ spec/build/bsps/arm/xilinx-zynq/optresetvec.yml | 15 +++++ 25 files changed, 572 insertions(+) create mode 100644 spec/build/bsps/arm/xilinx-zynq/abi.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspqemu.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspzc702.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspzc706.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/bspzedboard.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/grp.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/linkcmds.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/obj.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/objsmp.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optcachedata.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optclkuart.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optconirq.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optconminor.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optint0len.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optint0ori.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optint1len.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optint1ori.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optnocachelen.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optramlen.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optramori.yml create mode 100644 spec/build/bsps/arm/xilinx-zynq/optresetvec.yml (limited to 'spec/build/bsps/arm/xilinx-zynq') diff --git a/spec/build/bsps/arm/xilinx-zynq/abi.yml b/spec/build/bsps/arm/xilinx-zynq/abi.yml new file mode 100644 index 0000000000..a3a710c97d --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/abi.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: +- -march=armv7-a +- -mthumb +- -mfpu=neon +- -mfloat-abi=hard +- -mtune=cortex-a9 +default-by-variant: [] +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/bspqemu.yml b/spec/build/bsps/arm/xilinx-zynq/bspqemu.yml new file mode 100644 index 0000000000..a8f59548d9 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/bspqemu.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: xilinx_zynq_a9_qemu +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: xilinx-zynq +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +- role: build-dependency + uid: ../../opto2 +source: [] +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/bspzc702.yml b/spec/build/bsps/arm/xilinx-zynq/bspzc702.yml new file mode 100644 index 0000000000..683c2c7b8c --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/bspzc702.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: xilinx_zynq_zc702 +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: xilinx-zynq +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +- role: build-dependency + uid: ../../opto2 +source: [] +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/bspzc706.yml b/spec/build/bsps/arm/xilinx-zynq/bspzc706.yml new file mode 100644 index 0000000000..eca7aaf46c --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/bspzc706.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: xilinx_zynq_zc706 +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: xilinx-zynq +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +- role: build-dependency + uid: ../../opto2 +source: [] +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/bspzedboard.yml b/spec/build/bsps/arm/xilinx-zynq/bspzedboard.yml new file mode 100644 index 0000000000..ba285c1b80 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/bspzedboard.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: xilinx_zynq_zedboard +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: xilinx-zynq +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +- role: build-dependency + uid: ../../opto2 +source: [] +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml b/spec/build/bsps/arm/xilinx-zynq/grp.yml new file mode 100644 index 0000000000..264308e6ad --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml @@ -0,0 +1,64 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +includes: [] +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: abi +- role: build-dependency + uid: obj +- role: build-dependency + uid: objsmp +- role: build-dependency + uid: opta9periphclk +- role: build-dependency + uid: optcachedata +- role: build-dependency + uid: optcacheinst +- role: build-dependency + uid: optclkcpu1x +- role: build-dependency + uid: optclkfastidle +- role: build-dependency + uid: optclkuart +- role: build-dependency + uid: optconirq +- role: build-dependency + uid: optconminor +- role: build-dependency + uid: optint0len +- role: build-dependency + uid: optint0ori +- role: build-dependency + uid: optint1len +- role: build-dependency + uid: optint1ori +- role: build-dependency + uid: ../optmmusz +- role: build-dependency + uid: optnocachelen +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: optresetvec +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: ../../bspopts +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/arm/xilinx-zynq/linkcmds.yml b/spec/build/bsps/arm/xilinx-zynq/linkcmds.yml new file mode 100644 index 0000000000..d7c0934f78 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/linkcmds.yml @@ -0,0 +1,46 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + MEMORY { + RAM_INT_0 : ORIGIN = ${ZYNQ_RAM_INT_0_ORIGIN:#010x}, LENGTH = ${ZYNQ_RAM_INT_0_LENGTH:#010x} + RAM_INT_1 : ORIGIN = ${ZYNQ_RAM_INT_1_ORIGIN:#010x}, LENGTH = ${ZYNQ_RAM_INT_1_LENGTH:#010x} + RAM_MMU : ORIGIN = ${ZYNQ_RAM_ORIGIN:#010x}, LENGTH = ${ARM_MMU_TRANSLATION_TABLE_SIZE:#010x} + RAM : ORIGIN = ${ZYNQ_RAM_ORIGIN:#010x} + ${ARM_MMU_TRANSLATION_TABLE_SIZE:#010x}, LENGTH = ${ZYNQ_RAM_LENGTH:#010x} - ${ZYNQ_RAM_ORIGIN:#010x} - ${ARM_MMU_TRANSLATION_TABLE_SIZE:#010x} - ${ZYNQ_RAM_NOCACHE_LENGTH:#010x} + NOCACHE : ORIGIN = ${ZYNQ_RAM_LENGTH:#010x} - ${ZYNQ_RAM_NOCACHE_LENGTH:#010x}, LENGTH = ${ZYNQ_RAM_NOCACHE_LENGTH:#010x} + } + + REGION_ALIAS ("REGION_START", RAM); + REGION_ALIAS ("REGION_VECTOR", RAM); + REGION_ALIAS ("REGION_TEXT", RAM); + REGION_ALIAS ("REGION_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_RODATA", RAM); + REGION_ALIAS ("REGION_RODATA_LOAD", RAM); + REGION_ALIAS ("REGION_DATA", RAM); + REGION_ALIAS ("REGION_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_TEXT", RAM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_DATA", RAM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_BSS", RAM); + REGION_ALIAS ("REGION_WORK", RAM); + REGION_ALIAS ("REGION_STACK", RAM); + REGION_ALIAS ("REGION_NOCACHE", NOCACHE); + REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE); + + bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; + + bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; + + bsp_vector_table_in_start_section = 1; + + bsp_translation_table_base = ORIGIN (RAM_MMU); + bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU); + + INCLUDE linkcmds.armv4 +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml b/spec/build/bsps/arm/xilinx-zynq/obj.yml new file mode 100644 index 0000000000..6f7f8ab39a --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml @@ -0,0 +1,47 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/xilinx-zynq/include/bsp.h + - bsps/arm/xilinx-zynq/include/tm27.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h + - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h + - bsps/arm/xilinx-zynq/include/bsp/i2c.h + - bsps/arm/xilinx-zynq/include/bsp/irq.h +links: [] +source: +- bsps/arm/shared/cache/cache-l2c-310.c +- bsps/arm/shared/clock/clock-a9mpcore.c +- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c +- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c +- bsps/arm/shared/irq/irq-gic.c +- bsps/arm/shared/serial/zynq-uart.c +- bsps/arm/shared/serial/zynq-uart-polled.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/xilinx-zynq/console/console-config.c +- bsps/arm/xilinx-zynq/console/console-init.c +- bsps/arm/xilinx-zynq/console/debug-console.c +- bsps/arm/xilinx-zynq/i2c/cadence-i2c.c +- bsps/arm/xilinx-zynq/start/bspreset.c +- bsps/arm/xilinx-zynq/start/bspstart.c +- bsps/arm/xilinx-zynq/start/bspstarthooks.c +- bsps/arm/xilinx-zynq/start/bspstartmmu.c +- bsps/shared/dev/btimer/btimer-stub.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/bspgetworkarea-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/objsmp.yml b/spec/build/bsps/arm/xilinx-zynq/objsmp.yml new file mode 100644 index 0000000000..587884f6a3 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/objsmp.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: +- RTEMS_SMP +includes: [] +install: [] +links: [] +source: +- bsps/arm/shared/start/arm-a9mpcore-smp.c +- bsps/arm/xilinx-zynq/start/bspsmp.c +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml new file mode 100644 index 0000000000..0b10b47bc2 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml @@ -0,0 +1,22 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 100000000 +default-by-variant: +- value: 333333333 + variants: + - arm/xilinx_zynq_zc702.* +- value: 666666667 + variants: + - arm/xilinx_zynq_zedboard.* +description: | + ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz +enabled-by: true +format: '{}' +links: [] +name: BSP_ARM_A9MPCORE_PERIPHCLK +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml b/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml new file mode 100644 index 0000000000..1664b0fc31 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: +- value: false + variants: + - arm/.*qemu +description: | + enable data cache +enabled-by: true +links: [] +name: BSP_DATA_CACHE_ENABLED +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml b/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml new file mode 100644 index 0000000000..b191133af9 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: +- value: false + variants: + - arm/.*qemu +description: | + enable instruction cache +enabled-by: true +links: [] +name: BSP_INSTRUCTION_CACHE_ENABLED +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml b/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml new file mode 100644 index 0000000000..1f93f52a8a --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml @@ -0,0 +1,22 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 111111111 +default-by-variant: +- value: 111111111 + variants: + - arm/xilinx_zynq_zc702.* +- value: 111111111 + variants: + - arm/xilinx_zynq_zedboard.* +description: | + Zynq cpu_1x clock frequency in Hz +enabled-by: true +format: '{}' +links: [] +name: ZYNQ_CLOCK_CPU_1X +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml new file mode 100644 index 0000000000..b800b20428 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: false +default-by-variant: +- value: true + variants: + - arm/.*qemu +description: | + This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. +enabled-by: true +links: [] +name: CLOCK_DRIVER_USE_FAST_IDLE +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml new file mode 100644 index 0000000000..7d69273eb2 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml @@ -0,0 +1,22 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 50000000 +default-by-variant: +- value: 50000000 + variants: + - arm/xilinx_zynq_zc702.* +- value: 50000000 + variants: + - arm/xilinx_zynq_zedboard.* +description: | + Zynq UART clock frequency in Hz +enabled-by: true +format: '{}' +links: [] +name: ZYNQ_CLOCK_UART +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optconirq.yml b/spec/build/bsps/arm/xilinx-zynq/optconirq.yml new file mode 100644 index 0000000000..ecb91d81a3 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optconirq.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + use interrupt driven mode for console devices (used by default) +enabled-by: true +links: [] +name: ZYNQ_CONSOLE_USE_INTERRUPTS +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optconminor.yml b/spec/build/bsps/arm/xilinx-zynq/optconminor.yml new file mode 100644 index 0000000000..55074c6dac --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optconminor.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + minor number of console device +enabled-by: true +links: [] +name: BSP_CONSOLE_MINOR +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optint0len.yml b/spec/build/bsps/arm/xilinx-zynq/optint0len.yml new file mode 100644 index 0000000000..90d77daeb7 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optint0len.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 196608 +default-by-variant: [] +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_INT_0_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optint0ori.yml b/spec/build/bsps/arm/xilinx-zynq/optint0ori.yml new file mode 100644 index 0000000000..a8c4514fd9 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optint0ori.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 0 +default-by-variant: [] +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_INT_0_ORIGIN +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optint1len.yml b/spec/build/bsps/arm/xilinx-zynq/optint1len.yml new file mode 100644 index 0000000000..32a2c8f3d6 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optint1len.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 65024 +default-by-variant: [] +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_INT_1_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optint1ori.yml b/spec/build/bsps/arm/xilinx-zynq/optint1ori.yml new file mode 100644 index 0000000000..f089c467c4 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optint1ori.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 4294901760 +default-by-variant: [] +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_INT_1_ORIGIN +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optnocachelen.yml b/spec/build/bsps/arm/xilinx-zynq/optnocachelen.yml new file mode 100644 index 0000000000..7a553ab9a2 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optnocachelen.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 1048576 +default-by-variant: [] +description: | + length of nocache RAM region +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_NOCACHE_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optramlen.yml b/spec/build/bsps/arm/xilinx-zynq/optramlen.yml new file mode 100644 index 0000000000..e51d3ebf38 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optramlen.yml @@ -0,0 +1,30 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 268435456 +default-by-variant: +- value: 268435456 + variants: + - arm/xilinx_zynq_a9_qemu +- value: 1073741824 + variants: + - arm/xilinx_zynq_zc702 +- value: 1073741824 + variants: + - arm/xilinx_zynq_zc706 +- value: 536870912 + variants: + - arm/xilinx_zynq_zedboard +description: | + override a BSP's default RAM length +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optramori.yml b/spec/build/bsps/arm/xilinx-zynq/optramori.yml new file mode 100644 index 0000000000..5723b73d53 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optramori.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- assert-aligned: 1048576 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 1048576 +default-by-variant: +- value: 4194304 + variants: + - arm/xilinx_zynq_zc706 +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQ_RAM_ORIGIN +type: build diff --git a/spec/build/bsps/arm/xilinx-zynq/optresetvec.yml b/spec/build/bsps/arm/xilinx-zynq/optresetvec.yml new file mode 100644 index 0000000000..efd1ea2b2a --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynq/optresetvec.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: false +default-by-variant: [] +description: | + reset vector address for BSP start +enabled-by: true +links: [] +name: BSP_START_RESET_VECTOR +type: build -- cgit v1.2.3