From 99494370d6124ef5d773119fa59f5bac4bbf395f Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 4 Mar 2020 12:34:34 +0100 Subject: bsp/stm32h7: New BSP Update #3910. --- spec/build/bsps/arm/stm32h7/.doorstop.yml | 6 + spec/build/bsps/arm/stm32h7/abi.yml | 20 + spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 415 +++++++++++++++++++++ spec/build/bsps/arm/stm32h7/linkcmds.yml | 11 + spec/build/bsps/arm/stm32h7/linkcmdsflash.yml | 49 +++ spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml | 92 +++++ spec/build/bsps/arm/stm32h7/linkcmdssdram.yml | 49 +++ spec/build/bsps/arm/stm32h7/optenmpualign.yml | 20 + spec/build/bsps/arm/stm32h7/optenuart4.yml | 16 + spec/build/bsps/arm/stm32h7/optenuart5.yml | 16 + spec/build/bsps/arm/stm32h7/optenuart7.yml | 16 + spec/build/bsps/arm/stm32h7/optenuart8.yml | 16 + spec/build/bsps/arm/stm32h7/optenuart9.yml | 16 + spec/build/bsps/arm/stm32h7/optenusart1.yml | 16 + spec/build/bsps/arm/stm32h7/optenusart10.yml | 16 + spec/build/bsps/arm/stm32h7/optenusart2.yml | 16 + spec/build/bsps/arm/stm32h7/optenusart3.yml | 16 + spec/build/bsps/arm/stm32h7/optenusart6.yml | 16 + spec/build/bsps/arm/stm32h7/optlinkcmds.yml | 17 + spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemflashsz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemitcmsz.yml | 18 + spec/build/bsps/arm/stm32h7/optmemnandsz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemnorsz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemnullsz.yml | 17 + spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemquadspisz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsram1sz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsram2sz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsram3sz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsram4sz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml | 16 + spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml | 16 + spec/build/bsps/arm/stm32h7/optprintkinstance.yml | 16 + spec/build/bsps/arm/stm32h7/optvariant.yml | 29 ++ 37 files changed, 1143 insertions(+) create mode 100644 spec/build/bsps/arm/stm32h7/.doorstop.yml create mode 100644 spec/build/bsps/arm/stm32h7/abi.yml create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h7.yml create mode 100644 spec/build/bsps/arm/stm32h7/linkcmds.yml create mode 100644 spec/build/bsps/arm/stm32h7/linkcmdsflash.yml create mode 100644 spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml create mode 100644 spec/build/bsps/arm/stm32h7/linkcmdssdram.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenmpualign.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenuart4.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenuart5.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenuart7.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenuart8.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenuart9.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenusart1.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenusart10.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenusart2.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenusart3.yml create mode 100644 spec/build/bsps/arm/stm32h7/optenusart6.yml create mode 100644 spec/build/bsps/arm/stm32h7/optlinkcmds.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemflashsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemitcmsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemnandsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemnorsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemnullsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemquadspisz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsram1sz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsram2sz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsram3sz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsram4sz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml create mode 100644 spec/build/bsps/arm/stm32h7/optprintkinstance.yml create mode 100644 spec/build/bsps/arm/stm32h7/optvariant.yml (limited to 'spec/build/bsps/arm/stm32h7') diff --git a/spec/build/bsps/arm/stm32h7/.doorstop.yml b/spec/build/bsps/arm/stm32h7/.doorstop.yml new file mode 100644 index 0000000000..16950ce80f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/.doorstop.yml @@ -0,0 +1,6 @@ +settings: + digits: 3 + parent: RTEMS-BUILD-BSP-ARM + prefix: RTEMS-BUILD-BSP-ARM-STM32H7 + sep: '-' +attributes: !include ../../../attributes.inc diff --git a/spec/build/bsps/arm/stm32h7/abi.yml b/spec/build/bsps/arm/stm32h7/abi.yml new file mode 100644 index 0000000000..697220b1b1 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/abi.yml @@ -0,0 +1,20 @@ +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +default: +- -mthumb +- -mcpu=cortex-m7 +- -mfpu=fpv5-d16 +- -mfloat-abi=hard +default-by-variant: [] +enabled-by: true +links: [] +name: ABI_FLAGS +description: | + ABI flags +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml new file mode 100644 index 0000000000..9fb7d3611f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -0,0 +1,415 @@ +arch: arm +bsp: stm32h7 +build-type: bsp +cflags: [] +cppflags: [] +enabled-by: true +family: stm32h7 +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/stm32h7/include/bsp.h + - bsps/arm/stm32h7/include/tm27.h + - bsps/arm/stm32h7/include/chip.h + - bsps/arm/stm32h7/include/stm32_assert_template.h + - bsps/arm/stm32h7/include/stm32h742xx.h + - bsps/arm/stm32h7/include/stm32h743xx.h + - bsps/arm/stm32h7/include/stm32h745xx.h + - bsps/arm/stm32h7/include/stm32h747xx.h + - bsps/arm/stm32h7/include/stm32h750xx.h + - bsps/arm/stm32h7/include/stm32h753xx.h + - bsps/arm/stm32h7/include/stm32h755xx.h + - bsps/arm/stm32h7/include/stm32h757xx.h + - bsps/arm/stm32h7/include/stm32h7a3xx.h + - bsps/arm/stm32h7/include/stm32h7a3xxq.h + - bsps/arm/stm32h7/include/stm32h7b0xx.h + - bsps/arm/stm32h7/include/stm32h7b0xxq.h + - bsps/arm/stm32h7/include/stm32h7b3xx.h + - bsps/arm/stm32h7/include/stm32h7b3xxq.h + - bsps/arm/stm32h7/include/stm32h7/hal.h + - bsps/arm/stm32h7/include/stm32h7xx.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_adc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_adc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cec.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_comp.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_conf_template.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cortex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_crc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_crc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cryp_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_cryp.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dac_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dac.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dcmi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_def.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dma2d.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dma_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dma.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dsi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_dts.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_eth_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_eth.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_exti.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_fdcan.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_flash.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_gfxmmu.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_gpio_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_gpio.h + - bsps/arm/stm32h7/include/stm32h7xx_hal.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hash_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hash.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hcd.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hrtim.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_hsem.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2c_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2c.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2s_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_i2s.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_irda_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_irda.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_iwdg.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_jpeg.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_lptim.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mdios.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mdma.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mmc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_mmc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_nand.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_nor.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_opamp_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_opamp.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_otfdec.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pcd_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pcd.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pssi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pwr_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_qspi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_ramecc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rcc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rcc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rng_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rng.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rtc_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_rtc.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sai_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sai.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sd_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sd.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sdram.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_smbus.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_spdifrx.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_spi_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_sram.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_swpmi.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_tim_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_tim.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_uart_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_usart_ex.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_usart.h + - bsps/arm/stm32h7/include/stm32h7xx_hal_wwdg.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_bdma.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_bus.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_comp.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_crc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_crs.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dac.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_delayblock.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dma2d.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_dmamux.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_exti.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_gpio.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_hrtim.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_hsem.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_i2c.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_iwdg.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_lptim.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_lpuart.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_mdma.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_opamp.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_rcc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_rng.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_rtc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_sdmmc.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_swpmi.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_system.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_tim.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_usart.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_usb.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_utils.h + - bsps/arm/stm32h7/include/stm32h7xx_ll_wwdg.h + - bsps/arm/stm32h7/include/system_stm32h7xx.h +- destination: ${BSP_INCLUDEDIR}/Legacy + source: + - bsps/arm/stm32h7/include/Legacy/stm32_hal_legacy.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/stm32h7/include/bsp/irq.h +- destination: ${BSP_INCLUDEDIR}/stm32h7 + source: + - bsps/arm/stm32h7/include/stm32h7/hal.h + - bsps/arm/stm32h7/include/stm32h7/memory.h +- destination: ${BSP_LIBDIR} + source: + - bsps/arm/stm32h7/start/bsp_specs +links: +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: abi +- role: build-dependency + uid: optenmpualign +- role: build-dependency + uid: optenuart4 +- role: build-dependency + uid: optenuart5 +- role: build-dependency + uid: optenuart7 +- role: build-dependency + uid: optenuart8 +- role: build-dependency + uid: optenuart9 +- role: build-dependency + uid: optenusart10 +- role: build-dependency + uid: optenusart1 +- role: build-dependency + uid: optenusart2 +- role: build-dependency + uid: optenusart3 +- role: build-dependency + uid: optenusart6 +- role: build-dependency + uid: optlinkcmds +- role: build-dependency + uid: optmemdtcmsz +- role: build-dependency + uid: optmemflashsz +- role: build-dependency + uid: optmemitcmsz +- role: build-dependency + uid: optmemnandsz +- role: build-dependency + uid: optmemnorsz +- role: build-dependency + uid: optmemnullsz +- role: build-dependency + uid: optmemperipheralsz +- role: build-dependency + uid: optmemquadspisz +- role: build-dependency + uid: optmemsdram1sz +- role: build-dependency + uid: optmemsdram2sz +- role: build-dependency + uid: optmemsram1sz +- role: build-dependency + uid: optmemsram2sz +- role: build-dependency + uid: optmemsram3sz +- role: build-dependency + uid: optmemsram4sz +- role: build-dependency + uid: optmemsramaxisz +- role: build-dependency + uid: optmemsrambackupsz +- role: build-dependency + uid: optprintkinstance +- role: build-dependency + uid: optvariant +- role: build-dependency + uid: ../../optconsolebaud +- role: build-dependency + uid: ../../optconsoleirq +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: linkcmdsflash +- role: build-dependency + uid: linkcmdsmemory +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: linkcmdssdram +- role: build-dependency + uid: ../../bspopts +source: +- bsps/arm/shared/cache/cache-v7m.c +- bsps/arm/shared/clock/clock-armv7m.c +- bsps/arm/shared/cpucounter/cpucounter-armv7m.c +- bsps/arm/shared/irq/irq-armv7m.c +- bsps/arm/shared/irq/irq-dispatch-armv7m.c +- bsps/arm/shared/start/bspreset-armv7m.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/stm32h7/console/console.c +- bsps/arm/stm32h7/console/console-uart4.c +- bsps/arm/stm32h7/console/console-uart5.c +- bsps/arm/stm32h7/console/console-uart7.c +- bsps/arm/stm32h7/console/console-uart8.c +- bsps/arm/stm32h7/console/console-uart9.c +- bsps/arm/stm32h7/console/console-usart10.c +- bsps/arm/stm32h7/console/console-usart1.c +- bsps/arm/stm32h7/console/console-usart2.c +- bsps/arm/stm32h7/console/console-usart3.c +- bsps/arm/stm32h7/console/console-usart6.c +- bsps/arm/stm32h7/console/printk-support.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_adc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_adc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cec.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_comp.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cortex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_crc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_crc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cryp.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_cryp_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dac.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dac_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dcmi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dfsdm.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dfsdm_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dma2d.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dma.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dma_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dsi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_dts.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_eth.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_eth_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_exti.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_fdcan.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_flash.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_gfxmmu.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_gpio.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hash.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hash_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hcd.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hrtim.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_hsem.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2c.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2c_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2s.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_i2s_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_irda.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_iwdg.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_jpeg.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_lptim.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ltdc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ltdc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mdios.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mdma.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mmc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_mmc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_nand.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_nor.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_opamp.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_opamp_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ospi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_otfdec.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pcd.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pcd_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pssi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pwr.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_pwr_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_qspi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_ramecc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rcc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rcc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rng.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rng_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rtc.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_rtc_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sai.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sai_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sd.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sd_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sdram.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_smartcard.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_smartcard_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_smbus.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_spdifrx.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_spi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_spi_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_sram.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_swpmi.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_tim.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_tim_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_uart.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_uart_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_usart.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_usart_ex.c +- bsps/arm/stm32h7/hal/stm32h7xx_hal_wwdg.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_adc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_bdma.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_comp.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_crc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_crs.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_dac.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_delayblock.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_dma2d.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_dma.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_exti.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_fmc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_gpio.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_hrtim.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_i2c.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_lptim.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_lpuart.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_mdma.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_opamp.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_pwr.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_rng.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_rtc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_sdmmc.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_spi.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_swpmi.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_tim.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_usart.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_usb.c +- bsps/arm/stm32h7/hal/stm32h7xx_ll_utils.c +- bsps/arm/stm32h7/start/bspstart.c +- bsps/arm/stm32h7/start/bspstarthooks.c +- bsps/arm/stm32h7/start/ext-mem-ctl.c +- bsps/arm/stm32h7/start/getentropy-rng.c +- bsps/arm/stm32h7/start/stm32h7-config.c +- bsps/arm/stm32h7/start/stm32h7-hal.c +- bsps/arm/stm32h7/start/stm32h7-hal-eth.c +- bsps/arm/stm32h7/start/stm32h7-hal-uart.c +- bsps/arm/stm32h7/start/system_stm32h7xx.c +- bsps/shared/dev/btimer/btimer-stub.c +- bsps/shared/dev/rtc/rtc-support.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/bspgetworkarea-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmds.yml b/spec/build/bsps/arm/stm32h7/linkcmds.yml new file mode 100644 index 0000000000..95f31bbedb --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmds.yml @@ -0,0 +1,11 @@ +build-type: config-file +content: | + INCLUDE ${STM32H7_DEFAULT_LINKCMDS} +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsflash.yml b/spec/build/bsps/arm/stm32h7/linkcmdsflash.yml new file mode 100644 index 0000000000..4785c45b9f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmdsflash.yml @@ -0,0 +1,49 @@ +build-type: script +do-build: | + bld.install_as("${BSP_LIBDIR}/linkcmds.flash", "linkcmds.flash") +do-configure: | + content = """INCLUDE linkcmds.memory + + REGION_ALIAS ("REGION_START", FLASH); + REGION_ALIAS ("REGION_VECTOR", FLASH); + REGION_ALIAS ("REGION_TEXT", FLASH); + REGION_ALIAS ("REGION_TEXT_LOAD", FLASH); + REGION_ALIAS ("REGION_RODATA", FLASH); + REGION_ALIAS ("REGION_RODATA_LOAD", FLASH); + REGION_ALIAS ("REGION_DATA", SRAM_AXI); + REGION_ALIAS ("REGION_DATA_LOAD", FLASH); + REGION_ALIAS ("REGION_FAST_TEXT", ITCM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ITCM); + REGION_ALIAS ("REGION_FAST_DATA", DTCM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", DTCM); + REGION_ALIAS ("REGION_BSS", SRAM_AXI); + REGION_ALIAS ("REGION_WORK", SRAM_AXI); + REGION_ALIAS ("REGION_STACK", SRAM_AXI); + REGION_ALIAS ("REGION_NOCACHE", SRAM_1); + REGION_ALIAS ("REGION_NOCACHE_LOAD", FLASH); + + bsp_vector_table_in_start_section = 1; + """ + + if conf.env.STM32H7_ENABLE_MPU_ALIGNMENT: + content += """ + bsp_align_text_and_rodata_end_to_power_of_2 = 1; + """ + + content += """ + INCLUDE linkcmds.armv7m + """ + f = conf.bldnode.make_node( + conf.env.VARIANT + "/linkcmds.flash" + ) + f.parent.mkdir() + f.write(content) + conf.env.append_value("cfg_files", f.abspath()) +enabled-by: true +links: [] +prepare-build: null +prepare-configure: null +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml new file mode 100644 index 0000000000..7ff7f3da5e --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml @@ -0,0 +1,92 @@ +build-type: config-file +content: | + MEMORY { + NULL : ORIGIN = 0x00000000, LENGTH = ${STM32H7_MEMORY_NULL_SIZE:#010x} + ITCM : ORIGIN = ${STM32H7_MEMORY_NULL_SIZE:#010x}, LENGTH = ${STM32H7_MEMORY_ITCM_SIZE:#010x} + FLASH : ORIGIN = 0x08000000, LENGTH = ${STM32H7_MEMORY_FLASH_SIZE:#010x} + DTCM : ORIGIN = 0x20000000, LENGTH = ${STM32H7_MEMORY_DTCM_SIZE:#010x} + SRAM_AXI : ORIGIN = 0x24000000, LENGTH = ${STM32H7_MEMORY_SRAM_AXI_SIZE:#010x} + SRAM_1 : ORIGIN = 0x30000000, LENGTH = ${STM32H7_MEMORY_SRAM_1_SIZE:#010x} + SRAM_2 : ORIGIN = 0x30020000, LENGTH = ${STM32H7_MEMORY_SRAM_2_SIZE:#010x} + SRAM_3 : ORIGIN = 0x30040000, LENGTH = ${STM32H7_MEMORY_SRAM_3_SIZE:#010x} + SRAM_4 : ORIGIN = 0x38000000, LENGTH = ${STM32H7_MEMORY_SRAM_4_SIZE:#010x} + SRAM_BACKUP : ORIGIN = 0x38800000, LENGTH = ${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x} + PERIPHERAL : ORIGIN = 0x40000000, LENGTH = ${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x} + NOR : ORIGIN = 0x60000000, LENGTH = ${STM32H7_MEMORY_NOR_SIZE:#010x} + SDRAM_1 : ORIGIN = 0x70000000, LENGTH = ${STM32H7_MEMORY_SDRAM_1_SIZE:#010x} + NAND : ORIGIN = 0x80000000, LENGTH = ${STM32H7_MEMORY_NAND_SIZE:#010x} + QUADSPI : ORIGIN = 0x90000000, LENGTH = ${STM32H7_MEMORY_QUADSPI_SIZE:#010x} + SDRAM_2 : ORIGIN = 0xd0000000, LENGTH = ${STM32H7_MEMORY_SDRAM_2_SIZE:#010x} + } + + stm32h7_memory_null_begin = ORIGIN (NULL); + stm32h7_memory_null_end = ORIGIN (NULL) + LENGTH (NULL); + stm32h7_memory_null_size = LENGTH (NULL); + + stm32h7_memory_itcm_begin = ORIGIN (ITCM); + stm32h7_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM); + stm32h7_memory_itcm_size = LENGTH (ITCM); + + stm32h7_memory_flash_begin = ORIGIN (FLASH); + stm32h7_memory_flash_end = ORIGIN (FLASH) + LENGTH (FLASH); + stm32h7_memory_flash_size = LENGTH (FLASH); + + stm32h7_memory_dtcm_begin = ORIGIN (DTCM); + stm32h7_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM); + stm32h7_memory_dtcm_size = LENGTH (DTCM); + + stm32h7_memory_sram_axi_begin = ORIGIN (SRAM_AXI); + stm32h7_memory_sram_axi_end = ORIGIN (SRAM_AXI) + LENGTH (SRAM_AXI); + stm32h7_memory_sram_axi_size = LENGTH (SRAM_AXI); + + stm32h7_memory_sram_1_begin = ORIGIN (SRAM_1); + stm32h7_memory_sram_1_end = ORIGIN (SRAM_1) + LENGTH (SRAM_1); + stm32h7_memory_sram_1_size = LENGTH (SRAM_1); + + stm32h7_memory_sram_2_begin = ORIGIN (SRAM_2); + stm32h7_memory_sram_2_end = ORIGIN (SRAM_2) + LENGTH (SRAM_2); + stm32h7_memory_sram_2_size = LENGTH (SRAM_2); + + stm32h7_memory_sram_3_begin = ORIGIN (SRAM_3); + stm32h7_memory_sram_3_end = ORIGIN (SRAM_3) + LENGTH (SRAM_3); + stm32h7_memory_sram_3_size = LENGTH (SRAM_3); + + stm32h7_memory_sram_4_begin = ORIGIN (SRAM_4); + stm32h7_memory_sram_4_end = ORIGIN (SRAM_4) + LENGTH (SRAM_4); + stm32h7_memory_sram_4_size = LENGTH (SRAM_4); + + stm32h7_memory_sram_backup_begin = ORIGIN (SRAM_BACKUP); + stm32h7_memory_sram_backup_end = ORIGIN (SRAM_BACKUP) + LENGTH (SRAM_BACKUP); + stm32h7_memory_sram_backup_size = LENGTH (SRAM_BACKUP); + + stm32h7_memory_peripheral_begin = ORIGIN (PERIPHERAL); + stm32h7_memory_peripheral_end = ORIGIN (PERIPHERAL) + LENGTH (PERIPHERAL); + stm32h7_memory_peripheral_size = LENGTH (PERIPHERAL); + + stm32h7_memory_nor_begin = ORIGIN (NOR); + stm32h7_memory_nor_end = ORIGIN (NOR) + LENGTH (NOR); + stm32h7_memory_nor_size = LENGTH (NOR); + + stm32h7_memory_sdram_1_begin = ORIGIN (SDRAM_1); + stm32h7_memory_sdram_1_end = ORIGIN (SDRAM_1) + LENGTH (SDRAM_1); + stm32h7_memory_sdram_1_size = LENGTH (SDRAM_1); + + stm32h7_memory_nand_begin = ORIGIN (NAND); + stm32h7_memory_nand_end = ORIGIN (NAND) + LENGTH (NAND); + stm32h7_memory_nand_size = LENGTH (NAND); + + stm32h7_memory_quadspi_begin = ORIGIN (QUADSPI); + stm32h7_memory_quadspi_end = ORIGIN (QUADSPI) + LENGTH (QUADSPI); + stm32h7_memory_quadspi_size = LENGTH (QUADSPI); + + stm32h7_memory_sdram_2_begin = ORIGIN (SDRAM_2); + stm32h7_memory_sdram_2_end = ORIGIN (SDRAM_2) + LENGTH (SDRAM_2); + stm32h7_memory_sdram_2_size = LENGTH (SDRAM_2); +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds.memory +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/linkcmdssdram.yml b/spec/build/bsps/arm/stm32h7/linkcmdssdram.yml new file mode 100644 index 0000000000..5254e5c56f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/linkcmdssdram.yml @@ -0,0 +1,49 @@ +build-type: script +do-build: | + bld.install_as("${BSP_LIBDIR}/linkcmds.sdram", "linkcmds.sdram") +do-configure: | + content = """INCLUDE linkcmds.memory + + REGION_ALIAS ("REGION_START", SDRAM_1); + REGION_ALIAS ("REGION_VECTOR", SDRAM_1); + REGION_ALIAS ("REGION_TEXT", SDRAM_1); + REGION_ALIAS ("REGION_TEXT_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_RODATA", SDRAM_1); + REGION_ALIAS ("REGION_RODATA_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_DATA", SDRAM_1); + REGION_ALIAS ("REGION_DATA_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_FAST_TEXT", ITCM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_FAST_DATA", DTCM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", SDRAM_1); + REGION_ALIAS ("REGION_BSS", SDRAM_1); + REGION_ALIAS ("REGION_WORK", SDRAM_1); + REGION_ALIAS ("REGION_STACK", SRAM_AXI); + REGION_ALIAS ("REGION_NOCACHE", SRAM_1); + REGION_ALIAS ("REGION_NOCACHE_LOAD", SDRAM_1); + + bsp_vector_table_in_start_section = 1; + """ + + if conf.env.STM32H7_ENABLE_MPU_ALIGNMENT: + content += """ + bsp_align_text_and_rodata_end_to_power_of_2 = 1; + """ + + content += """ + INCLUDE linkcmds.armv7m + """ + f = conf.bldnode.make_node( + conf.env.VARIANT + "/linkcmds.sdram" + ) + f.parent.mkdir() + f.write(content) + conf.env.append_value("cfg_files", f.abspath()) +enabled-by: true +links: [] +prepare-build: null +prepare-configure: null +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenmpualign.yml b/spec/build/bsps/arm/stm32h7/optenmpualign.yml new file mode 100644 index 0000000000..4005485940 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenmpualign.yml @@ -0,0 +1,20 @@ +actions: +- get-boolean: null +- env-assign: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_ENABLE_MPU_ALIGNMENT +description: | + Enable the alignment of the size of the combined start and text sections and + the rodata section to meet MPU region alignment requirements. This increases + the memory footprint. It enables a write-protection of the start, text, and + rodata sections. It makes the data sections non-executable. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart4.yml b/spec/build/bsps/arm/stm32h7/optenuart4.yml new file mode 100644 index 0000000000..cd5fd31370 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart4.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART4 +description: | + Enable UART4 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart5.yml b/spec/build/bsps/arm/stm32h7/optenuart5.yml new file mode 100644 index 0000000000..f124d72113 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart5.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART5 +description: | + Enable UART5 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart7.yml b/spec/build/bsps/arm/stm32h7/optenuart7.yml new file mode 100644 index 0000000000..7310cef713 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart7.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART7 +description: | + Enable UART7 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart8.yml b/spec/build/bsps/arm/stm32h7/optenuart8.yml new file mode 100644 index 0000000000..f0407f6510 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart8.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART8 +description: | + Enable UART8 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenuart9.yml b/spec/build/bsps/arm/stm32h7/optenuart9.yml new file mode 100644 index 0000000000..1a3ef49459 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenuart9.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_UART9 +description: | + Enable UART9 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart1.yml b/spec/build/bsps/arm/stm32h7/optenusart1.yml new file mode 100644 index 0000000000..a4f478f753 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart1.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART1 +description: | + Enable USART1 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart10.yml b/spec/build/bsps/arm/stm32h7/optenusart10.yml new file mode 100644 index 0000000000..659d1a96b6 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart10.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART10 +description: | + Enable USART10 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart2.yml b/spec/build/bsps/arm/stm32h7/optenusart2.yml new file mode 100644 index 0000000000..0bbec65278 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart2.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART2 +description: | + Enable USART2 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart3.yml b/spec/build/bsps/arm/stm32h7/optenusart3.yml new file mode 100644 index 0000000000..09e673ff7f --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart3.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART3 +description: | + Enable USART3 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optenusart6.yml b/spec/build/bsps/arm/stm32h7/optenusart6.yml new file mode 100644 index 0000000000..e6524fd40d --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optenusart6.yml @@ -0,0 +1,16 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: true +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_CONSOLE_ENABLE_USART6 +description: | + Enable USART6 device in console driver. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml new file mode 100644 index 0000000000..d0bb033cef --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml @@ -0,0 +1,17 @@ +actions: +- get-string: null +- env-assign: null +build-type: option +default: linkcmds.sdram +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_DEFAULT_LINKCMDS +description: | + The default linker command file. Must be either linkcmds.flash or + linkcmds.sdram. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml b/spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml new file mode 100644 index 0000000000..e7c1a2bdf6 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemdtcmsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_DTCM_SIZE +description: | + Size of the Data Tightly Coupled Memory (DTCM) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemflashsz.yml b/spec/build/bsps/arm/stm32h7/optmemflashsz.yml new file mode 100644 index 0000000000..627543f9a8 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemflashsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x200000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_FLASH_SIZE +description: | + Size of the internal flash in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemitcmsz.yml b/spec/build/bsps/arm/stm32h7/optmemitcmsz.yml new file mode 100644 index 0000000000..610de5f074 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemitcmsz.yml @@ -0,0 +1,18 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0xff00 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_ITCM_SIZE +description: | + Size of the Instruction Tightly Coupled Memory (ITCM) in bytes. The size + must take the NULL pointer protection memory area into account + (STM32H7_MEMORY_NULL_SIZE). +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemnandsz.yml b/spec/build/bsps/arm/stm32h7/optmemnandsz.yml new file mode 100644 index 0000000000..0bfbcc4623 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemnandsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_NAND_SIZE +description: | + Size of the NAND flash in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemnorsz.yml b/spec/build/bsps/arm/stm32h7/optmemnorsz.yml new file mode 100644 index 0000000000..d41d4e9e49 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemnorsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_NOR_SIZE +description: | + Size of the NOR flash or PSRAM in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemnullsz.yml b/spec/build/bsps/arm/stm32h7/optmemnullsz.yml new file mode 100644 index 0000000000..a31169adb1 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemnullsz.yml @@ -0,0 +1,17 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 256 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_NULL_SIZE +description: | + Size of the NULL pointer protection area in bytes. This memory area reduces + the size of the ITCM available to the application (STM32H7_MEMORY_ITCM_SIZE). +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml b/spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml new file mode 100644 index 0000000000..0a1bd610e7 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemperipheralsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_PERIPHERAL_SIZE +description: | + Size of the peripheral memory in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml b/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml new file mode 100644 index 0000000000..11e5f943e0 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_QUADSPI_SIZE +description: | + Size of the QUADSPI memory in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml new file mode 100644 index 0000000000..11228ddb92 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 33554432 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SDRAM_1_SIZE +description: | + Size of the SDRAM 1 in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml new file mode 100644 index 0000000000..5a1ffdcace --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SDRAM_2_SIZE +description: | + Size of the SDRAM 2 in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml new file mode 100644 index 0000000000..01e9dbe1cc --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_1_SIZE +description: | + Size of the SRAM 1 (D2 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml new file mode 100644 index 0000000000..2a4890730a --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x20000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_2_SIZE +description: | + Size of the SRAM 2 (D2 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml new file mode 100644 index 0000000000..eca335fd81 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x8000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_3_SIZE +description: | + Size of the SRAM 3 (D2 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml b/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml new file mode 100644 index 0000000000..cda2e722a4 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x10000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_4_SIZE +description: | + Size of the SRAM 4 (D3 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml b/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml new file mode 100644 index 0000000000..9cb05540b7 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x80000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_AXI_SIZE +description: | + Size of the AXI SRAM (D1 domain) in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml b/spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml new file mode 100644 index 0000000000..f1c5f60bac --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optmemsrambackupsz.yml @@ -0,0 +1,16 @@ +actions: +- get-integer: null +- env-assign: null +build-type: option +default: 0x1000 +default-by-variant: [] +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32H7_MEMORY_SRAM_BACKUP_SIZE +description: | + Size of backup SRAM in bytes. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optprintkinstance.yml b/spec/build/bsps/arm/stm32h7/optprintkinstance.yml new file mode 100644 index 0000000000..6eaf4a2011 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optprintkinstance.yml @@ -0,0 +1,16 @@ +actions: +- get-string: null +- define-unquoted: null +build-type: option +default: stm32h7_usart1_instance +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_PRINTK_INSTANCE +description: | + UART/USART instance used for printk() and getchark(). +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) diff --git a/spec/build/bsps/arm/stm32h7/optvariant.yml b/spec/build/bsps/arm/stm32h7/optvariant.yml new file mode 100644 index 0000000000..586fa2052b --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/optvariant.yml @@ -0,0 +1,29 @@ +actions: +- get-string: null +- script: | + variants = ["STM32H742xx", "STM32H743xx", "STM32H745xx", "STM32H747xx", + "STM32H750xx", "STM32H753xx", "STM32H755xx", "STM32H757xx", "STM32H7A3xx", + "STM32H7A3xxQ", "STM32H7B0xx", "STM32H7B0xxQ", "STM32H7B3xx", "STM32H7B3xxQ"] + if value not in variants: + conf.fatal( + "STM32H7 chip variant '{}' is not one of {}".format( + value, variants + ) + ) + conf.define_cond(value, True) +build-type: option +default: STM32H743xx +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H7_VARIANT +description: | + Select the STM32H7 series chip variant out of STM32H742xx, STM32H743xx, + STM32H745xx, STM32H747xx, STM32H750xx, STM32H753xx, STM32H755xx, STM32H757xx, + STM32H7A3xx, STM32H7A3xxQ, STM32H7B0xx, STM32H7B0xxQ, STM32H7B3xx, and + STM32H7B3xxQ. +type: build +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -- cgit v1.2.3