From 5cc075712e628191477d0c9d074e15b6a7c1e1e3 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 1 Jul 2022 15:21:47 +0200 Subject: irq/arm-gicv3.h: Customize CPU Interface init Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers. --- spec/build/bsps/arm/fvp/grp.yml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'spec/build/bsps/arm/fvp/grp.yml') diff --git a/spec/build/bsps/arm/fvp/grp.yml b/spec/build/bsps/arm/fvp/grp.yml index 8de7d10917..eecbd9efd9 100644 --- a/spec/build/bsps/arm/fvp/grp.yml +++ b/spec/build/bsps/arm/fvp/grp.yml @@ -24,6 +24,8 @@ links: uid: ../../obj - role: build-dependency uid: ../../objirq +- role: build-dependency + uid: ../../dev/irq/objarmgicv3 - role: build-dependency uid: ../../objmem - role: build-dependency -- cgit v1.2.3