From 5fe49a0853e55dce9d81ac3241edb878216b48bd Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Tue, 18 May 2021 14:51:46 -0500 Subject: bsps/aarch64: Add MMU driver to relax alignment Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the toolchain and in the BSPs themselves. In writing this driver, it was found that the synchronous exception handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to avoid thread stack misalignments in RTEMS_DEBUG mode. This is now avoided by exactly preserving thread mode stack and flags and the new implementation is compatible with the draft information provided on the mailing list covering the Exception Management API. --- spec/build/bsps/aarch64/optmmupages.yml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 spec/build/bsps/aarch64/optmmupages.yml (limited to 'spec/build/bsps/aarch64/optmmupages.yml') diff --git a/spec/build/bsps/aarch64/optmmupages.yml b/spec/build/bsps/aarch64/optmmupages.yml new file mode 100644 index 0000000000..d737002f87 --- /dev/null +++ b/spec/build/bsps/aarch64/optmmupages.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0x1 +- assert-le: 0x800 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research (OAR) +default: 0x40 +default-by-variant: [] +description: | + Defines the number of MMU translation table pages to provide. +enabled-by: true +format: '{:#010x}' +links: [] +name: AARCH64_MMU_TRANSLATION_TABLE_PAGES +type: build -- cgit v1.2.3