From 5cc075712e628191477d0c9d074e15b6a7c1e1e3 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 1 Jul 2022 15:21:47 +0200 Subject: irq/arm-gicv3.h: Customize CPU Interface init Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers. --- spec/build/bsps/aarch64/grp.yml | 1 - 1 file changed, 1 deletion(-) (limited to 'spec/build/bsps/aarch64/grp.yml') diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml index ba4ec6c6cf..9428fb9435 100644 --- a/spec/build/bsps/aarch64/grp.yml +++ b/spec/build/bsps/aarch64/grp.yml @@ -22,7 +22,6 @@ install: - bsps/include/dev/irq/arm-gic-regs.h - bsps/include/dev/irq/arm-gic-tm27.h - bsps/include/dev/irq/arm-gic.h - - bsps/include/dev/irq/arm-gicv3.h - destination: ${BSP_LIBDIR} source: - bsps/aarch64/shared/start/linkcmds.base -- cgit v1.2.3