From 5cc075712e628191477d0c9d074e15b6a7c1e1e3 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 1 Jul 2022 15:21:47 +0200 Subject: irq/arm-gicv3.h: Customize CPU Interface init Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers. --- spec/build/bsps/aarch64/a53/obj.yml | 1 - 1 file changed, 1 deletion(-) (limited to 'spec/build/bsps/aarch64/a53/obj.yml') diff --git a/spec/build/bsps/aarch64/a53/obj.yml b/spec/build/bsps/aarch64/a53/obj.yml index 242631fba2..33c0884b85 100644 --- a/spec/build/bsps/aarch64/a53/obj.yml +++ b/spec/build/bsps/aarch64/a53/obj.yml @@ -26,7 +26,6 @@ source: - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/dev/serial/console-termios-init.c - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c -- cgit v1.2.3