From 967eceb2b337fa53049f095483085981519ad305 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Sun, 19 Apr 2009 15:49:20 +0000 Subject: 2009-04-19 Joel Sherrill * cpu_supplement/.cvsignore, cpu_supplement/Makefile.am, cpu_supplement/cpu_supplement.texi: Add shell for Atmel AVR chapter. * cpu_supplement/avr.t: New file. --- doc/ChangeLog | 6 ++ doc/cpu_supplement/.cvsignore | 1 + doc/cpu_supplement/Makefile.am | 7 +- doc/cpu_supplement/avr.t | 128 +++++++++++++++++++++++++++++++++ doc/cpu_supplement/cpu_supplement.texi | 4 +- 5 files changed, 144 insertions(+), 2 deletions(-) create mode 100644 doc/cpu_supplement/avr.t (limited to 'doc') diff --git a/doc/ChangeLog b/doc/ChangeLog index 7f1d8722cb..753ac74cc5 100644 --- a/doc/ChangeLog +++ b/doc/ChangeLog @@ -1,3 +1,9 @@ +2009-04-19 Joel Sherrill + + * cpu_supplement/.cvsignore, cpu_supplement/Makefile.am, + cpu_supplement/cpu_supplement.texi: Add shell for Atmel AVR chapter. + * cpu_supplement/avr.t: New file. + 2009-03-30 Sebastian Huber * shell/confinit.t: New argument sequence for rtems_shell_init(). diff --git a/doc/cpu_supplement/.cvsignore b/doc/cpu_supplement/.cvsignore index 119eeab730..a10e10a70e 100644 --- a/doc/cpu_supplement/.cvsignore +++ b/doc/cpu_supplement/.cvsignore @@ -1,4 +1,5 @@ arm.texi +avr.texi bfin.texi cpu_supplement cpu_supplement-? diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am index 1de6ce65f0..3539e78464 100644 --- a/doc/cpu_supplement/Makefile.am +++ b/doc/cpu_supplement/Makefile.am @@ -21,7 +21,7 @@ TEXI2WWW_ARGS=\ -header rtems_header.html \ -footer rtems_footer.html \ -icons ../images -GENERATED_FILES = general.texi arm.texi bfin.texi i386.texi lm32.texi \ +GENERATED_FILES = general.texi arm.texi avr.texi bfin.texi i386.texi lm32.texi \ m68k.texi mips.texi powerpc.texi sh.texi sparc.texi tic4x.texi COMMON_FILES += $(top_srcdir)/common/cpright.texi @@ -45,6 +45,11 @@ arm.texi: arm.t -u "Top" \ -n "" < $< > $@ +avr.texi: avr.t + $(BMENU2) -p "" \ + -u "Top" \ + -n "" < $< > $@ + bfin.texi: bfin.t $(BMENU2) -p "" \ -u "Top" \ diff --git a/doc/cpu_supplement/avr.t b/doc/cpu_supplement/avr.t new file mode 100644 index 0000000000..ed65441304 --- /dev/null +++ b/doc/cpu_supplement/avr.t @@ -0,0 +1,128 @@ +@c +@c COPYRIGHT (c) 1988-2009. +@c On-Line Applications Research Corporation (OAR). +@c All rights reserved. +@c +@c $Id$ +@c + +@ifinfo +@end ifinfo +@chapter Atmel AVR Specific Information + +This chapter discusses the AVR architecture dependencies in this +port of RTEMS. + +@subheading Architecture Documents + +For information on the AVR architecture, refer to the following +documents available from Atmel. + +TBD + +@itemize @bullet + +@item See other CPUs for documentation reference formatting examples. + +@end itemize + + +@section CPU Model Dependent Features + +CPUs of the AVR 53X only differ in the peripherals and thus in the +device drivers. This port does not yet support the 56X dual core variants. + +@subsection Count Leading Zeroes Instruction + +The AVR CPU has the XXX instruction which could be used to speed +up the find first bit operation. The use of this instruction should +significantly speed up the scheduling associated with a thread blocking. + +@section Calling Conventions + +@subsection Processor Background + +The AVR architecture supports a simple call and return mechanism. +A subroutine is invoked via the call (@code{call}) instruction. +This instruction saves the return address in the @code{RETS} register +and transfers the execution to the given address. + +It is the called funcions responsability to use the link instruction +to reserve space on the stack for the local variables. Returning from +a subroutine is done by using the RTS (@code{RTS}) instruction which +loads the PC with the adress stored in RETS. + +It is is important to note that the @code{call} instruction does not +automatically save or restore any registers. It is the responsibility +of the high-level language compiler to define the register preservation +and usage convention. + +@subsection Register Usage + +A called function may clobber all registers, except RETS, R4-R7, P3-P5, +FP and SP. It may also modify the first 12 bytes in the caller’s stack +frame which is used as an argument area for the first three arguments +(which are passed in R0...R3 but may be placed on the stack by the +called function). + +@subsection Parameter Passing + +RTEMS assumes that the AVR GCC calling convention is followed. +The first three parameters are stored in registers R0, R1, and R2. +All other parameters are put pushed on the stack. The result is returned +through register R0. + +@section Memory Model + +The AVR family architecutre support a single unified 4 GB byte +address space using 32-bit addresses. It maps all resources like internal +and external memory and IO registers into separate sections of this +common address space. + +The AVR architcture supports some form of memory +protection via its Memory Management Unit. Since the +AVR port runs in supervisior mode this memory +protection mechanisms are not used. + +@section Interrupt Processing + +Discussed in this chapter are the AVR's interrupt response and +control mechanisms as they pertain to RTEMS. + +@subsection Vectoring of an Interrupt Handler + +TBD + +@subsection Disabling of Interrupts by RTEMS + +During interrupt disable critical sections, RTEMS disables interrupts to +level N (N) before the execution of this section and restores them +to the previous level upon completion of the section. RTEMS uses the +instructions CLI and STI to enable and disable Interrupts. Emulation, +Reset, NMI and Exception Interrupts are never disabled. + +@subsection Interrupt Stack + +The AVR Architecture works with two different kind of stacks, +User and Supervisor Stack. Since RTEMS and its Application run +in supervisor mode, all interrupts will use the interrupted +tasks stack for execution. + +@section Default Fatal Error Processing + +The default fatal error handler for the AVR performs the following +actions: + +@itemize @bullet +@item disables processor interrupts, +@item places the error code in @b{r0}, and +@item executes an infinite loop (@code{while(0);} to +simulate a halt processor instruction. +@end itemize + +@section Board Support Packages + + +@subsection System Reset + +TBD diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi index fc18653ca7..bdc630d61b 100644 --- a/doc/cpu_supplement/cpu_supplement.texi +++ b/doc/cpu_supplement/cpu_supplement.texi @@ -8,7 +8,7 @@ @c %**end of header @c -@c COPYRIGHT (c) 1988-2008. +@c COPYRIGHT (c) 1988-2009. @c On-Line Applications Research Corporation (OAR). @c All rights reserved. @c @@ -61,6 +61,7 @@ @include preface.texi @include general.texi @include arm.texi +@include avr.texi @include bfin.texi @include i386.texi @include lm32.texi @@ -80,6 +81,7 @@ This is the online version of the RTEMS CPU Architecture Supplement. * Preface:: * Port Specific Information:: * ARM Specific Information:: +* Atmel AVR Specific Information:: * Blackfin Specific Information:: * Intel/AMD x86 Specific Information:: * Lattice Mico32 Specific Information:: -- cgit v1.2.3