From 2d7ae960bbdbc82f795814ee6c600e93200ddf4d Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 11 Jun 2012 13:37:29 -0500 Subject: v850 port: Initial addition with BSP for simulator in GDB Port + v850 does not have appear to have any optimized bit scan instructions + v850 does have single instructions for wap u16 and u32 + Code path optimization preferences set + Add BSP variants for each GCC CPU model flag and a README - v850e1 variant does not work (fails during BSP initialization) BSP for GDB v850 Simulator + linkcmds matches defaults in GDB simulator with RTEMS mods + crt1.c added from v850 newlib port for __main() + BSP exits cleanly + printk and console I/O work + uses clock tick from IDLE task + Tests not requiring real clock ISR work Documentation + CPU Supplment chapter for v850 added --- doc/cpu_supplement/Makefile.am | 9 +++- doc/cpu_supplement/v850.t | 104 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 doc/cpu_supplement/v850.t (limited to 'doc') diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am index 970ea7a6f9..8d117cfcd0 100644 --- a/doc/cpu_supplement/Makefile.am +++ b/doc/cpu_supplement/Makefile.am @@ -1,5 +1,5 @@ # -# COPYRIGHT (c) 1988-2002. +# COPYRIGHT (c) 1988-2012. # On-Line Applications Research Corporation (OAR). # All rights reserved. @@ -11,7 +11,7 @@ include $(top_srcdir)/main.am REPLACE2 = $(PERL) $(top_srcdir)/tools/word-replace2 GENERATED_FILES = general.texi arm.texi avr.texi bfin.texi i386.texi lm32.texi \ - m68k.texi mips.texi powerpc.texi sh.texi sparc.texi sparc64.texi + m68k.texi mips.texi powerpc.texi sh.texi sparc.texi sparc64.texi v850.texi COMMON_FILES += $(top_srcdir)/common/cpright.texi @@ -84,6 +84,11 @@ sparc64.texi: sparc64.t -u "Top" \ -n "" < $< > $@ +v850.texi: v850.t + $(BMENU2) -p "" \ + -u "Top" \ + -n "" < $< > $@ + CLEANFILES += cpu_supplement.info CLEANFILES += cpu_supplement.info-1 CLEANFILES += cpu_supplement.info-2 diff --git a/doc/cpu_supplement/v850.t b/doc/cpu_supplement/v850.t new file mode 100644 index 0000000000..072e10e4e0 --- /dev/null +++ b/doc/cpu_supplement/v850.t @@ -0,0 +1,104 @@ +@c +@c COPYRIGHT (c) 1988-2002. +@c On-Line Applications Research Corporation (OAR). +@c All rights reserved. + +@ifinfo +@end ifinfo +@chapter V850 Specific Information + +This chapter discusses the +@uref{http://en.wikipedia.org/wiki/V850,V850 architecture} +dependencies in this port of RTEMS. The V850 was originally manufactured +by NEC but is now part of the Renesas Electronics product line. + +@subheading Architecture Documents + +For information on the V850 architecture refer to the +@uref{http://am.renesas.com/products/mpumcu/v850/index.jsp,Renesas v850 product page}. + +@section CPU Model Dependent Features + +This section presents the set of features which vary across V850 implementations and are of importance to RTEMS. The set of CPU model feature macros are defined in the file @file{cpukit/score/cpu/v850/rtems/score/v850.h} based upon the particular CPU +model flags specified on the compilation command line. + +@subsection CPU Model Name + +The macro @code{CPU_MODEL_NAME} is a string which designates +the architectural level of this CPU model. See in +@file{cpukit/score/cpu/v850/rtems/score/v850.h} for the values. + +@subsection Count Leading Zeroes Instruction + +The V850v5 and later has the count leading zeroes @code{clz} instruction which +could be used to speed up the find first bit operation. The use of this +instruction should significantly speed up the scheduling associated with a +thread blocking. This is currently not used. + +@subsection Floating Point Unit + +A floating point unit is currently not supported. + +@section Calling Conventions + +Please refer to the +@uref{http://www.filibeto.org/unix/tru64/lib/ossc/doc/cygnus_doc-99r1/html/6_embed/embV850.html, +Procedure Call Standard for the V850 Architecture} or the GCC source +code for detailed information on the calling conventions. + +@subsection Register Usage + +Fixed registers are never available for register allocation in the +compiler. By default the following registers are fixed in GCC: + +@itemize @bullet +@item r0 (zero) +@item r3 (sp) +@item r4 (gp) +@item r30 (ep) +@end itemize + +@c r1 is mentioned as special purpose but I do not see a purpose + +Caller saved registers can be used by the compiler to hold values that +do not live across function calls. The caller saved registers are r2, +r5 through r19, and r31. + +Callee saved registers retain their value across function calls. The +callee saved registers are r20 through r29. + +r6 through r9 are parameter registers while r10 and r11 are function return registers. r31 is the return pointer. + +r29 is used as the frame pointer in some functions. + +@section Memory Model + +A flat 32-bit memory model is supported. + +@section Interrupt Processing + +The V850 architecture has ... + +@subsection Interrupt Levels + +The RTEMS interrupt level mapping scheme for the V850 is very simple. If +the requested interrupt level is 1, then interrupts are disabled in the +PSW register using the @code{di} instruction. If the requested interrupt +level is 0, then interrupts are enabled in the PSW register using the +@code{ei} instruction or restoring the previous value of the PSW register. + +@subsection Interrupt Stack + +The board support package must initialize the interrupt stack. The memory for +the stacks is usually reserved in the linker script. + +@section Default Fatal Error Processing + +The default fatal error handler for this architecture performs the +following actions: + +@itemize @bullet +@item disables operating system supported interrupts (IRQ), +@item places the error code in @code{r10}, and +@item executes a halt processor instruction. +@end itemize -- cgit v1.2.3