From 03889c1a1e45d591d8d2568cff400de002777612 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 19 Oct 1998 21:46:32 +0000 Subject: All of the Supplemental manuals are now generated as automatically as possible. --- doc/supplements/i386/Makefile | 26 ++-------- doc/supplements/m68k/Makefile | 97 ++++++++++++++++++++++++++---------- doc/supplements/m68k/bsp.t | 21 +------- doc/supplements/m68k/callconv.t | 33 +----------- doc/supplements/m68k/cpumodel.t | 41 +-------------- doc/supplements/m68k/cputable.t | 19 +------ doc/supplements/m68k/fatalerr.t | 15 ------ doc/supplements/m68k/intr_NOTIMES.t | 41 +-------------- doc/supplements/m68k/m68k.texi | 2 +- doc/supplements/m68k/memmodel.t | 15 ------ doc/supplements/m68k/timeMVME136.t | 44 +--------------- doc/supplements/powerpc/Makefile | 6 +-- doc/supplements/sparc/Makefile | 95 +++++++++++++++++++++++------------ doc/supplements/sparc/bsp.t | 21 +------- doc/supplements/sparc/callconv.t | 57 +-------------------- doc/supplements/sparc/cpumodel.t | 45 +---------------- doc/supplements/sparc/cputable.t | 17 +------ doc/supplements/sparc/fatalerr.t | 15 ------ doc/supplements/sparc/intr_NOTIMES.t | 37 +------------- doc/supplements/sparc/memmodel.t | 15 ------ doc/supplements/sparc/sparc.texi | 2 +- doc/supplements/template/Makefile | 6 +-- 22 files changed, 159 insertions(+), 511 deletions(-) (limited to 'doc/supplements') diff --git a/doc/supplements/i386/Makefile b/doc/supplements/i386/Makefile index 440f36d8c8..81f458da6c 100644 --- a/doc/supplements/i386/Makefile +++ b/doc/supplements/i386/Makefile @@ -15,6 +15,8 @@ REPLACE=../../tools/word-replace all: html info ps +COMMON_FILES=../../common/cpright.texi ../../common/setup.texi + GENERATED_FILES=\ cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \ bsp.texi cputable.texi timing.texi wksheets.texi timeFORCE386.texi @@ -27,8 +29,6 @@ FILES= $(PROJECT).texi \ dirs: $(make-dirs) -COMMON_FILES=../../common/cpright.texi ../../common/setup.texi - info: dirs c_i386 cp c_$(PROJECT) $(INFO_INSTALL) #cp c_$(PROJECT) c_$(PROJECT)-* $(INFO_INSTALL) @@ -46,8 +46,6 @@ $(PROJECT).ps: $(PROJECT).dvi $(PROJECT).dvi: $(FILES) $(TEXI2DVI) $(PROJECT).texi -replace: timedata.texi - # # Chapters which get automatic processing # @@ -151,20 +149,6 @@ timeFORCE386.texi: timeFORCE386_.t Makefile -n "Command and Variable Index" timeFORCE386_.t mv timeFORCE386_.texi timeFORCE386.texi -## Timing Chapter -# -#timetbl.t: ../../common/timetbl.t -# sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \ -# <../../common/timetbl.t >timetbl.t -# -#timetbl.texi: timetbl.t FORCE386_TIMES -# ${REPLACE} -p FORCE386_TIMES timetbl.t -# mv timetbl.t.fixed timetbl.texi -# -#timedata.texi: timedata.t FORCE386_TIMES -# ${REPLACE} -p FORCE386_TIMES timedata.t -# mv timedata.t.fixed timedata.texi - html: dirs $(FILES) -mkdir -p $(WWW_INSTALL)/c_i386 $(TEXI2WWW) $(TEXI2WWW_ARGS) -dir $(WWW_INSTALL)/c_$(PROJECT) \ @@ -175,8 +159,8 @@ clean: rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE) rm -f $(PROJECT) $(PROJECT)-* rm -f c_i386 c_i386-* - rm -f timedata.texi timetbl.texi intr.texi $(GENERATED_FILES) - rm -f timetbl.t wksheets.t wksheets_NOTIMES.t timing.t intr.t - rm -f timeFORCE386_.t + rm -f intr.t $(GENERATED_FILES) + rm -f wksheets.t wksheets_NOTIMES.t timing.t intr.t + rm -f timeFORCE386_.t timeFORCE386_.texi rm -f *.fixed _* diff --git a/doc/supplements/m68k/Makefile b/doc/supplements/m68k/Makefile index 2995d519b5..3fbbfa7ed6 100644 --- a/doc/supplements/m68k/Makefile +++ b/doc/supplements/m68k/Makefile @@ -20,12 +20,12 @@ dirs: COMMON_FILES=../../common/cpright.texi ../../common/setup.texi -GENERATED_FILES= \ - timing.texi wksheets.texi +GENERATED_FILES=\ + cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \ + bsp.texi cputable.texi timing.texi wksheets.texi timeMVME136.texi FILES= $(PROJECT).texi \ - bsp.texi callconv.texi cpumodel.texi cputable.texi fatalerr.texi \ - intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \ + preface.texi \ $(GENERATED_FILES) info: dirs c_m68k @@ -44,27 +44,61 @@ $(PROJECT).ps: $(PROJECT).dvi $(PROJECT).dvi: $(FILES) $(TEXI2DVI) $(PROJECT).texi -replace: timedata.texi - # # Chapters which get automatic processing # -# CPU Model -# Calling Conventions -# Memory Model +cpumodel.texi: cpumodel.t Makefile + $(BMENU) -p "Preface" \ + -u "Top" \ + -n "Calling Conventions" ${*}.t + +callconv.texi: callconv.t Makefile + $(BMENU) -p "CPU Model Dependent Features Extend Byte to Long Instruction" \ + -u "Top" \ + -n "Memory Model" ${*}.t + +memmodel.texi: memmodel.t Makefile + $(BMENU) -p "Calling Conventions User-Provided Routines" \ + -u "Top" \ + -n "Interrupt Processing" ${*}.t + + +## Interrupt Chapter: +## 1. Replace Times and Sizes +## 2. Build Node Structure +# +#intr.texi: intr.t MVME136_TIMES +# ${REPLACE} -p MVME136_TIMES intr.t +# mv intr.t.fixed intr.texi # Interrupt Chapter: # 1. Replace Times and Sizes # 2. Build Node Structure +intr.t: intr_NOTIMES.t MVME136_TIMES + ${REPLACE} -p MVME136_TIMES intr_NOTIMES.t + mv intr_NOTIMES.t.fixed intr.t -intr.texi: intr.t MVME136_TIMES - ${REPLACE} -p MVME136_TIMES intr.t - mv intr.t.fixed intr.texi +intr.texi: intr.t Makefile + $(BMENU) -p "Memory Model Flat Memory Model" \ + -u "Top" \ + -n "Default Fatal Error Processing" ${*}.t + +fatalerr.texi: fatalerr.t Makefile + $(BMENU) -p "Interrupt Processing Interrupt Stack" \ + -u "Top" \ + -n "Board Support Packages" ${*}.t + +bsp.texi: bsp.t Makefile + $(BMENU) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \ + -u "Top" \ + -n "Processor Dependent Information Table" ${*}.t + +cputable.texi: cputable.t Makefile + $(BMENU) -p "Board Support Packages Processor Initialization" \ + -u "Top" \ + -n "Memory Requirements" ${*}.t -# Fatal Error -# BSP -# CPU Table # Worksheets Chapter: # 1. Obtain the Shared File @@ -95,17 +129,25 @@ timing.texi: timing.t Makefile -u "Top" \ -n "MVME136 Timing Data" ${*}.t -timetbl.t: ../../common/timetbl.t - sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \ - <../../common/timetbl.t >timetbl.t - -timetbl.texi: timetbl.t MVME136_TIMES - ${REPLACE} -p MVME136_TIMES timetbl.t - mv timetbl.t.fixed timetbl.texi +# Timing Data for BSP Chapter: +# 1. Copy the Shared File +# 2. Replace Times and Sizes +# 3. Build Node Structure -timedata.texi: timedata.t MVME136_TIMES - ${REPLACE} -p MVME136_TIMES timedata.t - mv timedata.t.fixed timedata.texi +timeMVME136_.t: ../../common/timetbl.t timeMVME136.t + cat timeMVME136.t ../../common/timetbl.t >timeMVME136_.t + @echo >>timeMVME136_.t + @echo "@tex" >>timeMVME136_.t + @echo "\\global\\advance \\smallskipamount by 4pt" >>timeMVME136_.t + @echo "@end tex" >>timeMVME136_.t + ${REPLACE} -p MVME136_TIMES timeMVME136_.t + mv timeMVME136_.t.fixed timeMVME136_.t + +timeMVME136.texi: timeMVME136_.t Makefile + $(BMENU) -p "Timing Specification Terminology" \ + -u "Top" \ + -n "Command and Variable Index" timeMVME136_.t + mv timeMVME136_.texi timeMVME136.texi html: dirs $(FILES) -mkdir -p $(WWW_INSTALL)/c_m68k @@ -117,6 +159,7 @@ clean: rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE) rm -f $(PROJECT) $(PROJECT)-* rm -f c_m68k c_m68k-* - rm -f timedata.texi timetbl.texi intr.texi $(GENERATED_FILES) - rm -f timetbl.t wksheets.t wksheets_NOTIMES.t + rm -f intr.t $(GENERATED_FILES) + rm -f wksheets.t wksheets_NOTIMES.t + rm -f timeMVME136_.t timeMVME136_.texi rm -f *.fixed _* timing.t diff --git a/doc/supplements/m68k/bsp.t b/doc/supplements/m68k/bsp.t index cc056b2c06..7782fe2e3d 100644 --- a/doc/supplements/m68k/bsp.t +++ b/doc/supplements/m68k/bsp.t @@ -6,21 +6,8 @@ @c $Id$ @c -@ifinfo -@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top -@end ifinfo @chapter Board Support Packages -@ifinfo -@menu -* Board Support Packages Introduction:: -* Board Support Packages System Reset:: -* Board Support Packages Processor Initialization:: -@end menu -@end ifinfo - -@ifinfo -@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages -@end ifinfo + @section Introduction An RTEMS Board Support Package (BSP) must be designed @@ -30,9 +17,6 @@ issues. For more information on developing a BSP, refer to the chapter titled Board Support Packages in the RTEMS Applications User's Guide. -@ifinfo -@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages -@end ifinfo @section System Reset An RTEMS based application is initiated or @@ -66,9 +50,6 @@ vector 1 (bytes 4-7) of the EVT. the PC. @end itemize -@ifinfo -@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages -@end ifinfo @section Processor Initialization The address of the application's initialization code diff --git a/doc/supplements/m68k/callconv.t b/doc/supplements/m68k/callconv.t index 014222a9fc..1ebdf7592e 100644 --- a/doc/supplements/m68k/callconv.t +++ b/doc/supplements/m68k/callconv.t @@ -6,24 +6,8 @@ @c $Id$ @c -@ifinfo -@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Extend Byte to Long Instruction, Top -@end ifinfo @chapter Calling Conventions -@ifinfo -@menu -* Calling Conventions Introduction:: -* Calling Conventions Processor Background:: -* Calling Conventions Calling Mechanism:: -* Calling Conventions Register Usage:: -* Calling Conventions Parameter Passing:: -* Calling Conventions User-Provided Routines:: -@end menu -@end ifinfo - -@ifinfo -@node Calling Conventions Introduction, Calling Conventions Processor Background, Calling Conventions, Calling Conventions -@end ifinfo + @section Introduction Each high-level language compiler generates @@ -44,9 +28,6 @@ target processor are the same, different compilers may use different calling conventions. As a result, calling conventions are both processor and compiler dependent. -@ifinfo -@node Calling Conventions Processor Background, Calling Conventions Calling Mechanism, Calling Conventions Introduction, Calling Conventions -@end ifinfo @section Processor Background The MC68xxx architecture supports a simple yet @@ -61,18 +42,12 @@ automatically save or restore any registers. It is the responsibility of the high-level language compiler to define the register preservation and usage convention. -@ifinfo -@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Processor Background, Calling Conventions -@end ifinfo @section Calling Mechanism All RTEMS directives are invoked using either a bsr or jsr instruction and return to the user application via the rts instruction. -@ifinfo -@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions -@end ifinfo @section Register Usage As discussed above, the bsr and jsr instructions do @@ -82,9 +57,6 @@ not preserved by RTEMS directives therefore, the contents of these registers should not be assumed upon return from any RTEMS directive. -@ifinfo -@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions -@end ifinfo @section Parameter Passing RTEMS assumes that arguments are placed on the @@ -112,9 +84,6 @@ from the stack after control is returned to the caller. This removal is typically accomplished by adding the size of the argument list in bytes to the current stack pointer. -@ifinfo -@node Calling Conventions User-Provided Routines, Memory Model, Calling Conventions Parameter Passing, Calling Conventions -@end ifinfo @section User-Provided Routines All user-provided routines invoked by RTEMS, such as diff --git a/doc/supplements/m68k/cpumodel.t b/doc/supplements/m68k/cpumodel.t index 0c693ad8c3..d9bf601e1f 100644 --- a/doc/supplements/m68k/cpumodel.t +++ b/doc/supplements/m68k/cpumodel.t @@ -6,26 +6,8 @@ @c $Id$ @c -@ifinfo -@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top -@end ifinfo @chapter CPU Model Dependent Features -@ifinfo -@menu -* CPU Model Dependent Features Introduction:: -* CPU Model Dependent Features CPU Model Name:: -* CPU Model Dependent Features Floating Point Unit:: -* CPU Model Dependent Features BFFFO Instruction:: -* CPU Model Dependent Features Vector Base Register:: -* CPU Model Dependent Features Separate Stacks:: -* CPU Model Dependent Features Pre-Indexing Address Mode:: -* CPU Model Dependent Features Extend Byte to Long Instruction:: -@end menu -@end ifinfo - -@ifinfo -@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features, CPU Model Dependent Features -@end ifinfo + @section Introduction Microprocessors are generally classified into @@ -67,18 +49,12 @@ The set of CPU model feature macros are defined in the file c/src/exec/score/cpu/m68k/m68k.h based upon the particular CPU model defined on the compilation command line. -@ifinfo -@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Introduction, CPU Model Dependent Features -@end ifinfo @section CPU Model Name The macro CPU_MODEL_NAME is a string which designates the name of this CPU model. For example, for the MC68020 processor, this macro is set to the string "mc68020". -@ifinfo -@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features -@end ifinfo @section Floating Point Unit The macro M68K_HAS_FPU is set to 1 to indicate that @@ -87,42 +63,27 @@ otherwise. It does not matter whether the hardware floating point support is incorporated on-chip or is an external coprocessor. -@ifinfo -@node CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features -@end ifinfo @section BFFFO Instruction The macro M68K_HAS_BFFFO is set to 1 to indicate that this CPU model has the bfffo instruction. -@ifinfo -@node CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features -@end ifinfo @section Vector Base Register The macro M68K_HAS_VBR is set to 1 to indicate that this CPU model has a vector base register (vbr). -@ifinfo -@node CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features -@end ifinfo @section Separate Stacks The macro M68K_HAS_SEPARATE_STACKS is set to 1 to indicate that this CPU model has separate interrupt, user, and supervisor mode stacks. -@ifinfo -@node CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features Extend Byte to Long Instruction, CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features -@end ifinfo @section Pre-Indexing Address Mode The macro M68K_HAS_PREINDEXING is set to 1 to indicate that this CPU model has the pre-indexing address mode. -@ifinfo -@node CPU Model Dependent Features Extend Byte to Long Instruction, Calling Conventions, CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features -@end ifinfo @section Extend Byte to Long Instruction The macro M68K_HAS_EXTB_L is set to 1 to indicate that this CPU model diff --git a/doc/supplements/m68k/cputable.t b/doc/supplements/m68k/cputable.t index b0d011e2c5..7a7273ea8e 100644 --- a/doc/supplements/m68k/cputable.t +++ b/doc/supplements/m68k/cputable.t @@ -6,20 +6,8 @@ @c $Id$ @c -@ifinfo -@node Processor Dependent Information Table, Processor Dependent Information Table Introduction, Board Support Packages Processor Initialization, Top -@end ifinfo -@chapter Processor Dependent Information Table -@ifinfo -@menu -* Processor Dependent Information Table Introduction:: -* Processor Dependent Information Table CPU Dependent Information Table:: -@end menu -@end ifinfo - -@ifinfo -@node Processor Dependent Information Table Introduction, Processor Dependent Information Table CPU Dependent Information Table, Processor Dependent Information Table, Processor Dependent Information Table -@end ifinfo +@chapter Processor Dependent Information Table + @section Introduction Any highly processor dependent information required @@ -28,9 +16,6 @@ Dependent Information Table. This table is not required for all processors supported by RTEMS. This chapter describes the contents, if any, for a particular processor type. -@ifinfo -@node Processor Dependent Information Table CPU Dependent Information Table, Memory Requirements, Processor Dependent Information Table Introduction, Processor Dependent Information Table -@end ifinfo @section CPU Dependent Information Table The MC68xxx version of the RTEMS CPU Dependent diff --git a/doc/supplements/m68k/fatalerr.t b/doc/supplements/m68k/fatalerr.t index c2390f50bd..4b4c8d0b8d 100644 --- a/doc/supplements/m68k/fatalerr.t +++ b/doc/supplements/m68k/fatalerr.t @@ -6,20 +6,8 @@ @c $Id$ @c -@ifinfo -@node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Interrupt Stack, Top -@end ifinfo @chapter Default Fatal Error Processing -@ifinfo -@menu -* Default Fatal Error Processing Introduction:: -* Default Fatal Error Processing Default Fatal Error Handler Operations:: -@end menu -@end ifinfo -@ifinfo -@node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing -@end ifinfo @section Introduction Upon detection of a fatal error by either the @@ -32,9 +20,6 @@ default fatal error handler is then invoked. This chapter describes the precise operations of the default fatal error handler. -@ifinfo -@node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing -@end ifinfo @section Default Fatal Error Handler Operations The default fatal error handler which is invoked by diff --git a/doc/supplements/m68k/intr_NOTIMES.t b/doc/supplements/m68k/intr_NOTIMES.t index ea28bdbc84..89c5225625 100644 --- a/doc/supplements/m68k/intr_NOTIMES.t +++ b/doc/supplements/m68k/intr_NOTIMES.t @@ -8,23 +8,8 @@ @c $Id$ @c -@ifinfo -@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top -@end ifinfo @chapter Interrupt Processing -@ifinfo -@menu -* Interrupt Processing Introduction:: -* Interrupt Processing Vectoring of an Interrupt Handler:: -* Interrupt Processing Interrupt Levels:: -* Interrupt Processing Disabling of Interrupts by RTEMS:: -* Interrupt Processing Interrupt Stack:: -@end menu -@end ifinfo - -@ifinfo -@node Interrupt Processing Introduction, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing, Interrupt Processing -@end ifinfo + @section Introduction Different types of processors respond to the @@ -42,24 +27,12 @@ unique architecture. Discussed in this chapter are the MC68xxx's interrupt response and control mechanisms as they pertain to RTEMS. -@ifinfo -@node Interrupt Processing Vectoring of an Interrupt Handler, Models Without Separate Interrupt Stacks, Interrupt Processing Introduction, Interrupt Processing -@end ifinfo @section Vectoring of an Interrupt Handler -@ifinfo -@menu -* Models Without Separate Interrupt Stacks:: -* Models With Separate Interrupt Stacks:: -@end menu -@end ifinfo Depending on whether or not the particular CPU supports a separate interrupt stack, the MC68xxx family has two different interrupt handling models. -@ifinfo -@node Models Without Separate Interrupt Stacks, Models With Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing Vectoring of an Interrupt Handler -@end ifinfo @subsection Models Without Separate Interrupt Stacks Upon receipt of an interrupt the MC68xxx family @@ -70,9 +43,6 @@ the following actions: @item To Be Written @end itemize -@ifinfo -@node Models With Separate Interrupt Stacks, Interrupt Processing Interrupt Levels, Models Without Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler -@end ifinfo @subsection Models With Separate Interrupt Stacks Upon receipt of an interrupt the MC68xxx family @@ -173,9 +143,6 @@ MC68xxx CPU models with separate interrupt stacks: @end html @end ifset -@ifinfo -@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Models With Separate Interrupt Stacks, Interrupt Processing -@end ifinfo @section Interrupt Levels Eight levels (0-7) of interrupt priorities are @@ -191,9 +158,6 @@ through 7 directly correspond to MC68xxx interrupt levels. All other RTEMS interrupt levels are undefined and their behavior is unpredictable. -@ifinfo -@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing -@end ifinfo @section Disabling of Interrupts by RTEMS During the execution of directive calls, critical @@ -217,9 +181,6 @@ occur due to the inability of RTEMS to protect its critical sections. However, ISRs that make no system calls may safely execute as non-maskable interrupts. -@ifinfo -@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing -@end ifinfo @section Interrupt Stack RTEMS allocates the interrupt stack from the diff --git a/doc/supplements/m68k/m68k.texi b/doc/supplements/m68k/m68k.texi index 5137005216..edd541331d 100644 --- a/doc/supplements/m68k/m68k.texi +++ b/doc/supplements/m68k/m68k.texi @@ -73,7 +73,7 @@ END-INFO-DIR-ENTRY @include cputable.texi @include wksheets.texi @include timing.texi -@include timedata.texi +@include timeMVME136.texi @ifinfo @node Top, Preface, (dir), (dir) @top c_m68k diff --git a/doc/supplements/m68k/memmodel.t b/doc/supplements/m68k/memmodel.t index e8c7c460dd..6054fd54a9 100644 --- a/doc/supplements/m68k/memmodel.t +++ b/doc/supplements/m68k/memmodel.t @@ -6,20 +6,8 @@ @c $Id$ @c -@ifinfo -@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top -@end ifinfo @chapter Memory Model -@ifinfo -@menu -* Memory Model Introduction:: -* Memory Model Flat Memory Model:: -@end menu -@end ifinfo -@ifinfo -@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model -@end ifinfo @section Introduction A processor may support any combination of memory @@ -31,9 +19,6 @@ memory of any kind. The appropriate memory model for RTEMS provided by the targeted processor and related characteristics of that model are described in this chapter. -@ifinfo -@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model -@end ifinfo @section Flat Memory Model The MC68xxx family supports a flat 32-bit address diff --git a/doc/supplements/m68k/timeMVME136.t b/doc/supplements/m68k/timeMVME136.t index 74b64bd088..7f126b4606 100644 --- a/doc/supplements/m68k/timeMVME136.t +++ b/doc/supplements/m68k/timeMVME136.t @@ -11,36 +11,8 @@ \global\advance \smallskipamount by -4pt @end tex -@ifinfo -@node MVME136 Timing Data, MVME136 Timing Data Introduction, Timing Specification Terminology, Top -@end ifinfo @chapter MVME136 Timing Data -@ifinfo -@menu -* MVME136 Timing Data Introduction:: -* MVME136 Timing Data Hardware Platform:: -* MVME136 Timing Data Interrupt Latency:: -* MVME136 Timing Data Context Switch:: -* MVME136 Timing Data Directive Times:: -* MVME136 Timing Data Task Manager:: -* MVME136 Timing Data Interrupt Manager:: -* MVME136 Timing Data Clock Manager:: -* MVME136 Timing Data Timer Manager:: -* MVME136 Timing Data Semaphore Manager:: -* MVME136 Timing Data Message Manager:: -* MVME136 Timing Data Event Manager:: -* MVME136 Timing Data Signal Manager:: -* MVME136 Timing Data Partition Manager:: -* MVME136 Timing Data Region Manager:: -* MVME136 Timing Data Dual-Ported Memory Manager:: -* MVME136 Timing Data I/O Manager:: -* MVME136 Timing Data Rate Monotonic Manager:: -@end menu -@end ifinfo - -@ifinfo -@node MVME136 Timing Data Introduction, MVME136 Timing Data Hardware Platform, MVME136 Timing Data, MVME136 Timing Data -@end ifinfo + @section Introduction The timing data for the MC68020 version of RTEMS is @@ -51,9 +23,6 @@ understanding of each directive time provided. Also, provided is a description of the interrupt latency and the context switch times as they pertain to the MC68020 version of RTEMS. -@ifinfo -@node MVME136 Timing Data Hardware Platform, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Introduction, MVME136 Timing Data -@end ifinfo @section Hardware Platform All times reported except for the maximum period @@ -77,9 +46,6 @@ should be noted that the worst case instruction times for the MC68020 assume that the internal cache is disabled and that no instructions overlap. -@ifinfo -@node MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Context Switch, MVME136 Timing Data Hardware Platform, MVME136 Timing Data -@end ifinfo @section Interrupt Latency The maximum period with interrupts disabled within @@ -104,9 +70,6 @@ overhead time was generated on an MVME135 benchmark platform using the Multiprocessing Communications registers to generate as the interrupt source. -@ifinfo -@node MVME136 Timing Data Context Switch, MVME136 Timing Data Directive Times, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data -@end ifinfo @section Context Switch The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS @@ -143,8 +106,3 @@ are executing. The state of the coprocessor is task specific. The following table summarizes the context switch times for the MVME135 benchmark platform: -@include timetbl.texi - -@tex -\global\advance \smallskipamount by 4pt -@end tex diff --git a/doc/supplements/powerpc/Makefile b/doc/supplements/powerpc/Makefile index 0b8dc01a90..88836739a1 100644 --- a/doc/supplements/powerpc/Makefile +++ b/doc/supplements/powerpc/Makefile @@ -127,7 +127,7 @@ timing.texi: timing.t Makefile # 3. Build Node Structure timePSIM_.t: ../../common/timetbl.t timePSIM.t - cat timePSIM.t ../../common/timetbl.t >timePSIM_.t + cat timePSIM.t ../../common/timetbl.t >timePSIM_.t @echo >>timePSIM_.t @echo "@tex" >>timePSIM_.t @echo "\\global\\advance \\smallskipamount by 4pt" >>timePSIM_.t @@ -147,7 +147,7 @@ timePSIM.texi: timePSIM_.t Makefile # 3. Build Node Structure timeDMV177_.t: ../../common/timetbl.t timeDMV177.t - cat timeDMV177.t ../../common/timetbl.t >timeDMV177_.t + cat timeDMV177.t ../../common/timetbl.t >timeDMV177_.t @echo >>timeDMV177_.t @echo "@tex" >>timeDMV177_.t @echo "\\global\\advance \\smallskipamount by 4pt" >>timeDMV177_.t @@ -172,7 +172,7 @@ clean: rm -f $(PROJECT) $(PROJECT)-* rm -f c_$(PROJECT) c_$(PROJECT)-* rm -f intr.t $(GENERATED_FILES) - rm -f timetbl.t wksheets.t wksheets_NOTIMES.t timing.t + rm -f wksheets.t wksheets_NOTIMES.t timing.t rm -f timePSIM_.t timePSIM_.texi rm -f timeDMV177_.t timeDMV177_.texi rm -f *.fixed _* diff --git a/doc/supplements/sparc/Makefile b/doc/supplements/sparc/Makefile index 76bccc4e8a..b7c5a9f55c 100644 --- a/doc/supplements/sparc/Makefile +++ b/doc/supplements/sparc/Makefile @@ -20,12 +20,12 @@ dirs: COMMON_FILES=../../common/cpright.texi ../../common/setup.texi -GENERATED_FILES= \ - timing.texi wksheets.texi +GENERATED_FILES=\ + cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \ + bsp.texi cputable.texi timing.texi wksheets.texi timeERC32.texi FILES= $(PROJECT).texi \ - bsp.texi callconv.texi cpumodel.texi cputable.texi fatalerr.texi \ - intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \ + preface.texi \ $(GENERATED_FILES) INFOFILES=$(wildcard $(PROJECT) $(PROJECT)-*) @@ -46,27 +46,52 @@ $(PROJECT).ps: dirs $(PROJECT).dvi $(PROJECT).dvi: $(FILES) $(TEXI2DVI) $(PROJECT).texi -replace: timedata.texi - # # Chapters which get automatic processing # -# CPU Model -# Calling Conventions -# Memory Model +cpumodel.texi: cpumodel.t Makefile + $(BMENU) -p "Preface" \ + -u "Top" \ + -n "Calling Conventions" ${*}.t + +callconv.texi: callconv.t Makefile + $(BMENU) -p "CPU Model Dependent Features CPU Model Implementation Notes" \ + -u "Top" \ + -n "Memory Model" ${*}.t + +memmodel.texi: memmodel.t Makefile + $(BMENU) -p "Calling Conventions User-Provided Routines" \ + -u "Top" \ + -n "Interrupt Processing" ${*}.t # Interrupt Chapter: # 1. Replace Times and Sizes # 2. Build Node Structure +intr.t: intr_NOTIMES.t ERC32_TIMES + ${REPLACE} -p ERC32_TIMES intr_NOTIMES.t + mv intr_NOTIMES.t.fixed intr.t + +intr.texi: intr.t Makefile + $(BMENU) -p "Memory Model Flat Memory Model" \ + -u "Top" \ + -n "Default Fatal Error Processing" ${*}.t + +fatalerr.texi: fatalerr.t Makefile + $(BMENU) -p "Interrupt Processing Interrupt Stack" \ + -u "Top" \ + -n "Board Support Packages" ${*}.t -intr.texi: intr.t SIS_TIMES - ${REPLACE} -p SIS_TIMES intr.t - mv intr.t.fixed intr.texi +bsp.texi: bsp.t Makefile + $(BMENU) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \ + -u "Top" \ + -n "Processor Dependent Information Table" ${*}.t + +cputable.texi: cputable.t Makefile + $(BMENU) -p "Board Support Packages Processor Initialization" \ + -u "Top" \ + -n "Memory Requirements" ${*}.t -# Fatal Error -# BSP -# CPU Table # Worksheets Chapter: # 1. Obtain the Shared File @@ -76,8 +101,8 @@ intr.texi: intr.t SIS_TIMES wksheets_NOTIMES.t: ../../common/wksheets.t cp ../../common/wksheets.t wksheets_NOTIMES.t -wksheets.t: wksheets_NOTIMES.t SIS_TIMES - ${REPLACE} -p SIS_TIMES wksheets_NOTIMES.t +wksheets.t: wksheets_NOTIMES.t ERC32_TIMES + ${REPLACE} -p ERC32_TIMES wksheets_NOTIMES.t mv wksheets_NOTIMES.t.fixed wksheets.t wksheets.texi: wksheets.t Makefile @@ -97,19 +122,26 @@ timing.texi: timing.t Makefile -u "Top" \ -n "ERC32 Timing Data" ${*}.t -# Timing Chapter - -timetbl.t: ../../common/timetbl.t - sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \ - <../../common/timetbl.t >timetbl.t +# Timing Data for ERC32 BSP Chapter: +# 1. Copy the Shared File +# 2. Replace Times and Sizes +# 3. Build Node Structure -timetbl.texi: timetbl.t SIS_TIMES - ${REPLACE} -p SIS_TIMES timetbl.t - mv timetbl.t.fixed timetbl.texi +timeERC32_.t: ../../common/timetbl.t timeERC32.t + cat timeERC32.t ../../common/timetbl.t >timeERC32_.t + @echo >>timeERC32_.t + @echo "@tex" >>timeERC32_.t + @echo "\\global\\advance \\smallskipamount by 4pt" >>timeERC32_.t + @echo "@end tex" >>timeERC32_.t + ${REPLACE} -p ERC32_TIMES timeERC32_.t + mv timeERC32_.t.fixed timeERC32_.t + +timeERC32.texi: timeERC32_.t Makefile + $(BMENU) -p "Timing Specification Terminology" \ + -u "Top" \ + -n "Command and Variable Index" timeERC32_.t + mv timeERC32_.texi timeERC32.texi -timedata.texi: timedata.t SIS_TIMES - ${REPLACE} -p SIS_TIMES timedata.t - mv timedata.t.fixed timedata.texi html: dirs $(FILES) -mkdir -p $(WWW_INSTALL)/c_$(PROJECT) @@ -120,8 +152,9 @@ clean: rm -f *.o $(PROG) *.txt core rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE) rm -f $(PROJECT) $(PROJECT)-* - rm -f c_sparc c_sparc-* - rm -f timedata.texi timetbl.texi intr.texi $(GENERATED_FILES) - rm -f timetbl.t wksheets.t wksheets_NOTIMES.t timing.t + rm -f c_$(PROJECT) c_$(PROJECT)-* + rm -f intr.t $(GENERATED_FILES) + rm -f wksheets.t wksheets_NOTIMES.t timing.t + rm -f timeERC32_.t timeERC32_.texi rm -f *.fixed _* diff --git a/doc/supplements/sparc/bsp.t b/doc/supplements/sparc/bsp.t index 6930065cab..2ba100edbd 100644 --- a/doc/supplements/sparc/bsp.t +++ b/doc/supplements/sparc/bsp.t @@ -6,21 +6,8 @@ @c $Id$ @c -@ifinfo -@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top -@end ifinfo @chapter Board Support Packages -@ifinfo -@menu -* Board Support Packages Introduction:: -* Board Support Packages System Reset:: -* Board Support Packages Processor Initialization:: -@end menu -@end ifinfo - -@ifinfo -@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages -@end ifinfo + @section Introduction An RTEMS Board Support Package (BSP) must be designed @@ -30,9 +17,6 @@ For more information on developing a BSP, refer to the chapter titled Board Support Packages in the RTEMS Applications User's Guide. -@ifinfo -@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages -@end ifinfo @section System Reset An RTEMS based application is initiated or @@ -56,9 +40,6 @@ registers retain their value from the previous execution mode. This is true even of the Trap Base Register (TBR) whose contents reflect the last trap which occurred before the reset. -@ifinfo -@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages -@end ifinfo @section Processor Initialization It is the responsibility of the application's diff --git a/doc/supplements/sparc/callconv.t b/doc/supplements/sparc/callconv.t index 3ec25bbee1..030f9f9b5a 100644 --- a/doc/supplements/sparc/callconv.t +++ b/doc/supplements/sparc/callconv.t @@ -6,26 +6,8 @@ @c $Id$ @c -@ifinfo -@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features CPU Model Implementation Notes, Top -@end ifinfo @chapter Calling Conventions -@ifinfo -@menu -* Calling Conventions Introduction:: -* Calling Conventions Programming Model:: -* Calling Conventions Register Windows:: -* Calling Conventions Call and Return Mechanism:: -* Calling Conventions Calling Mechanism:: -* Calling Conventions Register Usage:: -* Calling Conventions Parameter Passing:: -* Calling Conventions User-Provided Routines:: -@end menu -@end ifinfo - -@ifinfo -@node Calling Conventions Introduction, Calling Conventions Programming Model, Calling Conventions, Calling Conventions -@end ifinfo + @section Introduction Each high-level language compiler generates @@ -48,24 +30,11 @@ target processor are the same, different compilers may use different calling conventions. As a result, calling conventions are both processor and compiler dependent. -@ifinfo -@node Calling Conventions Programming Model, Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions -@end ifinfo @section Programming Model -@ifinfo -@menu -* Non-Floating Point Registers:: -* Floating Point Registers:: -* Special Registers:: -@end menu -@end ifinfo This section discusses the programming model for the SPARC architecture. -@ifinfo -@node Non-Floating Point Registers, Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model -@end ifinfo @subsection Non-Floating Point Registers The SPARC architecture defines thirty-two @@ -224,9 +193,6 @@ describes the role of each of these registers: @end ifset -@ifinfo -@node Floating Point Registers, Special Registers, Non-Floating Point Registers, Calling Conventions Programming Model -@end ifinfo @subsection Floating Point Registers The SPARC V7 architecture includes thirty-two, @@ -260,9 +226,6 @@ outstanding instructions and by floating point exception handlers with the store double floating point queue (stdfq) instruction. -@ifinfo -@node Special Registers, Calling Conventions Register Windows, Floating Point Registers, Calling Conventions Programming Model -@end ifinfo @subsection Special Registers The SPARC architecture includes two special registers @@ -276,9 +239,6 @@ the psr and wim register are used to manage the register windows in the SPARC architecture. The register windows are discussed in more detail below. -@ifinfo -@node Calling Conventions Register Windows, Calling Conventions Call and Return Mechanism, Special Registers, Calling Conventions -@end ifinfo @section Register Windows The SPARC architecture includes the concept of @@ -370,9 +330,6 @@ those parameters are available in its input registers. This is a very efficient way to pass parameters as no data is actually moved by the save or restore instructions. -@ifinfo -@node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Register Windows, Calling Conventions -@end ifinfo @section Call and Return Mechanism The SPARC architecture supports a simple yet @@ -394,17 +351,11 @@ call and return mechanism does not automatically save and restore any registers. This is accomplished via the save and restore instructions which manage the set of registers windows. -@ifinfo -@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Call and Return Mechanism, Calling Conventions -@end ifinfo @section Calling Mechanism All RTEMS directives are invoked using the regular SPARC calling convention via the call instruction. -@ifinfo -@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions -@end ifinfo @section Register Usage As discussed above, the call instruction does not @@ -414,9 +365,6 @@ windows. When a register window is allocated, the new set of local registers are available for the exclusive use of the subroutine which allocated this register set. -@ifinfo -@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions -@end ifinfo @section Parameter Passing RTEMS assumes that arguments are placed in the @@ -436,9 +384,6 @@ load first argument into o0 invoke directive @end example -@ifinfo -@node Calling Conventions User-Provided Routines, Memory Model, Calling Conventions Parameter Passing, Calling Conventions -@end ifinfo @section User-Provided Routines All user-provided routines invoked by RTEMS, such as diff --git a/doc/supplements/sparc/cpumodel.t b/doc/supplements/sparc/cpumodel.t index f128f0f706..2871b08e7e 100644 --- a/doc/supplements/sparc/cpumodel.t +++ b/doc/supplements/sparc/cpumodel.t @@ -6,21 +6,8 @@ @c $Id$ @c -@ifinfo -@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top -@end ifinfo @chapter CPU Model Dependent Features -@ifinfo -@menu -* CPU Model Dependent Features Introduction:: -* CPU Model Dependent Features CPU Model Feature Flags:: -* CPU Model Dependent Features CPU Model Implementation Notes:: -@end menu -@end ifinfo - -@ifinfo -@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features, CPU Model Dependent Features -@end ifinfo + @section Introduction Microprocessors are generally classified into @@ -42,19 +29,7 @@ in significant ways, the high level of compatibility makes it possible to share the bulk of the CPU dependent executive code across the entire family. -@ifinfo -@node CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Introduction, CPU Model Dependent Features -@end ifinfo @section CPU Model Feature Flags -@ifinfo -@menu -* CPU Model Dependent Features CPU Model Name:: -* CPU Model Dependent Features Floating Point Unit:: -* CPU Model Dependent Features Bitscan Instruction:: -* CPU Model Dependent Features Number of Register Windows:: -* CPU Model Dependent Features Low Power Mode:: -@end menu -@end ifinfo Each processor family supported by RTEMS has a list of features which vary between CPU models @@ -78,9 +53,6 @@ The set of CPU model feature macros are defined in the file c/src/exec/score/cpu/sparc/sparc.h based upon the particular CPU model defined on the compilation command line. -@ifinfo -@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Feature Flags -@end ifinfo @subsection CPU Model Name The macro CPU_MODEL_NAME is a string which designates @@ -88,27 +60,18 @@ the name of this CPU model. For example, for the European Space Agency's ERC32 SPARC model, this macro is set to the string "erc32". -@ifinfo -@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Bitscan Instruction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features CPU Model Feature Flags -@end ifinfo @subsection Floating Point Unit The macro SPARC_HAS_FPU is set to 1 to indicate that this CPU model has a hardware floating point unit and 0 otherwise. -@ifinfo -@node CPU Model Dependent Features Bitscan Instruction, CPU Model Dependent Features Number of Register Windows, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags -@end ifinfo @subsection Bitscan Instruction The macro SPARC_HAS_BITSCAN is set to 1 to indicate that this CPU model has the bitscan instruction. For example, this instruction is supported by the Fujitsu SPARClite family. -@ifinfo -@node CPU Model Dependent Features Number of Register Windows, CPU Model Dependent Features Low Power Mode, CPU Model Dependent Features Bitscan Instruction, CPU Model Dependent Features CPU Model Feature Flags -@end ifinfo @subsection Number of Register Windows The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to @@ -117,9 +80,6 @@ CPU model. The SPARC architecture allows a for a maximum of thirty-two register window sets although most implementations only include eight. -@ifinfo -@node CPU Model Dependent Features Low Power Mode, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Number of Register Windows, CPU Model Dependent Features CPU Model Feature Flags -@end ifinfo @subsection Low Power Mode The macro SPARC_HAS_LOW_POWER_MODE is set to one to @@ -136,9 +96,6 @@ while ( TRUE ) @{ The code required to enter low power mode is CPU model specific. -@ifinfo -@node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Low Power Mode, CPU Model Dependent Features -@end ifinfo @section CPU Model Implementation Notes The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602 diff --git a/doc/supplements/sparc/cputable.t b/doc/supplements/sparc/cputable.t index c6fa926809..4e37375c9c 100644 --- a/doc/supplements/sparc/cputable.t +++ b/doc/supplements/sparc/cputable.t @@ -6,20 +6,8 @@ @c $Id$ @c -@ifinfo -@node Processor Dependent Information Table, Processor Dependent Information Table Introduction, Board Support Packages Processor Initialization, Top -@end ifinfo @chapter Processor Dependent Information Table -@ifinfo -@menu -* Processor Dependent Information Table Introduction:: -* Processor Dependent Information Table CPU Dependent Information Table:: -@end menu -@end ifinfo - -@ifinfo -@node Processor Dependent Information Table Introduction, Processor Dependent Information Table CPU Dependent Information Table, Processor Dependent Information Table, Processor Dependent Information Table -@end ifinfo + @section Introduction Any highly processor dependent information required @@ -28,9 +16,6 @@ Dependent Information Table. This table is not required for all processors supported by RTEMS. This chapter describes the contents, if any, for a particular processor type. -@ifinfo -@node Processor Dependent Information Table CPU Dependent Information Table, Memory Requirements, Processor Dependent Information Table Introduction, Processor Dependent Information Table -@end ifinfo @section CPU Dependent Information Table The SPARC version of the RTEMS CPU Dependent diff --git a/doc/supplements/sparc/fatalerr.t b/doc/supplements/sparc/fatalerr.t index b6b76f96be..eb035b3596 100644 --- a/doc/supplements/sparc/fatalerr.t +++ b/doc/supplements/sparc/fatalerr.t @@ -6,20 +6,8 @@ @c $Id$ @c -@ifinfo -@node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Interrupt Stack, Top -@end ifinfo @chapter Default Fatal Error Processing -@ifinfo -@menu -* Default Fatal Error Processing Introduction:: -* Default Fatal Error Processing Default Fatal Error Handler Operations:: -@end menu -@end ifinfo -@ifinfo -@node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing -@end ifinfo @section Introduction Upon detection of a fatal error by either the @@ -32,9 +20,6 @@ default fatal error handler is then invoked. This chapter describes the precise operations of the default fatal error handler. -@ifinfo -@node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing -@end ifinfo @section Default Fatal Error Handler Operations The default fatal error handler which is invoked by diff --git a/doc/supplements/sparc/intr_NOTIMES.t b/doc/supplements/sparc/intr_NOTIMES.t index 2b816feb28..4a4b0086a2 100644 --- a/doc/supplements/sparc/intr_NOTIMES.t +++ b/doc/supplements/sparc/intr_NOTIMES.t @@ -6,25 +6,8 @@ @c $Id$ @c -@ifinfo -@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top -@end ifinfo @chapter Interrupt Processing -@ifinfo -@menu -* Interrupt Processing Introduction:: -* Interrupt Processing Synchronous Versus Asynchronous Traps:: -* Interrupt Processing Vectoring of Interrupt Handler:: -* Interrupt Processing Traps and Register Windows:: -* Interrupt Processing Interrupt Levels:: -* Interrupt Processing Disabling of Interrupts by RTEMS:: -* Interrupt Processing Interrupt Stack:: -@end menu -@end ifinfo - -@ifinfo -@node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing, Interrupt Processing -@end ifinfo + @section Introduction Different types of processors respond to the @@ -47,9 +30,6 @@ interrupt and vector. In the SPARC architecture, these terms correspond to traps and trap type, respectively. The terms will be used interchangeably in this manual. -@ifinfo -@node Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing -@end ifinfo @section Synchronous Versus Asynchronous Traps The SPARC architecture includes two classes of traps: @@ -72,9 +52,6 @@ return address reported by the processor for synchronous traps is the instruction which caused the trap and the following instruction. -@ifinfo -@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Traps and Register Windows, Interrupt Processing Synchronous Versus Asynchronous Traps, Interrupt Processing -@end ifinfo @section Vectoring of Interrupt Handler Upon receipt of an interrupt the SPARC automatically @@ -141,9 +118,6 @@ A nested interrupt is processed similarly with the exception that the current stack need not be switched to the interrupt stack. -@ifinfo -@node Interrupt Processing Traps and Register Windows, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing -@end ifinfo @section Traps and Register Windows One of the register windows must be reserved at all @@ -161,9 +135,6 @@ RTEMS interrupt handler insures that a register window is available for subsequent traps before enabling traps and invoking the user's interrupt handler. -@ifinfo -@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Traps and Register Windows, Interrupt Processing -@end ifinfo @section Interrupt Levels Sixteen levels (0-15) of interrupt priorities are @@ -179,9 +150,6 @@ SPARC only supports sixteen. RTEMS interrupt levels 0 through other RTEMS interrupt levels are undefined and their behavior is unpredictable. -@ifinfo -@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing -@end ifinfo @section Disabling of Interrupts by RTEMS During the execution of directive calls, critical @@ -210,9 +178,6 @@ occur due to the inability of RTEMS to protect its critical sections. However, ISRs that make no system calls may safely execute as non-maskable interrupts. -@ifinfo -@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing -@end ifinfo @section Interrupt Stack The SPARC architecture does not provide for a diff --git a/doc/supplements/sparc/memmodel.t b/doc/supplements/sparc/memmodel.t index 1b96bebccf..3c7ae7b4e9 100644 --- a/doc/supplements/sparc/memmodel.t +++ b/doc/supplements/sparc/memmodel.t @@ -6,20 +6,8 @@ @c $Id$ @c -@ifinfo -@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top -@end ifinfo @chapter Memory Model -@ifinfo -@menu -* Memory Model Introduction:: -* Memory Model Flat Memory Model:: -@end menu -@end ifinfo -@ifinfo -@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model -@end ifinfo @section Introduction A processor may support any combination of memory @@ -31,9 +19,6 @@ memory of any kind. The appropriate memory model for RTEMS provided by the targeted processor and related characteristics of that model are described in this chapter. -@ifinfo -@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model -@end ifinfo @section Flat Memory Model The SPARC architecture supports a flat 32-bit address diff --git a/doc/supplements/sparc/sparc.texi b/doc/supplements/sparc/sparc.texi index e6f676d8a8..f00e2aa8b7 100644 --- a/doc/supplements/sparc/sparc.texi +++ b/doc/supplements/sparc/sparc.texi @@ -72,7 +72,7 @@ END-INFO-DIR-ENTRY @include cputable.texi @include wksheets.texi @include timing.texi -@include timedata.texi +@include timeERC32.texi @ifinfo @node Top, Preface, (dir), (dir) @top c_sparc diff --git a/doc/supplements/template/Makefile b/doc/supplements/template/Makefile index 1aeb754fe7..0f6200cf30 100644 --- a/doc/supplements/template/Makefile +++ b/doc/supplements/template/Makefile @@ -24,8 +24,6 @@ GENERATED_FILES=\ cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \ bsp.texi cputable.texi wksheets.texi timing.texi timeBSP.texi -# timetbl.texi timedata.texi wksheets.texi - FILES= $(PROJECT).texi preface.texi \ $(COMMON_FILES) $(GENERATED_FILES) @@ -136,7 +134,8 @@ timeBSP_.t: ../../common/timetbl.t timeBSP.t timeBSP.texi: timeBSP_.t Makefile $(BMENU) -p "Timing Specification Terminology" \ -u "Top" \ - -n "Command and Variable Index" ${*}.t + -n "Command and Variable Index" timeBSP_.t + mv timeBSP_.t timeBSP.texi html: dirs $(FILES) -mkdir -p $(WWW_INSTALL)/c_$(PROJECT) @@ -152,3 +151,4 @@ clean: rm -f intr.t rm -f timeBSP_.t timing.t rm -f *.fixed _* $(GENERATED_FILES) + rm -f timeBSP_.t -- cgit v1.2.3