From 83fb86f32b73942be758c22423c0bfe506fd4ff6 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 23 Aug 2006 19:11:14 +0000 Subject: 2006-08-23 Joel Sherrill * Makefile.am, configure.ac, FAQ/stamp-vti, FAQ/version.texi, common/cpright.texi: Merging CPU Supplements into a single document. As part of this removed the obsolete and impossible to maintain size and timing information. * cpu_supplement/.cvsignore, cpu_supplement/Makefile.am, cpu_supplement/arm.t, cpu_supplement/i386.t, cpu_supplement/m68k.t, cpu_supplement/mips.t, cpu_supplement/powerpc.t, cpu_supplement/preface.texi, cpu_supplement/sh.t, cpu_supplement/sparc.t, cpu_supplement/tic4x.t: New files. * supplements/.cvsignore, supplements/Makefile.am, supplements/supplement.am, supplements/arm/.cvsignore, supplements/arm/BSP_TIMES, supplements/arm/ChangeLog, supplements/arm/Makefile.am, supplements/arm/arm.texi, supplements/arm/bsp.t, supplements/arm/callconv.t, supplements/arm/cpumodel.t, supplements/arm/cputable.t, supplements/arm/fatalerr.t, supplements/arm/intr_NOTIMES.t, supplements/arm/memmodel.t, supplements/arm/preface.texi, supplements/arm/timeBSP.t, supplements/c4x/.cvsignore, supplements/c4x/BSP_TIMES, supplements/c4x/ChangeLog, supplements/c4x/Makefile.am, supplements/c4x/bsp.t, supplements/c4x/c4x.texi, supplements/c4x/callconv.t, supplements/c4x/cpumodel.t, supplements/c4x/cputable.t, supplements/c4x/fatalerr.t, supplements/c4x/intr_NOTIMES.t, supplements/c4x/memmodel.t, supplements/c4x/preface.texi, supplements/c4x/timeBSP.t, supplements/i386/.cvsignore, supplements/i386/ChangeLog, supplements/i386/FORCE386_TIMES, supplements/i386/Makefile.am, supplements/i386/bsp.t, supplements/i386/callconv.t, supplements/i386/cpumodel.t, supplements/i386/cputable.t, supplements/i386/fatalerr.t, supplements/i386/i386.texi, supplements/i386/intr_NOTIMES.t, supplements/i386/memmodel.t, supplements/i386/preface.texi, supplements/i386/timeFORCE386.t, supplements/m68k/.cvsignore, supplements/m68k/ChangeLog, supplements/m68k/MVME136_TIMES, supplements/m68k/Makefile.am, supplements/m68k/bsp.t, supplements/m68k/callconv.t, supplements/m68k/cpumodel.t, supplements/m68k/cputable.t, supplements/m68k/fatalerr.t, supplements/m68k/intr_NOTIMES.t, supplements/m68k/m68k.texi, supplements/m68k/memmodel.t, supplements/m68k/preface.texi, supplements/m68k/timeMVME136.t, supplements/m68k/timedata.t, supplements/mips/.cvsignore, supplements/mips/BSP_TIMES, supplements/mips/ChangeLog, supplements/mips/Makefile.am, supplements/mips/bsp.t, supplements/mips/callconv.t, supplements/mips/cpumodel.t, supplements/mips/cputable.t, supplements/mips/fatalerr.t, supplements/mips/intr_NOTIMES.t, supplements/mips/memmodel.t, supplements/mips/mips.texi, supplements/mips/preface.texi, supplements/mips/timeBSP.t, supplements/powerpc/.cvsignore, supplements/powerpc/ChangeLog, supplements/powerpc/DMV177_TIMES, supplements/powerpc/Makefile.am, supplements/powerpc/PSIM_TIMES, supplements/powerpc/bsp.t, supplements/powerpc/callconv.t, supplements/powerpc/cpumodel.t, supplements/powerpc/cputable.t, supplements/powerpc/fatalerr.t, supplements/powerpc/intr_NOTIMES.t, supplements/powerpc/memmodel.t, supplements/powerpc/powerpc.texi, supplements/powerpc/preface.texi, supplements/powerpc/timeDMV177.t, supplements/powerpc/timePSIM.t, supplements/sh/.cvsignore, supplements/sh/BSP_TIMES, supplements/sh/ChangeLog, supplements/sh/Makefile.am, supplements/sh/bsp.t, supplements/sh/callconv.t, supplements/sh/cpumodel.t, supplements/sh/cputable.t, supplements/sh/fatalerr.t, supplements/sh/intr_NOTIMES.t, supplements/sh/memmodel.t, supplements/sh/preface.texi, supplements/sh/sh.texi, supplements/sh/timeBSP.t, supplements/sparc/.cvsignore, supplements/sparc/ChangeLog, supplements/sparc/ERC32_TIMES, supplements/sparc/Makefile.am, supplements/sparc/bsp.t, supplements/sparc/callconv.t, supplements/sparc/cpumodel.t, supplements/sparc/cputable.t, supplements/sparc/fatalerr.t, supplements/sparc/intr_NOTIMES.t, supplements/sparc/memmodel.t, supplements/sparc/preface.texi, supplements/sparc/sparc.texi, supplements/sparc/timeERC32.t, supplements/template/.cvsignore, supplements/template/BSP_TIMES, supplements/template/ChangeLog, supplements/template/Makefile.am, supplements/template/bsp.t, supplements/template/callconv.t, supplements/template/cpumodel.t, supplements/template/cputable.t, supplements/template/fatalerr.t, supplements/template/intr_NOTIMES.t, supplements/template/memmodel.t, supplements/template/preface.texi, supplements/template/template.texi, supplements/template/timeBSP.t: Removed. --- doc/supplements/arm/.cvsignore | 31 ----- doc/supplements/arm/BSP_TIMES | 247 ------------------------------------- doc/supplements/arm/ChangeLog | 83 ------------- doc/supplements/arm/Makefile.am | 110 ----------------- doc/supplements/arm/arm.texi | 115 ----------------- doc/supplements/arm/bsp.t | 93 -------------- doc/supplements/arm/callconv.t | 73 ----------- doc/supplements/arm/cpumodel.t | 82 ------------ doc/supplements/arm/cputable.t | 109 ---------------- doc/supplements/arm/fatalerr.t | 37 ------ doc/supplements/arm/intr_NOTIMES.t | 122 ------------------ doc/supplements/arm/memmodel.t | 38 ------ doc/supplements/arm/preface.texi | 49 -------- doc/supplements/arm/timeBSP.t | 113 ----------------- 14 files changed, 1302 deletions(-) delete mode 100644 doc/supplements/arm/.cvsignore delete mode 100644 doc/supplements/arm/BSP_TIMES delete mode 100644 doc/supplements/arm/ChangeLog delete mode 100644 doc/supplements/arm/Makefile.am delete mode 100644 doc/supplements/arm/arm.texi delete mode 100644 doc/supplements/arm/bsp.t delete mode 100644 doc/supplements/arm/callconv.t delete mode 100644 doc/supplements/arm/cpumodel.t delete mode 100644 doc/supplements/arm/cputable.t delete mode 100644 doc/supplements/arm/fatalerr.t delete mode 100644 doc/supplements/arm/intr_NOTIMES.t delete mode 100644 doc/supplements/arm/memmodel.t delete mode 100644 doc/supplements/arm/preface.texi delete mode 100644 doc/supplements/arm/timeBSP.t (limited to 'doc/supplements/arm') diff --git a/doc/supplements/arm/.cvsignore b/doc/supplements/arm/.cvsignore deleted file mode 100644 index 0e010a5559..0000000000 --- a/doc/supplements/arm/.cvsignore +++ /dev/null @@ -1,31 +0,0 @@ -arm -arm-? -arm-?? -arm.aux -arm.cp -arm.dvi -arm.fn -arm*.html -arm.ky -arm.log -arm.pdf -arm.pg -arm.ps -arm.toc -arm.tp -arm.vr -index.html -intr.t -intr.texi -Makefile -Makefile.in -mdate-sh -rtems_footer.html -rtems_header.html -stamp-vti -timeBSP_.t -timing.t -timing.texi -version.texi -wksheets.t -wksheets.texi diff --git a/doc/supplements/arm/BSP_TIMES b/doc/supplements/arm/BSP_TIMES deleted file mode 100644 index 296602a23f..0000000000 --- a/doc/supplements/arm/BSP_TIMES +++ /dev/null @@ -1,247 +0,0 @@ -# -# CPU MODEL/BSP Timing and Size Information -# -# $Id$ -# - -# -# CPU Model Information -# -RTEMS_BSP generic-arm9dtmi -RTEMS_CPU_MODEL arm9dtmi -# -# Interrupt Latency -# -# NOTE: In general, the text says it is hand-calculated to be -# RTEMS_MAXIMUM_DISABLE_PERIOD at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ -# Mhz and this was last calculated for Release -# RTEMS_VERSION_FOR_MAXIMUM_DISABLE_PERIOD. -# -RTEMS_MAXIMUM_DISABLE_PERIOD TBD -RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ 100 -RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD ss-20020301 -# -# Context Switch Times -# -RTEMS_NO_FP_CONTEXTS 11 -RTEMS_RESTORE_1ST_FP_TASK NA -RTEMS_SAVE_INIT_RESTORE_INIT NA -RTEMS_SAVE_IDLE_RESTORE_INIT NA -RTEMS_SAVE_IDLE_RESTORE_IDLE NA -# -# Task Manager Times -# -RTEMS_TASK_CREATE_ONLY 43 -RTEMS_TASK_IDENT_ONLY 85 -RTEMS_TASK_START_ONLY 19 -RTEMS_TASK_RESTART_CALLING_TASK 26 -RTEMS_TASK_RESTART_SUSPENDED_RETURNS_TO_CALLER 23 -RTEMS_TASK_RESTART_BLOCKED_RETURNS_TO_CALLER 28 -RTEMS_TASK_RESTART_READY_RETURNS_TO_CALLER 24 -RTEMS_TASK_RESTART_SUSPENDED_PREEMPTS_CALLER 35 -RTEMS_TASK_RESTART_BLOCKED_PREEMPTS_CALLER 64 -RTEMS_TASK_RESTART_READY_PREEMPTS_CALLER 64 -RTEMS_TASK_DELETE_CALLING_TASK 55 -RTEMS_TASK_DELETE_SUSPENDED_TASK 42 -RTEMS_TASK_DELETE_BLOCKED_TASK 43 -RTEMS_TASK_DELETE_READY_TASK 43 -RTEMS_TASK_SUSPEND_CALLING_TASK 21 -RTEMS_TASK_SUSPEND_RETURNS_TO_CALLER 9 -RTEMS_TASK_RESUME_TASK_READIED_RETURNS_TO_CALLER 10 -RTEMS_TASK_RESUME_TASK_READIED_PREEMPTS_CALLER 18 -RTEMS_TASK_SET_PRIORITY_OBTAIN_CURRENT_PRIORITY 7 -RTEMS_TASK_SET_PRIORITY_RETURNS_TO_CALLER 15 -RTEMS_TASK_SET_PRIORITY_PREEMPTS_CALLER 29 -RTEMS_TASK_MODE_OBTAIN_CURRENT_MODE 4 -RTEMS_TASK_MODE_NO_RESCHEDULE 4 -RTEMS_TASK_MODE_RESCHEDULE_RETURNS_TO_CALLER 13 -RTEMS_TASK_MODE_RESCHEDULE_PREEMPTS_CALLER 30 -RTEMS_TASK_GET_NOTE_ONLY 8 -RTEMS_TASK_SET_NOTE_ONLY 7 -RTEMS_TASK_WAKE_AFTER_YIELD_RETURNS_TO_CALLER 5 -RTEMS_TASK_WAKE_AFTER_YIELD_PREEMPTS_CALLER 17 -RTEMS_TASK_WAKE_WHEN_ONLY 33 -# -# Interrupt Manager -# -RTEMS_INTR_ENTRY_RETURNS_TO_NESTED unavailable -RTEMS_INTR_ENTRY_RETURNS_TO_INTERRUPTED_TASK unavailable -RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK unavailable -RTEMS_INTR_EXIT_RETURNS_TO_NESTED unavailable -RTEMS_INTR_EXIT_RETURNS_TO_INTERRUPTED_TASK unavailable -RTEMS_INTR_EXIT_RETURNS_TO_PREEMPTING_TASK unavailable -# -# Clock Manager -# -RTEMS_CLOCK_SET_ONLY 21 -RTEMS_CLOCK_GET_ONLY 1 -RTEMS_CLOCK_TICK_ONLY 10 -# -# Timer Manager -# -RTEMS_TIMER_CREATE_ONLY 8 -RTEMS_TIMER_IDENT_ONLY 83 -RTEMS_TIMER_DELETE_INACTIVE 11 -RTEMS_TIMER_DELETE_ACTIVE 12 -RTEMS_TIMER_FIRE_AFTER_INACTIVE 14 -RTEMS_TIMER_FIRE_AFTER_ACTIVE 15 -RTEMS_TIMER_FIRE_WHEN_INACTIVE 21 -RTEMS_TIMER_FIRE_WHEN_ACTIVE 21 -RTEMS_TIMER_RESET_INACTIVE 14 -RTEMS_TIMER_RESET_ACTIVE 15 -RTEMS_TIMER_CANCEL_INACTIVE 7 -RTEMS_TIMER_CANCEL_ACTIVE 9 -# -# Semaphore Manager -# -RTEMS_SEMAPHORE_CREATE_ONLY 27 -RTEMS_SEMAPHORE_IDENT_ONLY 97 -RTEMS_SEMAPHORE_DELETE_ONLY 24 -RTEMS_SEMAPHORE_OBTAIN_AVAILABLE 5 -RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_NO_WAIT 5 -RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_CALLER_BLOCKS 28 -RTEMS_SEMAPHORE_RELEASE_NO_WAITING_TASKS 9 -RTEMS_SEMAPHORE_RELEASE_TASK_READIED_RETURNS_TO_CALLER 14 -RTEMS_SEMAPHORE_RELEASE_TASK_READIED_PREEMPTS_CALLER 22 -# -# Message Manager -# -RTEMS_MESSAGE_QUEUE_CREATE_ONLY 54 -RTEMS_MESSAGE_QUEUE_IDENT_ONLY 83 -RTEMS_MESSAGE_QUEUE_DELETE_ONLY 32 -RTEMS_MESSAGE_QUEUE_SEND_NO_WAITING_TASKS 14 -RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_RETURNS_TO_CALLER 16 -RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_PREEMPTS_CALLER 25 -RTEMS_MESSAGE_QUEUE_URGENT_NO_WAITING_TASKS 14 -RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_RETURNS_TO_CALLER 16 -RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_PREEMPTS_CALLER 25 -RTEMS_MESSAGE_QUEUE_BROADCAST_NO_WAITING_TASKS 11 -RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_RETURNS_TO_CALLER 35 -RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_PREEMPTS_CALLER 42 -RTEMS_MESSAGE_QUEUE_RECEIVE_AVAILABLE 15 -RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_NO_WAIT 10 -RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 29 -RTEMS_MESSAGE_QUEUE_FLUSH_NO_MESSAGES_FLUSHED 8 -RTEMS_MESSAGE_QUEUE_FLUSH_MESSAGES_FLUSHED 9 -# -# Event Manager -# -RTEMS_EVENT_SEND_NO_TASK_READIED 7 -RTEMS_EVENT_SEND_TASK_READIED_RETURNS_TO_CALLER 13 -RTEMS_EVENT_SEND_TASK_READIED_PREEMPTS_CALLER 22 -RTEMS_EVENT_RECEIVE_OBTAIN_CURRENT_EVENTS 1 -RTEMS_EVENT_RECEIVE_AVAILABLE 14 -RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_NO_WAIT 7 -RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 24 -# -# Signal Manager -# -RTEMS_SIGNAL_CATCH_ONLY 7 -RTEMS_SIGNAL_SEND_RETURNS_TO_CALLER 16 -RTEMS_SIGNAL_SEND_SIGNAL_TO_SELF 29 -RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_CALLING_TASK 22 -RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_PREEMPTING_TASK 25 -# -# Partition Manager -# -RTEMS_PARTITION_CREATE_ONLY 27 -RTEMS_PARTITION_IDENT_ONLY 83 -RTEMS_PARTITION_DELETE_ONLY 18 -RTEMS_PARTITION_GET_BUFFER_AVAILABLE 14 -RTEMS_PARTITION_GET_BUFFER_NOT_AVAILABLE 10 -RTEMS_PARTITION_RETURN_BUFFER_ONLY 17 -# -# Region Manager -# -RTEMS_REGION_CREATE_ONLY 29 -RTEMS_REGION_IDENT_ONLY 84 -RTEMS_REGION_DELETE_ONLY 17 -RTEMS_REGION_GET_SEGMENT_AVAILABLE 14 -RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_NO_WAIT 18 -RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_CALLER_BLOCKS 56 -RTEMS_REGION_RETURN_SEGMENT_NO_WAITING_TASKS 15 -RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_RETURNS_TO_CALLER 40 -RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_PREEMPTS_CALLER 58 -# -# Dual-Ported Memory Manager -# -RTEMS_PORT_CREATE_ONLY 18 -RTEMS_PORT_IDENT_ONLY 83 -RTEMS_PORT_DELETE_ONLY 19 -RTEMS_PORT_INTERNAL_TO_EXTERNAL_ONLY 6 -RTEMS_PORT_EXTERNAL_TO_INTERNAL_ONLY 6 -# -# IO Manager -# -RTEMS_IO_INITIALIZE_ONLY 2 -RTEMS_IO_OPEN_ONLY 1 -RTEMS_IO_CLOSE_ONLY 1 -RTEMS_IO_READ_ONLY 1 -RTEMS_IO_WRITE_ONLY 1 -RTEMS_IO_CONTROL_ONLY 1 -# -# Rate Monotonic Manager -# -RTEMS_RATE_MONOTONIC_CREATE_ONLY 18 -RTEMS_RATE_MONOTONIC_IDENT_ONLY 83 -RTEMS_RATE_MONOTONIC_CANCEL_ONLY 18 -RTEMS_RATE_MONOTONIC_DELETE_ACTIVE 23 -RTEMS_RATE_MONOTONIC_DELETE_INACTIVE 21 -RTEMS_RATE_MONOTONIC_PERIOD_INITIATE_PERIOD_RETURNS_TO_CALLER 25 -RTEMS_RATE_MONOTONIC_PERIOD_CONCLUDE_PERIOD_CALLER_BLOCKS 20 -RTEMS_RATE_MONOTONIC_PERIOD_OBTAIN_STATUS 13 -# -# Size Information -# -# -# xxx alloted for numbers -# -RTEMS_DATA_SPACE na -RTEMS_MINIMUM_CONFIGURATION na -RTEMS_MAXIMUM_CONFIGURATION na -# x,xxx alloted for numbers -RTEMS_CORE_CODE_SIZE na -RTEMS_INITIALIZATION_CODE_SIZE na -RTEMS_TASK_CODE_SIZE na -RTEMS_INTERRUPT_CODE_SIZE na -RTEMS_CLOCK_CODE_SIZE na -RTEMS_TIMER_CODE_SIZE na -RTEMS_SEMAPHORE_CODE_SIZE na -RTEMS_MESSAGE_CODE_SIZE na -RTEMS_EVENT_CODE_SIZE na -RTEMS_SIGNAL_CODE_SIZE na -RTEMS_PARTITION_CODE_SIZE na -RTEMS_REGION_CODE_SIZE na -RTEMS_DPMEM_CODE_SIZE na -RTEMS_IO_CODE_SIZE na -RTEMS_FATAL_ERROR_CODE_SIZE na -RTEMS_RATE_MONOTONIC_CODE_SIZE na -RTEMS_MULTIPROCESSING_CODE_SIZE na -# xxx alloted for numbers -RTEMS_TIMER_CODE_OPTSIZE na -RTEMS_SEMAPHORE_CODE_OPTSIZE na -RTEMS_MESSAGE_CODE_OPTSIZE na -RTEMS_EVENT_CODE_OPTSIZE na -RTEMS_SIGNAL_CODE_OPTSIZE na -RTEMS_PARTITION_CODE_OPTSIZE na -RTEMS_REGION_CODE_OPTSIZE na -RTEMS_DPMEM_CODE_OPTSIZE na -RTEMS_IO_CODE_OPTSIZE na -RTEMS_RATE_MONOTONIC_CODE_OPTSIZE na -RTEMS_MULTIPROCESSING_CODE_OPTSIZE na -# xxx alloted for numbers -RTEMS_BYTES_PER_TASK na -RTEMS_BYTES_PER_TIMER na -RTEMS_BYTES_PER_SEMAPHORE na -RTEMS_BYTES_PER_MESSAGE_QUEUE na -RTEMS_BYTES_PER_REGION na -RTEMS_BYTES_PER_PARTITION na -RTEMS_BYTES_PER_PORT na -RTEMS_BYTES_PER_PERIOD na -RTEMS_BYTES_PER_EXTENSION na -RTEMS_BYTES_PER_FP_TASK na -RTEMS_BYTES_PER_NODE na -RTEMS_BYTES_PER_GLOBAL_OBJECT na -RTEMS_BYTES_PER_PROXY na -# x,xxx alloted for numbers -RTEMS_BYTES_OF_FIXED_SYSTEM_REQUIREMENTS na diff --git a/doc/supplements/arm/ChangeLog b/doc/supplements/arm/ChangeLog deleted file mode 100644 index 74092a8203..0000000000 --- a/doc/supplements/arm/ChangeLog +++ /dev/null @@ -1,83 +0,0 @@ -2003-12-12 Ralf Corsepius - - * Makefile.am: Cosmetics. - -2003-12-11 Ralf Corsepius - - * Makefile.am: Cosmetics. - -2003-11-26 Ralf Corsepius - - * Makefile.am: Add *.info to CLEANFILES to accomodate - automake-1.7f/1.8 breaking building infos. - -2003-09-26 Joel Sherrill - - * cpumodel.t: Obsoleting HP PA-RISC port and removing all references. - -2003-09-22 Ralf Corsepius - - * Makefile.am: Merger from rtems-4-6-branch. - -2003-09-19 Joel Sherrill - - * arm.texi: Merge from branch. - -2003-01-25 Ralf Corsepius - - * arm.texi: Set @setfilename arm.info. - -2003-01-24 Ralf Corsepius - - * Makefile.am: Put GENERATED_FILES into $builddir. - -2003-01-22 Ralf Corsepius - - * version.texi: Remove from CVS. - * stamp-vti: Remove from CVS. - * .cvsignore: Add version.texi. - Add stamp-vti. - Re-sort. - -2003-01-22 Ralf Corsepius - - * wksheets.texi: Remove from CVS. - * timing.texi: Remove from CVS. - -2003-01-21 Joel Sherrill - - * stamp-vti, version.texi: Regenerated. - -2002-11-13 Joel Sherrill - - * stamp-vti, version.texi: Regenerated. - -2002-11-13 Jay Monkman - - * intr_NOTIMES.t: Real version submitted. - -2002-10-24 Joel Sherrill - - * stamp-vti, version.texi: Regenerated. - -2002-08-01 Joel Sherrill - - * BSP_TIMES, wksheets.texi: Updated to reflect ARM times - reported by Jay Monkman . These - times are subject to change as he tunes the ARM port and their BSP. - -2002-07-30 Joel Sherrill - - * .cvsignore: Corrected by tailoring for the ARM. - -2002-07-30 Joel Sherrill - - * .cvsignore: New file. - -2002-07-30 Joel Sherrill - - * BSP_TIMES, ChangeLog, Makefile.am, arm.texi, bsp.t, callconv.t, - cpumodel.t, cputable.t, fatalerr.t, intr_NOTIMES.t, memmodel.t, - preface.texi, stamp-vti, timeBSP.t, timing.texi, version.texi, - wksheets.texi: New files as ARM supplement initial version added. - diff --git a/doc/supplements/arm/Makefile.am b/doc/supplements/arm/Makefile.am deleted file mode 100644 index 3a83e7184d..0000000000 --- a/doc/supplements/arm/Makefile.am +++ /dev/null @@ -1,110 +0,0 @@ -# -# COPYRIGHT (c) 1988-2002. -# On-Line Applications Research Corporation (OAR). -# All rights reserved. -# -# $Id$ -# - -PROJECT = arm -EDITION = 1 - -include $(top_srcdir)/project.am -include $(top_srcdir)/supplements/supplement.am - -GENERATED_FILES = cpumodel.texi callconv.texi memmodel.texi intr.texi \ - fatalerr.texi bsp.texi cputable.texi wksheets.texi timing.texi \ - timeBSP.texi -COMMON_FILES += $(top_srcdir)/common/cpright.texi \ - $(top_srcdir)/common/timemac.texi - -FILES = preface.texi - -info_TEXINFOS = arm.texi -arm_TEXINFOS = $(FILES) $(COMMON_FILES) $(GENERATED_FILES) - -# -# Chapters which get automatic processing -# - -cpumodel.texi: cpumodel.t - $(BMENU2) -p "Preface" \ - -u "Top" \ - -n "Calling Conventions" < $< > $@ - -callconv.texi: callconv.t - $(BMENU2) -p "CPU Model Dependent Features Floating Point Unit" \ - -u "Top" \ - -n "Memory Model" < $< > $@ - -memmodel.texi: memmodel.t - $(BMENU2) -p "Calling Conventions User-Provided Routines" \ - -u "Top" \ - -n "Interrupt Processing" < $< > $@ - -# Interrupt Chapter: -# 1. Replace Times and Sizes -# 2. Build Node Structure -intr.texi: intr_NOTIMES.t BSP_TIMES - ${REPLACE2} -p $(srcdir)/BSP_TIMES $(srcdir)/intr_NOTIMES.t | \ - $(BMENU2) -p "Memory Model Flat Memory Model" \ - -u "Top" \ - -n "Default Fatal Error Processing" > $@ - -fatalerr.texi: fatalerr.t - $(BMENU2) -p "Interrupt Processing Interrupt Stack" \ - -u "Top" \ - -n "Board Support Packages" < $< > $@ - -bsp.texi: bsp.t - $(BMENU2) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \ - -u "Top" \ - -n "Processor Dependent Information Table" < $< > $@ - -cputable.texi: cputable.t - $(BMENU2) -p "Board Support Packages Processor Initialization" \ - -u "Top" \ - -n "Memory Requirements" < $< > $@ - -# Worksheets Chapter: -# 1. Obtain the Shared File -# 2. Replace Times and Sizes -# 3. Build Node Structure - -wksheets.texi: $(top_srcdir)/common/wksheets.t BSP_TIMES - ${REPLACE2} -p $(srcdir)/BSP_TIMES \ - $(top_srcdir)/common/wksheets.t | \ - $(BMENU2) -p "Processor Dependent Information Table CPU Dependent Information Table" \ - -u "Top" \ - -n "Timing Specification" > $@ - -# Timing Specification Chapter: -# 1. Copy the Shared File -# 3. Build Node Structure - -timing.texi: $(top_srcdir)/common/timing.t - $(BMENU2) -p "Memory Requirements RTEMS RAM Workspace Worksheet" \ - -u "Top" \ - -n "MYBSP Timing Data" < $< > $@ - -# Timing Data for BSP BSP Chapter: -# 1. Copy the Shared File -# 2. Replace Times and Sizes -# 3. Build Node Structure - -timeBSP.texi: $(top_srcdir)/common/timetbl.t timeBSP.t - cat $(srcdir)/timeBSP.t $(top_srcdir)/common/timetbl.t >timeBSP_.t - @echo >>timeBSP_.t - @echo "@tex" >>timeBSP_.t - @echo "\\global\\advance \\smallskipamount by 4pt" >>timeBSP_.t - @echo "@end tex" >>timeBSP_.t - ${REPLACE2} -p $(srcdir)/BSP_TIMES timeBSP_.t | \ - $(BMENU2) -p "Timing Specification Terminology" \ - -u "Top" \ - -n "Command and Variable Index" > $@ -CLEANFILES += timeBSP_.t - -EXTRA_DIST = BSP_TIMES bsp.t callconv.t cpumodel.t cputable.t fatalerr.t \ - intr_NOTIMES.t memmodel.t timeBSP.t - -CLEANFILES += arm.info diff --git a/doc/supplements/arm/arm.texi b/doc/supplements/arm/arm.texi deleted file mode 100644 index 32c3dcab18..0000000000 --- a/doc/supplements/arm/arm.texi +++ /dev/null @@ -1,115 +0,0 @@ -\input texinfo @c -*-texinfo-*- -@c %**start of header -@setfilename arm.info -@setcontentsaftertitlepage -@syncodeindex vr fn -@synindex ky cp -@paragraphindent 0 -@c %**end of header - -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@c -@c Master file for the ARM Applications Supplement -@c - -@include version.texi -@include common/setup.texi -@include common/rtems.texi - -@ifset use-ascii -@dircategory RTEMS Target Supplements -@direntry -* RTEMS ARM Applications Supplement: (arm). -@end direntry -@end ifset - -@c -@c Title Page Stuff -@c - -@c -@c I don't really like having a short title page. --joel -@c -@c @shorttitlepage RTEMS ARM Applications Supplement - -@setchapternewpage odd -@settitle RTEMS ARM Applications Supplement -@titlepage -@finalout - -@title RTEMS ARM Applications Supplement -@subtitle Edition @value{EDITION}, for RTEMS @value{VERSION} -@sp 1 -@subtitle @value{UPDATED} -@author On-Line Applications Research Corporation -@page - -@include common/cpright.texi -@end titlepage - -@c This prevents a black box from being printed on "overflow" lines. -@c The alternative is to rework a sentence to avoid this problem. - -@include preface.texi -@include cpumodel.texi -@include callconv.texi -@include memmodel.texi -@include intr.texi -@include fatalerr.texi -@include bsp.texi -@include cputable.texi -@include wksheets.texi -@include timing.texi -@include timeBSP.texi -@ifinfo -@node Top, Preface, (dir), (dir) -@top arm - -This is the online version of the RTEMS ARM -Applications Supplement. - -@menu -* Preface:: -* CPU Model Dependent Features:: -* Calling Conventions:: -* Memory Model:: -* Interrupt Processing:: -* Default Fatal Error Processing:: -* Board Support Packages:: -* Processor Dependent Information Table:: -* Memory Requirements:: -* Timing Specification:: -* MYBSP Timing Data:: -* Command and Variable Index:: -* Concept Index:: -@end menu - -@end ifinfo -@c -@c -@c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here -@c - -@node Command and Variable Index, Concept Index, MYBSP Timing Data Rate Monotonic Manager, Top -@unnumbered Command and Variable Index - -There are currently no Command and Variable Index entries. - -@c @printindex fn - -@node Concept Index, , Command and Variable Index, Top -@unnumbered Concept Index - -There are currently no Concept Index entries. -@c @printindex cp - -@contents -@bye - diff --git a/doc/supplements/arm/bsp.t b/doc/supplements/arm/bsp.t deleted file mode 100644 index 657c359a96..0000000000 --- a/doc/supplements/arm/bsp.t +++ /dev/null @@ -1,93 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Board Support Packages - -@section Introduction - -An RTEMS Board Support Package (BSP) must be designed -to support a particular processor and target board combination. -This chapter presents a discussion of XXX specific BSP -issues. For more information on developing a BSP, refer to the -chapter titled Board Support Packages in the RTEMS -Applications User's Guide. - -@section System Reset - -An RTEMS based application is initiated or -re-initiated when the XXX processor is reset. When the -XXX is reset, the processor performs the following actions: - -@itemize @bullet -@item The tracing bits of the status register are cleared to -disable tracing. - -@item The supervisor interrupt state is entered by setting the -supervisor (S) bit and clearing the master/interrupt (M) bit of -the status register. - -@item The interrupt mask of the status register is set to -level 7 to effectively disable all maskable interrupts. - -@item The vector base register (VBR) is set to zero. - -@item The cache control register (CACR) is set to zero to -disable and freeze the processor cache. - -@item The interrupt stack pointer (ISP) is set to the value -stored at vector 0 (bytes 0-3) of the exception vector table -(EVT). - -@item The program counter (PC) is set to the value stored at -vector 1 (bytes 4-7) of the EVT. - -@item The processor begins execution at the address stored in -the PC. -@end itemize - -@section Processor Initialization - -The address of the application's initialization code -should be stored in the first vector of the EVT which will allow -the immediate vectoring to the application code. If the -application requires that the VBR be some value besides zero, -then it should be set to the required value at this point. All -tasks share the same XXX's VBR value. Because interrupts -are enabled automatically by RTEMS as part of the initialize -executive directive, the VBR MUST be set before this directive -is invoked to insure correct interrupt vectoring. If processor -caching is to be utilized, then it should be enabled during the -reset application initialization code. - -In addition to the requirements described in the -Board Support Packages chapter of the Applications User's -Manual for the reset code which is executed before the call to -initialize executive, the XXX version has the following -specific requirements: - -@itemize @bullet -@item Must leave the S bit of the status register set so that -the XXX remains in the supervisor state. - -@item Must set the M bit of the status register to remove the -XXX from the interrupt state. - -@item Must set the master stack pointer (MSP) such that a -minimum stack size of MINIMUM_STACK_SIZE bytes is provided for -the initialize executive directive. - -@item Must initialize the XXX's vector table. -@end itemize - -Note that the BSP is not responsible for allocating -or installing the interrupt stack. RTEMS does this -automatically as part of initialization. If the BSP does not -install an interrupt stack and -- for whatever reason -- an -interrupt occurs before initialize_executive is invoked, then -the results are unpredictable. - diff --git a/doc/supplements/arm/callconv.t b/doc/supplements/arm/callconv.t deleted file mode 100644 index 167f5b8fa5..0000000000 --- a/doc/supplements/arm/callconv.t +++ /dev/null @@ -1,73 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Calling Conventions - -@section Introduction - -Each high-level language compiler generates -subroutine entry and exit code based upon a set of rules known -as the compiler's calling convention. These rules address the -following issues: - -@itemize @bullet -@item register preservation and usage -@item parameter passing -@item call and return mechanism -@end itemize - -A compiler's calling convention is of importance when -interfacing to subroutines written in another language either -assembly or high-level. Even when the high-level language and -target processor are the same, different compilers may use -different calling conventions. As a result, calling conventions -are both processor and compiler dependent. - -@section Processor Background - -The ARM architecture supports a simple yet -effective call and return mechanism. A subroutine is invoked -via the branch and link (@code{bl}) instruction. This instruction -saves the return address in the @code{lr} register. Returning -from a subroutine only requires that the return address be -moved into the program counter (@code{pc}), possibly with -an offset. It is is important to -note that the @code{bl} instruction does not -automatically save or restore any registers. It is the -responsibility of the high-level language compiler to define the -register preservation and usage convention. - -@section Calling Mechanism - -All RTEMS directives are invoked using the @code{bl} -instruction and return to the user application via the -mechanism described above. - -@section Register Usage - -As discussed above, the ARM's call and return mechanism dos -not automatically save any registers. RTEMS uses the registers -@code{r0}, @code{r1}, @code{r2}, and @code{r3} as scratch registers and -per ARM calling convention, the @code{lr} register is altered -as well. These registers are not preserved by RTEMS directives -therefore, the contents of these registers should not be assumed -upon return from any RTEMS directive. - -@section Parameter Passing - -RTEMS assumes that ARM calling conventions are followed and that -the first four arguments are placed in registers @code{r0} through -@code{r3}. If there are more arguments, than that, then they -are place on the stack. - -@section User-Provided Routines - -All user-provided routines invoked by RTEMS, such as -user extensions, device drivers, and MPCI routines, must also -adhere to these calling conventions. - diff --git a/doc/supplements/arm/cpumodel.t b/doc/supplements/arm/cpumodel.t deleted file mode 100644 index af45d1a77b..0000000000 --- a/doc/supplements/arm/cpumodel.t +++ /dev/null @@ -1,82 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter CPU Model Dependent Features - -@section Introduction - -Microprocessors are generally classified into -families with a variety of CPU models or implementations within -that family. Within a processor family, there is a high level -of binary compatibility. This family may be based on either an -architectural specification or on maintaining compatibility with -a popular processor. Recent microprocessor families such as the -ARM, SPARC, and PowerPC are based on an architectural specification -which is independent or any particular CPU model or -implementation. Older families such as the M68xxx and the iX86 -evolved as the manufacturer strived to produce higher -performance processor models which maintained binary -compatibility with older models. - -RTEMS takes advantage of the similarity of the -various models within a CPU family. Although the models do vary -in significant ways, the high level of compatibility makes it -possible to share the bulk of the CPU dependent executive code -across the entire family. Each processor family supported by -RTEMS has a list of features which vary between CPU models -within a family. For example, the most common model dependent -feature regardless of CPU family is the presence or absence of a -floating point unit or coprocessor. When defining the list of -features present on a particular CPU model, one simply notes -that floating point hardware is or is not present and defines a -single constant appropriately. Conditional compilation is -utilized to include the appropriate source code for this CPU -model's feature set. It is important to note that this means -that RTEMS is thus compiled using the appropriate feature set -and compilation flags optimal for this CPU model used. The -alternative would be to generate a binary which would execute on -all family members using only the features which were always -present. - -This chapter presents the set of features which vary -across ARM implementations and are of importance to RTEMS. -The set of CPU model feature macros are defined in the file -cpukit/score/cpu/arm/rtems/score/arm.h based upon the particular CPU -model defined on the compilation command line. - -@section CPU Model Name - -The macro @code{CPU_MODEL_NAME} is a string which designates -the architectural level of this CPU model. The following is -a list of the settings for this string based upon @code{gcc} -CPU model predefines: - -@example -__ARM_ARCH4__ "ARMv4" -__ARM_ARCH4T__ "ARMv4T" -__ARM_ARCH5__ "ARMv5" -__ARM_ARCH5T__ "ARMv5T" -__ARM_ARCH5E__ "ARMv5E" -__ARM_ARCH5TE__ "ARMv5TE" -@end example - -@section Count Leading Zeroes Instruction - -The ARMv5 and later has the count leading zeroes (@code{clz}) -instruction which could be used to speed up the find first bit -operation. The use of this instruction should significantly speed up -the scheduling associated with a thread blocking. - -@section Floating Point Unit - -The macro ARM_HAS_FPU is set to 1 to indicate that -this CPU model has a hardware floating point unit and 0 -otherwise. It does not matter whether the hardware floating -point support is incorporated on-chip or is an external -coprocessor. - diff --git a/doc/supplements/arm/cputable.t b/doc/supplements/arm/cputable.t deleted file mode 100644 index 75d0fc15f6..0000000000 --- a/doc/supplements/arm/cputable.t +++ /dev/null @@ -1,109 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Processor Dependent Information Table - -@section Introduction - -Any highly processor dependent information required -to describe a processor to RTEMS is provided in the CPU -Dependent Information Table. This table is not required for all -processors supported by RTEMS. This chapter describes the -contents, if any, for a particular processor type. - -@section CPU Dependent Information Table - -The XXX version of the RTEMS CPU Dependent -Information Table contains the information required to interface -a Board Support Package and RTEMS on the XXX. This -information is provided to allow RTEMS to interoperate -effectively with the BSP. The C structure definition is given -here: - -@example -@group -typedef struct @{ - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - /* XXX CPU family dependent stuff */ -@} rtems_cpu_table; -@end group -@end example - -@table @code -@item pretasking_hook -is the address of the user provided routine which is invoked -once RTEMS APIs are initialized. This routine will be invoked -before any system tasks are created. Interrupts are disabled. -This field may be NULL to indicate that the hook is not utilized. - -@item predriver_hook -is the address of the user provided -routine that is invoked immediately before the -the device drivers and MPCI are initialized. RTEMS -initialization is complete but interrupts and tasking are disabled. -This field may be NULL to indicate that the hook is not utilized. - -@item postdriver_hook -is the address of the user provided -routine that is invoked immediately after the -the device drivers and MPCI are initialized. RTEMS -initialization is complete but interrupts and tasking are disabled. -This field may be NULL to indicate that the hook is not utilized. - -@item idle_task -is the address of the optional user -provided routine which is used as the system's IDLE task. If -this field is not NULL, then the RTEMS default IDLE task is not -used. This field may be NULL to indicate that the default IDLE -is to be used. - -@item do_zero_of_workspace -indicates whether RTEMS should -zero the Workspace as part of its initialization. If set to -TRUE, the Workspace is zeroed. Otherwise, it is not. - -@item idle_task_stack_size -is the size of the RTEMS idle task stack in bytes. -If this number is less than MINIMUM_STACK_SIZE, then the -idle task's stack will be MINIMUM_STACK_SIZE in byte. - -@item interrupt_stack_size -is the size of the RTEMS -allocated interrupt stack in bytes. This value must be at least -as large as MINIMUM_STACK_SIZE. - -@item extra_mpci_receive_server_stack -is the extra stack space allocated for the RTEMS MPCI receive server task -in bytes. The MPCI receive server may invoke nearly all directives and -may require extra stack space on some targets. - -@item stack_allocate_hook -is the address of the optional user provided routine which allocates -memory for task stacks. If this hook is not NULL, then a stack_free_hook -must be provided as well. - -@item stack_free_hook -is the address of the optional user provided routine which frees -memory for task stacks. If this hook is not NULL, then a stack_allocate_hook -must be provided as well. - -@item XXX -is where the CPU family dependent stuff goes. - -@end table diff --git a/doc/supplements/arm/fatalerr.t b/doc/supplements/arm/fatalerr.t deleted file mode 100644 index 8a703718ea..0000000000 --- a/doc/supplements/arm/fatalerr.t +++ /dev/null @@ -1,37 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Default Fatal Error Processing - -@section Introduction - -Upon detection of a fatal error by either the -application or RTEMS the fatal error manager is invoked. The -fatal error manager will invoke the user-supplied fatal error -handlers. If no user-supplied handlers are configured, the -RTEMS provided default fatal error handler is invoked. If the -user-supplied fatal error handlers return to the executive the -default fatal error handler is then invoked. This chapter -describes the precise operations of the default fatal error -handler. - -@section Default Fatal Error Handler Operations - -The default fatal error handler which is invoked by -the @code{rtems_fatal_error_occurred} directive when there is -no user handler configured or the user handler returns control to -RTEMS. The default fatal error handler performs the -following actions: - -@itemize @bullet -@item disables processor interrupts, -@item places the error code in @b{r0}, and -@item executes an infinite loop (@code{while(0);} to -simulate a halt processor instruction. -@end itemize - diff --git a/doc/supplements/arm/intr_NOTIMES.t b/doc/supplements/arm/intr_NOTIMES.t deleted file mode 100644 index f4c61fa448..0000000000 --- a/doc/supplements/arm/intr_NOTIMES.t +++ /dev/null @@ -1,122 +0,0 @@ -@c -@c Interrupt Stack Frame Picture -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Interrupt Processing - -@section Introduction - -Different types of processors respond to the -occurrence of an interrupt in its own unique fashion. In -addition, each processor type provides a control mechanism to -allow for the proper handling of an interrupt. The processor -dependent response to the interrupt modifies the current -execution state and results in a change in the execution stream. -Most processors require that an interrupt handler utilize some -special control mechanisms to return to the normal processing -stream. Although RTEMS hides many of the processor dependent -details of interrupt processing, it is important to understand -how the RTEMS interrupt manager is mapped onto the processor's -unique architecture. Discussed in this chapter are the ARM's -interrupt response and control mechanisms as they pertain to -RTEMS. - -The ARM has 7 exception types: -@itemize @bullet - -@item Reset -@item Undefined instruction -@item Software interrupt (SWI) -@item Prefetch Abort -@item Data Abort -@item Interrupt (IRQ) -@item Fast Interrupt (FIQ) - -@end itemize - -Of these types, only IRQ and FIQ are handled through RTEMS's interrupt -vectoring. - -@section Vectoring of an Interrupt Handler - - -Unlike many other architectures, the ARM has seperate stacks for each -interrupt. When the CPU receives an interrupt, it: - -@itemize @bullet -@item switches to the exception mode corresponding to the interrupt, - -@item saves the Current Processor Status Register (CPSR) to the -exception mode's Saved Processor Status Register (SPSR), - -@item masks off the IRQ and if the interrupt source was FIQ, the FIQ -is masked off as well, - -@item saves the Program Counter (PC) to the exception mode's Link -Register (LR - same as R14), - -@item and sets the PC to the exception's vector address. - -@end itemize - -The vectors for both IRQ and FIQ point to the _ISR_Handler function. -_ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before -calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so -that it is safe to call C functions. Even ExecuteITHandler() can be written -in C. - -@section Interrupt Levels - -The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ -has a higher priority than IRQ, and has its own version of register R8 - R14, -however RTEMS does not take advantage of them. Both interrupts are enabled -through the CPSR. - -The RTEMS interrupt level mapping scheme for the AEM is not a numeric level -as on most RTEMS ports. It is a bit mapping that corresponds the enable -bits's postions in the CPSR: - -@table @b -@item FIQ -Setting bit 6 (0 is least significant bit) disables the FIQ. - -@item IRQ -Setting bit 7 (0 is least significant bit) disables the IRQ. - -@end table - - -@section Disabling of Interrupts by RTEMS - -During the execution of directive calls, critical -sections of code may be executed. When these sections are -encountered, RTEMS disables interrupts to level seven (7) before -the execution of this section and restores them to the previous -level upon completion of the section. RTEMS has been optimized -to insure that interrupts are disabled for less than -RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a -RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with -zero wait states. These numbers will vary based the -number of wait states and processor speed present on the target board. -[NOTE: The maximum period with interrupts disabled is hand calculated. This -calculation was last performed for Release -RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] - -Non-maskable interrupts (NMI) cannot be disabled, and -ISRs which execute at this level MUST NEVER issue RTEMS system -calls. If a directive is invoked, unpredictable results may -occur due to the inability of RTEMS to protect its critical -sections. However, ISRs that make no system calls may safely -execute as non-maskable interrupts. - -@section Interrupt Stack - -RTEMS expects the interrupt stacks to be set up in bsp_start(). The memory -for the stacks is reserved in the linker script. - diff --git a/doc/supplements/arm/memmodel.t b/doc/supplements/arm/memmodel.t deleted file mode 100644 index bf543364c7..0000000000 --- a/doc/supplements/arm/memmodel.t +++ /dev/null @@ -1,38 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Memory Model - -@section Introduction - -A processor may support any combination of memory -models ranging from pure physical addressing to complex demand -paged virtual memory systems. RTEMS supports a flat memory -model which ranges contiguously over the processor's allowable -address space. RTEMS does not support segmentation or virtual -memory of any kind. The appropriate memory model for RTEMS -provided by the targeted processor and related characteristics -of that model are described in this chapter. - -@section Flat Memory Model - -Members of the ARM family newer than Version 3 support a flat -32-bit address space with addresses ranging from 0x00000000 to -0xFFFFFFFF (4 gigabytes). Each address is represented by a -32-bit value and is byte addressable. -The address may be used to reference a -single byte, word (2-bytes), or long word (4 bytes). Memory -accesses within this address space are performed in the endian -mode that the processor is configured for. In general, ARM -processors are used in little endian mode. - -Some of the ARM family members such as the -920 and 720 include an MMU and thus support virtual memory and -segmentation. RTEMS does not support virtual memory or -segmentation on any of the ARM family members. - diff --git a/doc/supplements/arm/preface.texi b/doc/supplements/arm/preface.texi deleted file mode 100644 index 27bb11a558..0000000000 --- a/doc/supplements/arm/preface.texi +++ /dev/null @@ -1,49 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@ifinfo -@node Preface, CPU Model Dependent Features, Top, Top -@end ifinfo -@unnumbered Preface - -The Real Time Executive for Multiprocessor Systems (RTEMS) -is designed to be portable across multiple processor -architectures. However, the nature of real-time systems makes -it essential that the application designer understand certain -processor dependent implementation details. These processor -dependencies include calling convention, board support package -issues, interrupt processing, exact RTEMS memory requirements, -performance data, header files, and the assembly language -interface to the executive. - -This document discusses the ARM architecture dependencies -in this port of RTEMS. The ARM family has a wide variety -of implementations by a wide range of vendors. Consequently, -there are 100's of CPU models within it. - -It is highly recommended that the ARM -RTEMS application developer obtain and become familiar with the -documentation for the processor being used as well as the -documentation for the ARM architecture as a whole. - -@subheading Architecture Documents - -For information on the ARM architecture, -refer to the following documents available from Arm, Limited -(@file{http//www.arm.com/}). There does not appear to -be an electronic version of a manual on the architecture -in general on that site. The following book is a good -resource: - -@itemize @bullet -@item @cite{David Seal. "ARM Architecture Reference Manual." -Addison-Wesley. @b{ISBN 0-201-73719-1}. 2001.} - -@end itemize - - diff --git a/doc/supplements/arm/timeBSP.t b/doc/supplements/arm/timeBSP.t deleted file mode 100644 index 742272f775..0000000000 --- a/doc/supplements/arm/timeBSP.t +++ /dev/null @@ -1,113 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@include common/timemac.texi -@tex -\global\advance \smallskipamount by -4pt -@end tex - -@chapter MYBSP Timing Data - -@section Introduction - -The timing data for the ARM version of RTEMS is -provided along with the target dependent aspects concerning the -gathering of the timing data. The hardware platform used to -gather the times is described to give the reader a better -understanding of each directive time provided. Also, provided -is a description of the interrupt latency and the context switch -times as they pertain to the ARM version of RTEMS. - -@section Hardware Platform - -All times reported except for the maximum period -interrupts are disabled by RTEMS were measured using a Motorola -MYBSP CPU board. The MYBSP is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ -Mhz board with SDRAM and no numeric coprocessor. A -countdown timer on this board was used to measure -elapsed time with a 20 nanosecond resolution. All -sources of hardware interrupts were disabled, although the -interrupt level of the ARM microprocessor allows all interrupts. - -The maximum period interrupts are disabled was -measured by summing the number of CPU cycles required by each -assembly language instruction executed while interrupts were -disabled. The worst case times of the ARM9DTMI microprocessor -were used for each instruction. Zero wait state memory was -assumed. The total CPU cycles executed with interrupts -disabled, including the instructions to disable and enable -interrupts, was divided by TBD to simulate a TBD Mhz processor. It -should be noted that the worst case instruction times -assume that the internal cache is disabled and that no -instructions overlap. - -@section Interrupt Latency - -The maximum period with interrupts disabled within -RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD -microseconds including the instructions -which disable and re-enable interrupts. The time required for -the processor to vector an interrupt and for the RTEMS entry -overhead before invoking the user's interrupt handler are a -total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK -microseconds. These combine to yield a worst case -interrupt latency of less than -RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK -microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ -Mhz. [NOTE: The maximum period with interrupts -disabled was last determined for Release -RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] - -It should be noted again that the maximum period with -interrupts disabled within RTEMS is hand-timed and based upon -worst case (i.e. CPU cache disabled and no instruction overlap) -times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor. -The interrupt vector and entry -overhead time was generated on an MYBSP benchmark platform -using the Multiprocessing Communications registers to generate -as the interrupt source. - -@section Context Switch - -The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS -microseconds on the MYBSP benchmark platform when no floating -point context is saved or restored. Additional execution time -is required when a TASK_SWITCH user extension is configured. -The use of the TASK_SWITCH extension is application dependent. -Thus, its execution time is not considered part of the raw -context switch time. - -The ARM processor benchmarked does not have a floating point -unit and consequently no FPU results are reported. - -@c Since RTEMS was designed specifically for embedded -@c missile applications which are floating point intensive, the -@c executive is optimized to avoid unnecessarily saving and -@c restoring the state of the numeric coprocessor. The state of -@c the numeric coprocessor is only saved when an FLOATING_POINT -@c task is dispatched and that task was not the last task to -@c utilize the coprocessor. In a system with only one -@c FLOATING_POINT task, the state of the numeric coprocessor will -@c never be saved or restored. When the first FLOATING_POINT task -@c is dispatched, RTEMS does not need to save the current state of -@c the numeric coprocessor. - -@c The exact amount of time required to save and restore -@c floating point context is dependent on whether an XXX or -@c XXX is being used as well as the state of the numeric -@c coprocessor. These numeric coprocessors define three operating -@c states: initialized, idle, and busy. RTEMS places the -@c coprocessor in the initialized state when a task is started or -@c restarted. Once the task has utilized the coprocessor, it is in -@c the idle state when floating point instructions are not -@c executing and the busy state when floating point instructions -@c are executing. The state of the coprocessor is task specific. - -The following table summarizes the context switch -times for the MYBSP benchmark platform: - -- cgit v1.2.3