From b616350ec9e929ebb06a3c71fd94f11ce668d84f Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 29 Jun 2010 00:31:02 +0000 Subject: 2010-06-28 Joel Sherrill PR 1573/cpukit * arm_exc_interrupt.S: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed. --- cpukit/score/cpu/arm/ChangeLog | 7 +++++++ cpukit/score/cpu/arm/arm_exc_interrupt.S | 19 ++++--------------- 2 files changed, 11 insertions(+), 15 deletions(-) (limited to 'cpukit') diff --git a/cpukit/score/cpu/arm/ChangeLog b/cpukit/score/cpu/arm/ChangeLog index e7c347f590..c700021215 100644 --- a/cpukit/score/cpu/arm/ChangeLog +++ b/cpukit/score/cpu/arm/ChangeLog @@ -1,3 +1,10 @@ +2010-06-28 Joel Sherrill + + PR 1573/cpukit + * arm_exc_interrupt.S: Add a per cpu data structure which contains the + information required by RTEMS for each CPU core. This encapsulates + information such as thread executing, heir, idle and dispatch needed. + 2010-05-10 Joel Sherrill * rtems/score/arm.h: Make it a warning not error that the FPU multilib diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S index 18b129c4ad..e269e13455 100644 --- a/cpukit/score/cpu/arm/arm_exc_interrupt.S +++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S @@ -30,6 +30,7 @@ #endif #include +#include #define EXCHANGE_LR r4 #define EXCHANGE_SPSR r5 @@ -42,9 +43,6 @@ #define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12} #define CONTEXT_SIZE 28 -.extern _ISR_Nest_level -.extern _ISR_Signals_to_thread_executing -.extern _ISR_Thread_dispatch .extern _Thread_Dispatch_disable_level .extern bsp_interrupt_dispatch @@ -81,7 +79,7 @@ arm_exc_interrupt: ldmia r1, EXCHANGE_LIST /* Get interrupt nest level */ - ldr r0, =_ISR_Nest_level + ldr r0, =ISR_NEST_LEVEL ldr r2, [r0] /* Switch stack if necessary and save original stack pointer */ @@ -105,7 +103,7 @@ arm_exc_interrupt: bl bsp_interrupt_dispatch /* Decrement interrupt nest and thread dispatch disable level */ - ldr r0, =_ISR_Nest_level + ldr r0, =ISR_NEST_LEVEL ldr r1, =_Thread_Dispatch_disable_level ldr r2, [r0] ldr r3, [r1] @@ -124,13 +122,7 @@ arm_exc_interrupt: bne thread_dispatch_done /* Check context switch necessary */ - ldr r0, =_Context_Switch_necessary - ldrb r1, [r0] - ldr r0, =_ISR_Signals_to_thread_executing - cmp r1, #0 - bne do_thread_dispatch - - /* Check ISR signals to thread executing */ + ldr r0, =DISPATCH_NEEDED ldrb r1, [r0] cmp r1, #0 beq thread_dispatch_done @@ -142,9 +134,6 @@ arm_exc_interrupt: do_thread_dispatch: - /* Clear ISR signals to thread executing */ - strb r3, [r0] - /* Thread dispatch */ bl _Thread_Dispatch -- cgit v1.2.3