From a6c5a6d1ab679549c36979592b8fc979d86d004a Mon Sep 17 00:00:00 2001
From: Ralf Corsepius <ralf.corsepius@rtems.org>
Date: Thu, 9 Nov 2006 11:10:50 +0000
Subject: Remove stray whitespaces.

---
 cpukit/score/cpu/bfin/rtems/bfin/bf533.h | 20 +-----------
 cpukit/score/cpu/bfin/rtems/bfin/bfin.h  | 56 ++++++++++++++++----------------
 2 files changed, 29 insertions(+), 47 deletions(-)

(limited to 'cpukit')

diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
index a051af92e2..5389934efc 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
@@ -51,7 +51,7 @@ extern "C" {
 #define SPI_SHADOW             0xFFC00518
 
 /* SPORT0 Controller */
-#define SPORT0_TCR1            0xFFC00800 
+#define SPORT0_TCR1            0xFFC00800
 #define SPORT0_TCR2            0xFFC00804
 #define SPORT0_TCLKDIV         0xFFC00808
 #define SPORT0_TFSDIV          0xFFC0080C
@@ -359,24 +359,6 @@ extern "C" {
 #define EBIU_SDRRC             0xFFC00A18
 #define EBIU_SDSTAT            0xFFC00A1C
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
index 23ff5ea2a8..2645648bed 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
@@ -2,7 +2,7 @@
  *
  *  This file defines Macros for MMR register common to all Blackfin
  *  Processors.
- * 
+ *
  *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
  *                     and Antonio Giovanini <antonio@atos.com.br>
@@ -23,7 +23,7 @@ extern "C" {
 #endif
 
 /* Scratchpad SRAM */
- 
+
 #define SCRATCH                0xFFB00000
 #define SCRATCH_SIZE           0x1000
 #define SCRATCH_TOP            0xFFB00ffc
@@ -40,38 +40,38 @@ extern "C" {
 
 /* Event Vector Table        Chapter 4 */
 
-#define EVT0                   0xFFE02000  
-#define EVT1                   0xFFE02004  
-#define EVT2                   0xFFE02008  
-#define EVT3                   0xFFE0200C  
-#define EVT4                   0xFFE02010  
-#define EVT5                   0xFFE02014  
-#define EVT6                   0xFFE02018  
-#define EVT7                   0xFFE0201C  
-#define EVT8                   0xFFE02020  
-#define EVT9                   0xFFE02024  
-#define EVT10                  0xFFE02028  
-#define EVT11                  0xFFE0202C  
-#define EVT12                  0xFFE02030  
-#define EVT13                  0xFFE02034  
-#define EVT14                  0xFFE02038  
-#define EVT15                  0xFFE0203C  
-#define IMASK                  0xFFE02104  
-#define IPEND                  0xFFE02108  
-#define ILAT                   0xFFE0210C  
-#define IPRIO                  0xFFE02110  
- 
-/* Core Timer               Chapter 15 */
+#define EVT0                   0xFFE02000
+#define EVT1                   0xFFE02004
+#define EVT2                   0xFFE02008
+#define EVT3                   0xFFE0200C
+#define EVT4                   0xFFE02010
+#define EVT5                   0xFFE02014
+#define EVT6                   0xFFE02018
+#define EVT7                   0xFFE0201C
+#define EVT8                   0xFFE02020
+#define EVT9                   0xFFE02024
+#define EVT10                  0xFFE02028
+#define EVT11                  0xFFE0202C
+#define EVT12                  0xFFE02030
+#define EVT13                  0xFFE02034
+#define EVT14                  0xFFE02038
+#define EVT15                  0xFFE0203C
+#define IMASK                  0xFFE02104
+#define IPEND                  0xFFE02108
+#define ILAT                   0xFFE0210C
+#define IPRIO                  0xFFE02110
+
+
 #define TCNTL                  0xFFE03000
 #define TPERIOD                0xFFE03004
 #define TSCALE                 0xFFE03008
 #define TCOUNT                 0xFFE0300C
 
 /* Masks for Timer Control */
-#define TMPWR                  0x00000001  
-#define TMREN                  0x00000002  
-#define TAUTORLD               0x00000004  
-#define TINT                   0x00000008 
+#define TMPWR                  0x00000001
+#define TMREN                  0x00000002
+#define TAUTORLD               0x00000004
+#define TINT                   0x00000008
 
 /* Event Bit Positions */
 #define EVT_IVTMR_P            0x00000006
-- 
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