From 2d7aad73ea79fdfd80fa466233c7dbeceb98d43c Mon Sep 17 00:00:00 2001 From: Daniel Cederman Date: Mon, 16 Nov 2015 14:13:28 +0100 Subject: sparc: Fix context switch on SMP We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first write to PSR to be before the write to WIM, as there is now no risk that we get an interrupt where the CWP and WIM would be inconsistent. We only need to make sure that we do not use any of the non-global registers or instructions that affects CWP for three instructions after the write. In the earlier code the non-global %o1 register was used right after the write to PSR, which required the use of three nop:s. Close #2472. --- cpukit/score/cpu/sparc/cpu.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'cpukit') diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index 569b6f8ec8..5434355618 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -356,6 +356,9 @@ void _CPU_Context_Initialize( tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ + /* _CPU_Context_restore_heir() relies on this */ + _Assert( ( tmp_psr & SPARC_PSR_ET_MASK ) != 0 ); + #if (SPARC_HAS_FPU == 1) /* * If this bit is not set, then a task gets a fault when it accesses -- cgit v1.2.3