From 16ad7eafedff65567c1b9b67af4d422d1673db74 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 9 Jan 2001 16:48:26 +0000 Subject: 2001-01-09 Joel Sherrill * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels. --- cpukit/score/cpu/mips/ChangeLog | 5 +++++ cpukit/score/cpu/mips/cpu_asm.S | 10 +++++----- cpukit/score/cpu/mips/rtems/score/cpu.h | 2 +- cpukit/score/cpu/mips/rtems/score/mips.h | 16 ++++++++++++++++ 4 files changed, 27 insertions(+), 6 deletions(-) (limited to 'cpukit') diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index 39322e3962..0a3eca1838 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,8 @@ +2001-01-09 Joel Sherrill + + * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants + to make it easier to conditionalize the code for various ISA levels. + 2001-01-08 Joel Sherrill * idtcpu.h: Commented out definition of "wait". It was stupid to diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S index cc9e4ae4de..8c098a7064 100644 --- a/cpukit/score/cpu/mips/cpu_asm.S +++ b/cpukit/score/cpu/mips/cpu_asm.S @@ -367,7 +367,7 @@ ENDFRAME(_CPU_Context_switch) FRAME(_CPU_Context_switch,sp,0,ra) mfc0 t0,C0_SR - li t1,~SR_IEC + li t1,~(SR_INTERRUPT_ENABLE_BITS) sw t0,C0_SR_OFFSET*4(a0) /* save status register */ and t0,t1 mtc0 t0,C0_SR /* first disable ie bit (recommended) */ @@ -402,12 +402,12 @@ _CPU_Context_switch_restore: lw t0,C0_EPC_OFFSET*4(a1) mtc0 t0,C0_EPC lw t0, C0_SR_OFFSET*4(a1) - andi t0,SR_IEC /* we know IEC=0, e.g. disabled */ - beq t0,$0,_CPU_Context_1 /* set IEC level from restore context */ + andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */ + beq t0,$0,_CPU_Context_1 /* set level from restore context */ mfc0 t0,C0_SR nop - or t0,SR_IEC /* new_sr = sr | SR_IEC */ - mtc0 t0,C0_SR /* set with enabled */ + or t0,(SR_INTERRUPT_ENABLE_BITS) /* new_sr = old sr with enabled */ + mtc0 t0,C0_SR /* set with enabled */ _CPU_Context_1: diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index c0ed92a642..4eda5c35b1 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -599,7 +599,7 @@ extern unsigned int mips_interrupt_number_of_vectors; #define _CPU_ISR_Disable( _level ) \ do { \ mips_get_sr( _level ); \ - mips_set_sr( (_level) & ~SR_IMASK ); \ + mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \ } while(0) /* diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index f95175d362..e85540f892 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -22,6 +22,22 @@ extern "C" { #include #endif +/* + * SR bits that enable/disable interrupts + * + * NOTE: XXX what about SR_ERL? + */ + +#if __mips == 3 +#ifdef ASM +#define SR_INTERRUPT_ENABLE_BITS 0x03 +#else +#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL +#endif +#else +#define SR_INTERRUPT_ENABLE_BITS SR_IEC +#endif + /* * This file contains the information required to build * RTEMS for a particular member of the "no cpu" -- cgit v1.2.3