From e4266e1a60e8876686764dc5bcd46b9e92c1a547 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Wed, 9 Jun 2010 04:38:13 +0000 Subject: Remove (unsupported, no toolchain). --- cpukit/score/cpu/nios2/.cvsignore | 2 - cpukit/score/cpu/nios2/ChangeLog | 100 -- cpukit/score/cpu/nios2/Makefile.am | 25 - cpukit/score/cpu/nios2/cpu.c | 180 ---- cpukit/score/cpu/nios2/cpu_asm.S | 386 -------- cpukit/score/cpu/nios2/irq.c | 98 -- cpukit/score/cpu/nios2/preinstall.am | 45 - cpukit/score/cpu/nios2/rtems/asm.h | 97 -- cpukit/score/cpu/nios2/rtems/score/cpu.h | 1326 -------------------------- cpukit/score/cpu/nios2/rtems/score/cpu_asm.h | 74 -- cpukit/score/cpu/nios2/rtems/score/nios2.h | 62 -- cpukit/score/cpu/nios2/rtems/score/types.h | 51 - 12 files changed, 2446 deletions(-) delete mode 100644 cpukit/score/cpu/nios2/.cvsignore delete mode 100644 cpukit/score/cpu/nios2/ChangeLog delete mode 100644 cpukit/score/cpu/nios2/Makefile.am delete mode 100644 cpukit/score/cpu/nios2/cpu.c delete mode 100644 cpukit/score/cpu/nios2/cpu_asm.S delete mode 100644 cpukit/score/cpu/nios2/irq.c delete mode 100644 cpukit/score/cpu/nios2/preinstall.am delete mode 100644 cpukit/score/cpu/nios2/rtems/asm.h delete mode 100644 cpukit/score/cpu/nios2/rtems/score/cpu.h delete mode 100644 cpukit/score/cpu/nios2/rtems/score/cpu_asm.h delete mode 100644 cpukit/score/cpu/nios2/rtems/score/nios2.h delete mode 100644 cpukit/score/cpu/nios2/rtems/score/types.h (limited to 'cpukit/score') diff --git a/cpukit/score/cpu/nios2/.cvsignore b/cpukit/score/cpu/nios2/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/cpukit/score/cpu/nios2/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/cpukit/score/cpu/nios2/ChangeLog b/cpukit/score/cpu/nios2/ChangeLog deleted file mode 100644 index d1670cf8a8..0000000000 --- a/cpukit/score/cpu/nios2/ChangeLog +++ /dev/null @@ -1,100 +0,0 @@ -2010-03-27 Joel Sherrill - - * cpu.c, cpu_asm.S, irq.c: Add include of config.h - -2009-03-02 Joel Sherrill - - * cpu_asm.S: Eliminate extern of unused variables. - -2009-03-02 Joel Sherrill - - * cpu.c: Remove stray semi-colon. - -2009-02-12 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to - consistently return void * and take a uintptr_t argument. - -2009-02-11 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and - passing address of _Thread_Dispatch to _CPU_Initialize. Clean up - comments. - -2008-09-11 Ralf Corsépius - - * rtems/score/types.h: Do not define boolean, single_precision, - double_precision unless RTEMS_DEPRECATED_TYPES is given. - -2008-09-08 Joel Sherrill - - * rtems/score/cpu.h: Remove extraneous spaces. - -2008-08-21 Ralf Corsépius - - * rtems/score/types.h: Include stdbool.h. - Use bool as base-type for boolean. - -2008-07-31 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads. - -2008-06-05 Joel Sherrill - - * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting - parameter to indicate that the port uses the Simple Vectored - Interrupt model or the Programmable Interrupt Controller Model. The - PIC model is implemented primarily in the BSP and it is responsible - for all memory allocation. - -2007-12-17 Joel Sherrill - - * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. - -2007-12-17 Joel Sherrill - - * irq.c: Sweep to make sure grep for COPYRIGHT passes. - -2007-12-04 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU - Table to Configuration Table. Eliminate CPU Table from all ports. - Delete references to CPU Table in all forms. - -2007-12-03 Joel Sherrill - - * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to - the Configuration Table. This included pretasking_hook, - predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace, - extra_mpci_receive_server_stack, stack_allocate_hook, and - stack_free_hook. As a side-effect of this effort some multiprocessing - code was made conditional and some style clean up occurred. - -2007-04-17 Ralf Corsépius - - * rtems/score/cpu.h: - Use Context_Control_fp* instead of void* for fp_contexts. - Eliminate evil casts. - -2006-11-17 Ralf Corsépius - - * rtems/score/types.h: Remove unsigned64, signed64. - -2006-08-10 Joel Sherrill - - * .cvsignore: New file. - -2006-08-09 Kolja Waschk - - * rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/nios2.h, - rtems/score/types.h: New files. - -2006-08-09 Kolja Waschk - - * ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c, preinstall.am, - rtems/asm.h: New files. - -2005-12-09 Kolja Waschk - - Derived from no_cpu - diff --git a/cpukit/score/cpu/nios2/Makefile.am b/cpukit/score/cpu/nios2/Makefile.am deleted file mode 100644 index c1680f82fc..0000000000 --- a/cpukit/score/cpu/nios2/Makefile.am +++ /dev/null @@ -1,25 +0,0 @@ -## -## $Id$ -## - -include $(top_srcdir)/automake/compile.am - -CLEANFILES = -DISTCLEANFILES = - -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/nios2.h \ - rtems/score/cpu_asm.h rtems/score/types.h - -noinst_LIBRARIES = libscorecpu.a -libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S -libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) - -all-local: $(PREINSTALL_FILES) - -include $(srcdir)/preinstall.am - -include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/nios2/cpu.c b/cpukit/score/cpu/nios2/cpu.c deleted file mode 100644 index ff24be7efd..0000000000 --- a/cpukit/score/cpu/nios2/cpu.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * NIOS2 CPU Dependent Source - * - * COPYRIGHT (c) 1989-2006 - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize(void) -{ - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -uint32_t _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ) -{ -#if 1 - for(;;); -#else - for(;;) - { - uint32_t st = __builtin_rdctl(0); /* read status register */ - - /* Differentiate between IRQ off and on (for debugging) */ - if(st & 1) - for(;;); - else - for(;;); - - /* insert your "halt" instruction here */ ; - } -#endif -} diff --git a/cpukit/score/cpu/nios2/cpu_asm.S b/cpukit/score/cpu/nios2/cpu_asm.S deleted file mode 100644 index 206fa262f0..0000000000 --- a/cpukit/score/cpu/nios2/cpu_asm.S +++ /dev/null @@ -1,386 +0,0 @@ -/* - * $Id$ - * - * This file contains all assembly code for the - * NIOS2 implementation of RTEMS. - * - * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) - * - * Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999, - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include - - .set noat - -/* ===================================================================== */ - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * void _CPU_Context_restore( run_context, heir_context ) - * - * This routine performs a normal non-FP context switch. - */ - - .globl _CPU_Context_switch - -_CPU_Context_switch: - - rdctl r6, status - stw r16, 0(r4) - stw r17, 4(r4) - stw r18, 8(r4) - stw r19, 12(r4) - stw r20, 16(r4) - stw r21, 20(r4) - stw r22, 24(r4) - stw r23, 28(r4) - stw gp, 32(r4) - stw fp, 36(r4) - stw sp, 40(r4) - stw ra, 44(r4) - /* r6 saved status */ - stw r6, 48(r4) - -_CPU_Context_switch_restore: - - ldw r16, 0(r5) - ldw r17, 4(r5) - ldw r18, 8(r5) - ldw r19, 12(r5) - ldw r20, 16(r5) - ldw r21, 20(r5) - ldw r22, 24(r5) - ldw r23, 28(r5) - ldw gp, 32(r5) - ldw fp, 36(r5) - ldw sp, 40(r5) - - /* Disable interrupts */ - wrctl status, r0 - - ldw ea, 44(r5) - ldw at, 48(r5) - /* FIXME: Always have interrupts enabled when we return from Context_switch */ - ori at, at, 1 - wrctl estatus, at - - eret - - .globl _CPU_Context_restore - -_CPU_Context_restore: - - /* Copy first to second arg, then re-use 2nd half of Context_switch */ - mov r5, r4 - br _CPU_Context_switch_restore - - -/* ===================================================================== */ - - .globl _exception_vector - -_exception_vector: - - /* - * First, re-wind so we're pointed to the instruction where the exception - * occurred. - */ - - addi ea, ea, -4 - - /* - * Now test to determine the cause of the exception. - */ - - /* TODO: Look at [ea] if there was an unknown/trap instruction */ - - /* If interrupts are globally disabled, it certainly was no interrupt */ - rdctl et, estatus - andi et, et, 1 - beq et, zero, _Exception_Handler - - /* If no interrupts are pending, it was a software exception */ - rdctl et, ipending - beq et, zero, _Exception_Handler - - /* - * Falling through to here means that this was a hardware interrupt. - */ - - br _ISR_Handler - -/* ===================================================================== - * Exception handler: - * Responsible for unimplemented instructions and other software - * exceptions. Not responsible for hardware interrupts. Currently, - * software exceptions are regarded as error conditions, and the - * handling isn't perfect. */ - -_Exception_Handler: - - /* stw et, 108(sp') => stw et, -20(sp) */ - stw et, -20(sp) - mov et, sp - addi sp, sp, -128 - - stw r1, 0(sp) - stw r2, 4(sp) - stw r3, 8(sp) - - rdctl r1, estatus - rdctl r2, ienable - rdctl r3, ipending - - stw r4, 12(sp) - stw r5, 16(sp) - stw r6, 20(sp) - stw r7, 24(sp) - stw r8, 28(sp) - stw r9, 32(sp) - stw r10, 36(sp) - stw r11, 40(sp) - stw r12, 44(sp) - stw r13, 48(sp) - stw r14, 52(sp) - stw r15, 56(sp) - stw r16, 60(sp) - stw r17, 64(sp) - stw r18, 68(sp) - stw r19, 72(sp) - stw r20, 76(sp) - stw r21, 80(sp) - stw r22, 84(sp) - stw r23, 88(sp) - stw gp, 92(sp) - stw fp, 96(sp) - /* sp */ - stw et, 100(sp) - stw ra, 104(sp) - /* stw et, 108(sp) */ - stw ea, 112(sp) - - /* status */ - stw r1, 116(sp) - /* ienable */ - stw r2, 120(sp) - /* ipending */ - stw r3, 124(sp) - - /* - * Restore the global pointer. - */ - - movhi gp, %hiadj(_gp) - addi gp, gp, %lo(_gp) - - /* - * Pass a pointer to the stack frame as the input argument of the - * exception handler (CPU_Exception_frame *). - */ - - mov r4, sp - - /* - * Call the exception handler. - */ - - .extern __Exception_Handler - call __Exception_Handler - -stuck_in_exception: - br stuck_in_exception - - /* - * Restore the saved registers, so that all general purpose registers - * have been restored to their state at the time the interrupt occured. - */ - - ldw r1, 0(sp) - ldw r2, 4(sp) - ldw r3, 8(sp) - ldw r4, 12(sp) - ldw r5, 16(sp) - ldw r6, 20(sp) - ldw r7, 24(sp) - ldw r8, 28(sp) - ldw r9, 32(sp) - ldw r10, 36(sp) - ldw r11, 40(sp) - ldw r12, 44(sp) - ldw r13, 48(sp) - ldw r14, 52(sp) - ldw r15, 56(sp) - ldw r16, 60(sp) - ldw r17, 64(sp) - ldw r18, 68(sp) - ldw r19, 72(sp) - ldw r20, 76(sp) - ldw r21, 80(sp) - ldw r22, 84(sp) - ldw r23, 88(sp) - ldw gp, 92(sp) - ldw fp, 96(sp) - ldw ra, 104(sp) - - /* Disable interrupts */ - wrctl status, r0 - - ldw ea, 112(sp) - ldw et, 116(sp) - - /* FIXME: Enable interrupts after exception processing */ - ori et, et, 1 - wrctl estatus, et - ldw et, 108(sp) - - /* Restore stack pointer */ - ldw sp, 100(sp) - - eret - -/* ===================================================================== */ - - .section .text - -_ISR_Handler: - - /* - * Process an external hardware interrupt. - * - * First, preserve all callee saved registers on - * the stack. (See the Nios2 ABI documentation for details). - * - * Do we really need to save all? - * - * If this is interrupting a task (and not another interrupt), - * everything is saved into the task's stack, thus putting us - * in a situation similar to when the task calls a subroutine - * (and only the CPU_Context_Control subset needs to be changed) - */ - - rdctl et, estatus - - /* Keep this in the same order as CPU_Interrupt_frame: */ - - addi sp, sp, -76 - stw r1, 0(sp) - stw r2, 4(sp) - stw r3, 8(sp) - stw r4, 12(sp) - stw r5, 16(sp) - stw r6, 20(sp) - stw r7, 24(sp) - stw r8, 28(sp) - stw r9, 32(sp) - stw r10, 36(sp) - stw r11, 40(sp) - stw r12, 44(sp) - stw r13, 48(sp) - stw r14, 52(sp) - stw r15, 56(sp) - stw ra, 60(sp) - stw gp, 64(sp) - /* et contains status */ - stw et, 68(sp) - stw ea, 72(sp) - - /* - * Obtain a bitlist of the pending interrupts. - */ - - rdctl et, ipending - - /* - * Restore the global pointer to the expected value. - */ - - movhi gp, %hiadj(_gp) - addi gp, gp, %lo(_gp) - - /* - * Search through the bit list stored in r24(et) to find the first enabled - * bit. The offset of this bit is the index of the interrupt that is - * to be handled. - */ - - mov r4, zero -6: - andi r3, r24, 1 - bne r3, zero, 7f - addi r4, r4, 1 - srli r24, r24, 1 - br 6b -7: - - /* - * Having located the interrupt source, r4 contains the index of the - * interrupt to be handled. r5, the 2nd argument to the function, - * will point to the CPU_Interrupt_frame. - */ - - mov r5, sp - - .extern __ISR_Handler - call __ISR_Handler - - /* - * Now that the interrupt processing is complete, prepare to return to - * the interrupted code. - */ - - /* - * Restore the saved registers, so that all general purpose registers - * have been restored to their state at the time the interrupt occured. - */ - - ldw r1, 0(sp) - ldw r2, 4(sp) - ldw r3, 8(sp) - ldw r4, 12(sp) - ldw r5, 16(sp) - ldw r6, 20(sp) - ldw r7, 24(sp) - ldw r8, 28(sp) - ldw r9, 32(sp) - ldw r10, 36(sp) - ldw r11, 40(sp) - ldw r12, 44(sp) - ldw r13, 48(sp) - ldw r14, 52(sp) - ldw r15, 56(sp) - ldw ra, 60(sp) - ldw gp, 64(sp) - - /* Disable interrupts */ - wrctl status, r0 - - /* Restore the exception registers */ - - /* load saved ea into ea */ - ldw ea, 72(sp) - /* load saved estatus into et */ - ldw et, 68(sp) - /* Always have interrupts enabled when we return from interrupt */ - ori et, et, 1 - wrctl estatus, et - /* Restore the stack pointer */ - addi sp, sp, 76 - - /* - * Return to the interrupted instruction. - */ - eret - - diff --git a/cpukit/score/cpu/nios2/irq.c b/cpukit/score/cpu/nios2/irq.c deleted file mode 100644 index 2f13d86e3d..0000000000 --- a/cpukit/score/cpu/nios2/irq.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * NIOS2 exception and interrupt handler - * - * Derived from c4x/irq.c - * - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include - -/* - * This routine provides the RTEMS interrupt management. - * - * Upon entry, interrupts are disabled - */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr asm("sp"); - -void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr) -{ - register uint32_t level; - - /* Interrupts are disabled upon entry to this Handler */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high - 4; - } -#endif - - _ISR_Nest_level++; - - _Thread_Dispatch_disable_level++; - - if ( _ISR_Vector_table[ vector] ) - { - (*_ISR_Vector_table[ vector ])(vector, ifr); - }; - - /* Make sure that interrupts are disabled again */ - _CPU_ISR_Disable( level ); - - _Thread_Dispatch_disable_level--; - - _ISR_Nest_level--; - - if( _ISR_Nest_level == 0) - { -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - stack_ptr = _old_stack_ptr; -#endif - - if( _Thread_Dispatch_disable_level == 0 ) - { - if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) - { - _ISR_Signals_to_thread_executing = FALSE; - _CPU_ISR_Enable( level ); - _Thread_Dispatch(); - /* may have switched to another task and not return here immed. */ - _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */ - } - } - else - { - _ISR_Signals_to_thread_executing = FALSE; - }; - }; - - _CPU_ISR_Enable( level ); -} - -void __Exception_Handler(CPU_Exception_frame *efr) -{ - _CPU_Fatal_halt(0xECC0); -} - - diff --git a/cpukit/score/cpu/nios2/preinstall.am b/cpukit/score/cpu/nios2/preinstall.am deleted file mode 100644 index fd609c0ce8..0000000000 --- a/cpukit/score/cpu/nios2/preinstall.am +++ /dev/null @@ -1,45 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/nios2.h: rtems/score/nios2.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - diff --git a/cpukit/score/cpu/nios2/rtems/asm.h b/cpukit/score/cpu/nios2/rtems/asm.h deleted file mode 100644 index 390048d353..0000000000 --- a/cpukit/score/cpu/nios2/rtems/asm.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h deleted file mode 100644 index c4e113e783..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ /dev/null @@ -1,1326 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* COPYRIGHT (c) 1989-2004. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include /* pick up machine definitions */ -#ifndef ASM -#include -#endif - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or @ref CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a @ref RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - */ - -/** - * @ingroup CPUEndian - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN FALSE - -/** - * @ingroup CPUEndian - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN TRUE - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/** - * @ingroup CPUContext Management - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t status; - /* ienable? */ - /* ipending? */ -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * @ingroup CPUContext Management - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { -} Context_Control_fp; - -/** - * @ingroup CPUContext Management - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t ra; - uint32_t gp; - uint32_t et; - uint32_t ea; -} CPU_Interrupt_frame; - -/** - * @ingroup CPUContext Management - * This defines the set of integer and processor state registers that are - * saved during a software exception. - */ -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t et; - uint32_t ea; - uint32_t status; - uint32_t ienable; - uint32_t ipending; -} CPU_Exception_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/** - * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt - * stack. - */ -SCORE_EXTERN void *_CPU_Interrupt_stack_low; - -/** - * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt - * stack. - */ -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * @ingroup CPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) -/* kawk: was *4 */ - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param _isr_cookie (out) will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - _isr_cookie = __builtin_rdctl(0); /* read status register */ \ - __builtin_wrctl(0, 0); /* write 0 to status register */ \ - } - -/** - * @ingroup CPUInterrupt - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param _isr_cookie (in) contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - __builtin_wrctl( 0, _isr_cookie ); \ - } - -/** - * @ingroup CPUInterrupt - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param _isr_cookie (in) contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - __builtin_wrctl( 0, _isr_cookie ); \ - /* TODO: Does NIOS2 get a chance to \ - process IRQ between these statements? */ \ - __builtin_wrctl( 0, 0 ); \ - } - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); - -/** - * @ingroup CPUInterrupt - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param _the_context (in) is the context structure to be initialized - * @param _stack_base (in) is the lowest physical address of this task's stack - * @param _size (in) is the size of this task's stack - * @param _isr (in) is the interrupt disable level - * @param _entry_point (in) is the thread's entry point. This is - * always @a _Thread_Handler - * @param _is_fp (in) is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - do { \ - extern char _gp[]; \ - uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ - (_the_context)->gp = (void *)_gp; \ - (_the_context)->fp = (void *)_stack; \ - (_the_context)->sp = (void *)_stack; \ - (_the_context)->ra = (void *)(_entry_point); \ - (_the_context)->status = 0x1; /* IRQs enabled */ \ - } while ( 0 ) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. @ref _CPU_Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param _base (in) is the lowest physical address of the floating point - * context area - * @param _offset (in) is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if 1 -#define _CPU_Context_Fp_start( _base, _offset ) -#else -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param _destination (in) is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if 1 -#define _CPU_Context_Initialize_fp( _destination ) -#else -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _error ) \ - { \ - __builtin_wrctl(0, 0); /* write 0 to status register (disable interrupts) */ \ - __asm volatile ("mov et, %z0" : : "rM" (_error)); /* write error code to ET register */ \ - for(;;); \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ - -/** - * @ingroup CPUBitfield - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * @ingroup CPUBitfield - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * @ingroup CPUBitfield - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_Bit_map_control. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param _value (in) is the value to be scanned - * @param _output (in) is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param _priority (in) is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param vector (in) is the vector number - * @param new_handler (in) is the raw ISR handler to install - * @param old_handler (in) is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param vector (in) is the vector number - * @param new_handler (in) is the RTEMS ISR handler to install - * @param old_handler (in) is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param run (in) points to the context of the currently executing task - * @param heir (in) points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param new_context (in) points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -); - -/** - * @ingroup CPUContext - * This routine saves the floating point context passed to it. - * - * @param fp_context_ptr (in) is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUContext - * This routine restores the floating point context passed to it. - * - * @param fp_context_ptr (in) is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param value (in) is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param value (in) is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h deleted file mode 100644 index 7d6a8fe809..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file rtems/score/cpu_asm.h - */ - -/* - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2.h b/cpukit/score/cpu/nios2/rtems/score/nios2.h deleted file mode 100644 index f35eebbe8e..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/nios2.h +++ /dev/null @@ -1,62 +0,0 @@ -/* nios2.h - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specific to the NIOS2 port. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - * - */ - -#ifndef _RTEMS_SCORE_NIOS2_H -#define _RTEMS_SCORE_NIOS2_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NIOS2 family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -/* - * Define the name of the CPU family and specific model. - */ - -#define CPU_NAME "NIOS2" -#define CPU_MODEL_NAME "nios2" - -/* - * See also nios2-rtems-gcc -print-multi-lib for all valid combinations of - * - * -mno-hw-mul - * -mhw-mulx - * -mstack-check - * -pg - * -EB - * -mcustom-fpu-cfg=60-1 - * -mcustom-fpu-cfg=60-2 - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_NIOS2_H */ diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h deleted file mode 100644 index 3795195929..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/types.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file rtems/score/types.h - */ - -/* - * This include file contains type definitions pertaining to the - * Altera Nios II processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#ifndef ASM - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef uint16_t Priority_Bit_map_control; -typedef void nios2_isr; -typedef void ( *nios2_isr_entry )( void ); - -#ifdef RTEMS_DEPRECATED_TYPES -typedef bool boolean; /* Boolean value */ -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -- cgit v1.2.3