From 41dadd860aa819dc17b4f8bd16071dcebcc48553 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Wed, 9 Jun 2010 04:17:46 +0000 Subject: Remove (dead port). --- cpukit/score/cpu/c4x/.cvsignore | 2 - cpukit/score/cpu/c4x/ChangeLog | 422 ---------- cpukit/score/cpu/c4x/Makefile.am | 22 - cpukit/score/cpu/c4x/cpu.c | 180 ---- cpukit/score/cpu/c4x/cpu_asm.S | 773 ------------------ cpukit/score/cpu/c4x/irq.c | 93 --- cpukit/score/cpu/c4x/preinstall.am | 54 -- cpukit/score/cpu/c4x/rtems/asm.h | 97 --- cpukit/score/cpu/c4x/rtems/score/c4x.h | 367 --------- cpukit/score/cpu/c4x/rtems/score/cpu.h | 1225 ---------------------------- cpukit/score/cpu/c4x/rtems/score/cpu_asm.h | 72 -- cpukit/score/cpu/c4x/rtems/score/types.h | 51 -- cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h | 117 --- 13 files changed, 3475 deletions(-) delete mode 100644 cpukit/score/cpu/c4x/.cvsignore delete mode 100644 cpukit/score/cpu/c4x/ChangeLog delete mode 100644 cpukit/score/cpu/c4x/Makefile.am delete mode 100644 cpukit/score/cpu/c4x/cpu.c delete mode 100644 cpukit/score/cpu/c4x/cpu_asm.S delete mode 100644 cpukit/score/cpu/c4x/irq.c delete mode 100644 cpukit/score/cpu/c4x/preinstall.am delete mode 100644 cpukit/score/cpu/c4x/rtems/asm.h delete mode 100644 cpukit/score/cpu/c4x/rtems/score/c4x.h delete mode 100644 cpukit/score/cpu/c4x/rtems/score/cpu.h delete mode 100644 cpukit/score/cpu/c4x/rtems/score/cpu_asm.h delete mode 100644 cpukit/score/cpu/c4x/rtems/score/types.h delete mode 100644 cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h (limited to 'cpukit/score') diff --git a/cpukit/score/cpu/c4x/.cvsignore b/cpukit/score/cpu/c4x/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/cpukit/score/cpu/c4x/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/cpukit/score/cpu/c4x/ChangeLog b/cpukit/score/cpu/c4x/ChangeLog deleted file mode 100644 index 8c3d27fa57..0000000000 --- a/cpukit/score/cpu/c4x/ChangeLog +++ /dev/null @@ -1,422 +0,0 @@ -2010-03-27 Joel Sherrill - - * cpu.c, cpu_asm.S, irq.c: Add include of config.h - -2009-02-12 Joel Sherrill - - * cpu.c: Change prototype of IDLE thread to consistently return void * - and take a uintptr_t argument. - -2009-02-11 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and - passing address of _Thread_Dispatch to _CPU_Initialize. Clean up - comments. - -2008-09-11 Ralf Corsépius - - * rtems/score/types.h: Do not define boolean, single_precision, - double_precision unless RTEMS_DEPRECATED_TYPES is given. - -2008-08-21 Ralf Corsépius - - * rtems/score/types.h: Include stdbool.h. - Use bool as base-type for boolean. - -2008-07-31 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads. - -2008-06-05 Joel Sherrill - - * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting - parameter to indicate that the port uses the Simple Vectored - Interrupt model or the Programmable Interrupt Controller Model. The - PIC model is implemented primarily in the BSP and it is responsible - for all memory allocation. - -2007-12-17 Joel Sherrill - - * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. - -2007-12-17 Joel Sherrill - - * rtems/tic4x/c4xio.h: Sweep to make sure grep for COPYRIGHT passes. - -2007-12-04 Joel Sherrill - - * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU - Table to Configuration Table. Eliminate CPU Table from all ports. - Delete references to CPU Table in all forms. - -2007-12-03 Joel Sherrill - - * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to - the Configuration Table. This included pretasking_hook, - predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace, - extra_mpci_receive_server_stack, stack_allocate_hook, and - stack_free_hook. As a side-effect of this effort some multiprocessing - code was made conditional and some style clean up occurred. - -2007-05-09 Ralf Corsépius - - * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES. - -2007-04-17 Ralf Corsépius - - * rtems/score/cpu.h: - Use Context_Control_fp* instead of void* for fp_contexts. - Eliminate evil casts. - -2007-01-30 Ralf Corsépius - - * rtems/score/types.h: Use uint_least16_t for - Priority_Bit_map_control; - -2006-11-17 Ralf Corsépius - - * rtems/score/types.h: Remove unsigned64, signed64. - -2006-01-16 Joel Sherrill - - * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. - As a side-effect, grammar and spelling errors were corrected, spacing - errors were address, and some variable names were improved. - -2005-11-08 Ralf Corsepius - - * rtems/score/types.h: Eliminate unsigned16, unsigned32. - -2005-10-27 Ralf Corsepius - - * rtems/asm.h: Remove private version of CONCAT macros. - Include instead. - -2005-02-08 Ralf Corsepius - - * Makefile.am: Split out preinstallation rules. - * preinstall.am: New (Split out from Makefile.am). - -2005-02-04 Ralf Corsepius - - PR 754/rtems - * rtems/asm.h: New (relocated from .). - * asm.h: Remove (moved to rtems/asm.h). - * Makefile.am: Reflect changes above. - -2005-02-02 Ralf Corsepius - - PR rtems/752 - * rtems/tic4x/c4xio.h: New (relocated from .). - New header guard. - * c4xio.h: Remove. - * Makefile.am: Reflect changes above. - -2004-01-28 Ralf Corsepius - - * asm.h, rtems/score/c4x.h, rtems/score/cpu.h, - rtems/score/cpu_asm.h, rtems/score/types.h: New header guards. - -2005-01-24 Ralf Corsepius - - * rtems/score/types.h: Remove signed8, signed16, signed32, - unsigned8, unsigned16, unsigned32. - -2005-01-24 Ralf Corsepius - - * rtems/score/cpu.h: *_swap_u32( uint32_t ). - -2005-01-24 Ralf Corsepius - - * rtems/score/types.h: #include . - -2005-01-07 Ralf Corsepius - - * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V. - -2005-01-01 Ralf Corsepius - - * Makefile.am: Remove build-variant support. - -2004-11-21 Ralf Corsepius - - * rtems/score/types.h: Use __rtems_score_types_h as preprocessor - guard. - -2004-11-21 Ralf Corsepius - - * asm.h: Add doxygen preamble. - -2004-10-02 Ralf Corsepius - - * rtems/score/c4x.h: Add doxygen preamble. - * rtems/score/cpu.h: Add doxygen preamble. - * rtems/score/cpu_asm.h: Add doxygen preamble. - * rtems/score/types.h: Add doxygen preamble. - -2004-09-29 Joel Sherrill - - * rtems/score/cpu.h: i960 obsoleted and all references removed. - -2004-04-06 Ralf Corsepius - - * configure.ac: Remove (Merged into $(top_srcdir)/configure.ac). - * Makefile.am: Don't include multilib.am. - Reflect merging configure.ac into $(top_srcdir)/configure.ac. - -2004-04-02 Ralf Corsepius - - * Makefile.am: Install c4xio.h to $(includedir)/rtems/c4x. - -2004-04-01 Ralf Corsepius - - * Makefile.am: Install asm.h to $(includedir)/rtems. - -2004-04-01 Ralf Corsepius - - * cpu_asm.S: Include instead of . - -2004-03-30 Ralf Corsepius - - * c4xio.h, cpu.c, irq.c, rtems/score/cpu.h: Convert to using c99 - fixed size types. - -2004-03-29 Ralf Corsepius - - * configure.ac: RTEMS_TOP([../../../..]). - -2004-01-21 Ralf Corsepius - - * configure.ac: Move RTEMS_TOP one subdir down. - -2004-01-19 Ralf Corsepius - - * Makefile.am: Add PREINSTALL_DIRS. - -2004-01-14 Ralf Corsepius - - * Makefile.am: Re-add dirstamps to PREINSTALL_FILES. - Add PREINSTALL_FILES to CLEANFILES. - -2004-01-12 Ralf Corsepius - - * configure.ac: Requires automake >= 1.8.1. - -2004-01-11 Ralf Corsepius - - * Makefile.am: Include compile.am, again. - -2004-01-11 Ralf Corsepius - - * Makefile.am: Convert to using automake compilation rules. - -2003-12-12 Ralf Corsepius - - * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES. - -2003-12-12 Ralf Corsepius - - * configure.ac: Require automake >= 1.8, autoconf >= 2.59. - -2003-12-01 Ralf Corsepius - - * Makefile.am: Remove TMPINSTALL_FILES. - -2003-11-30 Ralf Corsepius - - * Makefile.am: Add $(dirstamp) to preinstallation rules. - -2003-11-23 Ralf Corsepius - - * Makefile.am: Don't use gmake rules for preinstallation. - -2003-10-21 Ralf Corsepius - - * configure.ac: Remove RTEMS_CANONICAL_HOST. - -2003-10-21 Ralf Corsepius - - * configure.ac: Remove RTEMS_CHECK_CPU. - -2003-09-26 Joel Sherrill - - * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all - references. - -2003-09-04 Joel Sherrill - - * cpu.c, cpu_asm.S, irq.c, rtems/score/c4x.h, rtems/score/cpu.h, - rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed. - -2003-08-11 Ralf Corsepius - - * configure.ac: Use rtems-bugs@rtems.com as bug report email address. - -2003-03-06 Ralf Corsepius - - * configure.ac: Remove AC_CONFIG_AUX_DIR. - -2003-02-11 Joel Sherrill - - * irq.c: Rework logic that decides when to call - _Thread_Dispatch. Analysis by Sergei Organov - determined that _ISR_Signals_to_thread_executing was not being - honored and/or cleared properly. - -2002-12-11 Ralf Corsepius - - * configure.ac: Require autoconf-2.57 + automake-1.7.2. - * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS. - -2002-11-19 Ralf Corsepius - - * configure.ac: Fix package name. - -2002-10-25 Ralf Corsepius - - * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE. - -2002-10-21 Ralf Corsepius - - * .cvsignore: Reformat. - Add autom4te*cache. - Remove autom4te.cache. - -2002-07-26 Ralf Corsepius - - * Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel. - -2002-07-22 Ralf Corsepius - - * Makefile.am: Use .$(OBJEXT) instead of .o. - -2002-07-22 Ralf Corsepius - - * Makefile.am: Use . instead of .o. - -2002-07-05 Joel Sherrill - - * cpu.c, irq.c, rtems/score/cpu.h: Filled in something that was - marked XXX. - -2002-07-05 Ralf Corsepius - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/c4xtypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-09 Ralf Corsepius - - * asm.h: Remove #include . - Add #include . - - - -2002-02-05 Ralf Corsepius - - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. - -2001-12-20 Ralf Corsepius - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill , - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-18 Joel Sherrill - - * rtems/score/c4x.h: Modified to properly multilib. This required - using only macros predefined by gcc. - -2000-09-04 Ralf Corsepius - - * Makefile.am: Include compile.am, formatting. - * rtems/Makefile.am: formatting. - * rtems/score/Makefile.am: formatting. - -2000-08-10 Joel Sherrill - - * ChangeLog: New file. diff --git a/cpukit/score/cpu/c4x/Makefile.am b/cpukit/score/cpu/c4x/Makefile.am deleted file mode 100644 index e8ccf6da39..0000000000 --- a/cpukit/score/cpu/c4x/Makefile.am +++ /dev/null @@ -1,22 +0,0 @@ -## -## $Id$ -## - -include $(top_srcdir)/automake/compile.am - -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_tic4xdir = $(includedir)/rtems/tic4x -include_rtems_tic4x_HEADERS = rtems/tic4x/c4xio.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/c4x.h \ - rtems/score/types.h rtems/score/cpu_asm.h - -noinst_LIBRARIES = libscorecpu.a -libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S -libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) - -include $(srcdir)/preinstall.am -include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/c4x/cpu.c b/cpukit/score/cpu/c4x/cpu.c deleted file mode 100644 index 71b497ce91..0000000000 --- a/cpukit/score/cpu/c4x/cpu.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C4x CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * C4x Specific Information: - * - */ - -void _CPU_Initialize(void) -{ -#if (CPU_HARDWARE_FP == TRUE) - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ -#endif -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * C4x Specific Information: - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - void **ittp; - - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - - ittp = c4x_get_ittp(); - *old_handler = ittp[ vector ]; - ittp[ vector ] = new_handler; -} - -/*XXX */ - -#define C4X_CACHE 1 -#define C4X_BASE_ST (C4X_CACHE==1) ? 0x4800 : 0x4000 - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp -) -{ - unsigned int *_stack; - _stack = (unsigned int *)_stack_base; - - *_stack = (unsigned int) _entry_point; - _the_context->sp = (unsigned int) _stack; - _the_context->st = C4X_BASE_ST; - if ( _isr == 0 ) - _the_context->st |= C4X_ST_GIE; -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * C4x Specific Information: - * - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - extern void rtems_irq_prologue_0(void); - extern void rtems_irq_prologue_1(void); - void *entry; - - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - entry = (void *)rtems_irq_prologue_0 + - ((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector); - _CPU_ISR_install_raw_handler( vector, entry, &ignored ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * C4x Specific Information: - * - * - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1) -void *_CPU_Thread_Idle_body( uintptr_t ignored ) -{ - - for( ; ; ) { - __asm__( "idle" ); - __asm__( "nop" ); - __asm__( "nop" ); - __asm__( "nop" ); - /* insert your "halt" instruction here */ ; - } -} -#endif diff --git a/cpukit/score/cpu/c4x/cpu_asm.S b/cpukit/score/cpu/c4x/cpu_asm.S deleted file mode 100644 index d4a4d25acb..0000000000 --- a/cpukit/score/cpu/c4x/cpu_asm.S +++ /dev/null @@ -1,773 +0,0 @@ -/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * void _CPU_Context_save_fp( - * void **fp_context_ptr - * - * C4x Specific Information: - * - * There is no distiniction between FP and integer context in this port. - */ - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * - * C4x Specific Information: - * - * There is no distiniction between FP and integer context in this port. - */ - - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * - * TMS320C3x General-Purpose Applications User's Guide, section 2.4 - * (p 2-11 and following), Context Switching in Interrupts and - * Subroutines states that "If the program is in a subroutine, it - * must preserve the dedicated C registers as follows:" - * - * Save as Integers Save as Floating-Point - * ================ ====================== - * R4 R8 R6 R7 - * AR4 AR5 - * AR6 AR7 - * FP DP (small model only) - * SP - */ - - .global SYM(_CPU_Context_switch) -SYM(_CPU_Context_switch): - .if .REGPARM == 0 - ldi sp, ar0 - ldi *ar0, ar2 ; get the location of running context - .endif - sti st,*ar2++ ; store status word - sti ar3,*ar2++ ; store ar3 - sti ar4,*ar2++ ; store ar4 - sti ar5,*ar2++ ; store ar5 - sti ar6,*ar2++ ; store ar6 - sti ar7,*ar2++ ; store ar7 - sti r4,*ar2++ ; store integer portion of r4 - sti r5,*ar2++ ; store integer portion of r5 - stf r6,*ar2++ ; store float portion of r6 - stf r7,*ar2++ ; store float portion of r7 - .if .TMS320C40 - sti r8,*ar2++ ; store integer portion of r8 - .endif - sti sp,*ar2++ ; store sp - - ; end of save - - .if .REGPARM == 0 - ldi *-ar0(2), ar2 ; get the location of heir context - .else - ldi r2,ar2 - .endif -_local_restore: - ldi *ar2++,ar0 ; load status word into register - ldi *ar2++,ar3 ; load ar3 - ldi *ar2++,ar4 ; load ar4 - ldi *ar2++,ar5 ; load ar5 - ldi *ar2++,ar6 ; load ar6 - ldi *ar2++,ar7 ; load ar7 - ldi *ar2++,r4 ; load integer portion of r4 - ldi *ar2++,r5 ; load integer portion of r5 - ldf *ar2++,r6 ; load float portion of r6 - ldf *ar2++,r7 ; load float portion of r7 - .if .TMS320C40 - ldi *ar2++,r8 ; load integer portion of r8 - .endif - ldi *ar2++,sp ; load sp - ldi ar0,st ; restore status word and interrupts - rets - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * void _CPU_Context_restore( - * Context_Control *new_context - * ) - */ - - .global SYM(_CPU_Context_restore) -SYM(_CPU_Context_restore): - .if .REGPARM == 0 - ldi sp, ar0 - ldi *ar0, ar2 ; get the location of context to restore - .endif - br _local_restore - -/* void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * void _ISR_Handler() - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - */ - - /* - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - * - * _ISR_Nest_level++; - * - * _Thread_Dispatch_disable_level++; - * - * (*_ISR_Vector_table[ vector ])( vector ); - * - * --_ISR_Nest_level; - * - * if ( _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary ) - * goto the label "exit interrupt (simple case)" - * - * if ( !_ISR_Signals_to_thread_executing ) - * _ISR_Signals_to_thread_executing = FALSE; - * goto the label "exit interrupt (simple case)" - * - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - * - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ - - .global SYM(_ISR_Handler_save_registers) -SYM(_ISR_Handler_save_registers): - ; no push st because it is already pushed - ; no push ar2 because it is already pushed and vector number loaded - push ar0 - push ar1 - push dp - push ir0 - push ir1 - push rs - push re - push rc - push bk - - push r0 - pushf r0 - push r1 - pushf r1 - push r2 - pushf r2 - push r3 - pushf r3 - ; no push r4 because other part of register is in basic context - push r4 - pushf r4 - ; no push r5 because other part of register is in basic context - push r5 - pushf r5 - push r6 - pushf r6 - ; no pushf r6 because other part of register is in basic context - push r7 - pushf r7 - ; no pushf r7 because other part of register is in basic context - .if .TMS320C40 - push r8 - ; no pushf r8 because other part of register is in basic context - push r9 - pushf r9 - push r10 - pushf r10 - push r11 - pushf r11 - .endif - - ldi sp,r2 - call SYM(__ISR_Handler) - - .if .TMS320C40 - popf r11 - pop r11 - popf r10 - pop r10 - popf r9 - pop r9 - ; no popf r8 because other part of register is in basic context - pop r8 - .endif - ; no popf r7 because other part of register is in basic context - popf r7 - pop r7 - ; no popf r6 because other part of register is in basic context - popf r6 - pop r6 - ; no popf r5 because other part of register is in basic context - popf r5 - pop r5 - ; no pop r4 because other part of register is in basic context - popf r4 - pop r4 - popf r3 - pop r3 - popf r2 - pop r2 - popf r1 - pop r1 - popf r0 - pop r0 - - pop bk - pop rc - pop re - pop rs - pop ir1 - pop ir0 - pop dp - pop ar1 - pop ar0 - pop ar2 ; because the vector numbers goes here - pop st - reti - -/* - * Prologues so we can know the vector number. Generated by this script: - * - * i=0 - * while test $i -lt 64 - * do - * - * printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i - * printf "SYM(rtems_irq_prologue_%X):\n" $i - * printf "\tpush\tst\n" - * printf "\tpush\tar2\n" - * printf "\tldi\t0x%x,ar2\n" $i - * printf "\tbr\tSYM(_ISR_Handler_save_registers)\n" - * printf "\n" - * i=`expr $i + 1` - * - * done - */ - - .global SYM(rtems_irq_prologue_0) -SYM(rtems_irq_prologue_0): - push st - push ar2 - ldi 0x0,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1) -SYM(rtems_irq_prologue_1): - push st - push ar2 - ldi 0x1,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2) -SYM(rtems_irq_prologue_2): - push st - push ar2 - ldi 0x2,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3) -SYM(rtems_irq_prologue_3): - push st - push ar2 - ldi 0x3,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_4) -SYM(rtems_irq_prologue_4): - push st - push ar2 - ldi 0x4,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_5) -SYM(rtems_irq_prologue_5): - push st - push ar2 - ldi 0x5,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_6) -SYM(rtems_irq_prologue_6): - push st - push ar2 - ldi 0x6,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_7) -SYM(rtems_irq_prologue_7): - push st - push ar2 - ldi 0x7,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_8) -SYM(rtems_irq_prologue_8): - push st - push ar2 - ldi 0x8,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_9) -SYM(rtems_irq_prologue_9): - push st - push ar2 - ldi 0x9,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_A) -SYM(rtems_irq_prologue_A): - push st - push ar2 - ldi 0xa,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_B) -SYM(rtems_irq_prologue_B): - push st - push ar2 - ldi 0xb,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_C) -SYM(rtems_irq_prologue_C): - push st - push ar2 - ldi 0xc,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_D) -SYM(rtems_irq_prologue_D): - push st - push ar2 - ldi 0xd,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_E) -SYM(rtems_irq_prologue_E): - push st - push ar2 - ldi 0xe,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_F) -SYM(rtems_irq_prologue_F): - push st - push ar2 - ldi 0xf,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_10) -SYM(rtems_irq_prologue_10): - push st - push ar2 - ldi 0x10,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_11) -SYM(rtems_irq_prologue_11): - push st - push ar2 - ldi 0x11,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_12) -SYM(rtems_irq_prologue_12): - push st - push ar2 - ldi 0x12,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_13) -SYM(rtems_irq_prologue_13): - push st - push ar2 - ldi 0x13,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_14) -SYM(rtems_irq_prologue_14): - push st - push ar2 - ldi 0x14,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_15) -SYM(rtems_irq_prologue_15): - push st - push ar2 - ldi 0x15,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_16) -SYM(rtems_irq_prologue_16): - push st - push ar2 - ldi 0x16,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_17) -SYM(rtems_irq_prologue_17): - push st - push ar2 - ldi 0x17,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_18) -SYM(rtems_irq_prologue_18): - push st - push ar2 - ldi 0x18,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_19) -SYM(rtems_irq_prologue_19): - push st - push ar2 - ldi 0x19,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1A) -SYM(rtems_irq_prologue_1A): - push st - push ar2 - ldi 0x1a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1B) -SYM(rtems_irq_prologue_1B): - push st - push ar2 - ldi 0x1b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1C) -SYM(rtems_irq_prologue_1C): - push st - push ar2 - ldi 0x1c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1D) -SYM(rtems_irq_prologue_1D): - push st - push ar2 - ldi 0x1d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1E) -SYM(rtems_irq_prologue_1E): - push st - push ar2 - ldi 0x1e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1F) -SYM(rtems_irq_prologue_1F): - push st - push ar2 - ldi 0x1f,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_20) -SYM(rtems_irq_prologue_20): - push st - push ar2 - ldi 0x20,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_21) -SYM(rtems_irq_prologue_21): - push st - push ar2 - ldi 0x21,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_22) -SYM(rtems_irq_prologue_22): - push st - push ar2 - ldi 0x22,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_23) -SYM(rtems_irq_prologue_23): - push st - push ar2 - ldi 0x23,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_24) -SYM(rtems_irq_prologue_24): - push st - push ar2 - ldi 0x24,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_25) -SYM(rtems_irq_prologue_25): - push st - push ar2 - ldi 0x25,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_26) -SYM(rtems_irq_prologue_26): - push st - push ar2 - ldi 0x26,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_27) -SYM(rtems_irq_prologue_27): - push st - push ar2 - ldi 0x27,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_28) -SYM(rtems_irq_prologue_28): - push st - push ar2 - ldi 0x28,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_29) -SYM(rtems_irq_prologue_29): - push st - push ar2 - ldi 0x29,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2A) -SYM(rtems_irq_prologue_2A): - push st - push ar2 - ldi 0x2a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2B) -SYM(rtems_irq_prologue_2B): - push st - push ar2 - ldi 0x2b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2C) -SYM(rtems_irq_prologue_2C): - push st - push ar2 - ldi 0x2c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2D) -SYM(rtems_irq_prologue_2D): - push st - push ar2 - ldi 0x2d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2E) -SYM(rtems_irq_prologue_2E): - push st - push ar2 - ldi 0x2e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2F) -SYM(rtems_irq_prologue_2F): - push st - push ar2 - ldi 0x2f,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_30) -SYM(rtems_irq_prologue_30): - push st - push ar2 - ldi 0x30,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_31) -SYM(rtems_irq_prologue_31): - push st - push ar2 - ldi 0x31,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_32) -SYM(rtems_irq_prologue_32): - push st - push ar2 - ldi 0x32,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_33) -SYM(rtems_irq_prologue_33): - push st - push ar2 - ldi 0x33,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_34) -SYM(rtems_irq_prologue_34): - push st - push ar2 - ldi 0x34,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_35) -SYM(rtems_irq_prologue_35): - push st - push ar2 - ldi 0x35,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_36) -SYM(rtems_irq_prologue_36): - push st - push ar2 - ldi 0x36,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_37) -SYM(rtems_irq_prologue_37): - push st - push ar2 - ldi 0x37,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_38) -SYM(rtems_irq_prologue_38): - push st - push ar2 - ldi 0x38,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_39) -SYM(rtems_irq_prologue_39): - push st - push ar2 - ldi 0x39,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3A) -SYM(rtems_irq_prologue_3A): - push st - push ar2 - ldi 0x3a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3B) -SYM(rtems_irq_prologue_3B): - push st - push ar2 - ldi 0x3b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3C) -SYM(rtems_irq_prologue_3C): - push st - push ar2 - ldi 0x3c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3D) -SYM(rtems_irq_prologue_3D): - push st - push ar2 - ldi 0x3d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3E) -SYM(rtems_irq_prologue_3E): - push st - push ar2 - ldi 0x3e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3F) -SYM(rtems_irq_prologue_3F): - push st - push ar2 - ldi 0x3f,ar2 - br SYM(_ISR_Handler_save_registers) diff --git a/cpukit/score/cpu/c4x/irq.c b/cpukit/score/cpu/c4x/irq.c deleted file mode 100644 index 00e6366b31..0000000000 --- a/cpukit/score/cpu/c4x/irq.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * C4x CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include - -/* - * This routine provides the RTEMS interrupt management. - */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr asm("sp"); - -void __ISR_Handler(uint32_t vector, void *isr_sp) -{ - register uint32_t level; - - /* already disabled when we get here */ - /* _CPU_ISR_Disable( level ); */ - - _Thread_Dispatch_disable_level++; - -#if 0 - if ( stack_ptr > (_Thread_Executing->Start.stack + - _Thread_Executing->Start.Initial_stack.size) ) { - printk( "Blown interrupt stack at 0x%x\n", stack_ptr ); - } -#endif - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_low; - } -#endif - - _ISR_Nest_level++; - - /* leave it to the ISR to decide if they get reenabled */ - /* _CPU_ISR_Enable( level ); */ - - /* call isp */ - if ( _ISR_Vector_table[ vector] ) - (*_ISR_Vector_table[ vector ])( - vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 ); - - _CPU_ISR_Disable( level ); - - _ISR_Nest_level--; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; -#endif - - _Thread_Dispatch_disable_level--; - - _CPU_ISR_Enable( level ); - - if ( _ISR_Nest_level ) - return; - - if ( _Thread_Dispatch_disable_level ) { - _ISR_Signals_to_thread_executing = FALSE; - return; - } - - if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) { - _ISR_Signals_to_thread_executing = FALSE; - _Thread_Dispatch(); - } -} diff --git a/cpukit/score/cpu/c4x/preinstall.am b/cpukit/score/cpu/c4x/preinstall.am deleted file mode 100644 index efbebe60e7..0000000000 --- a/cpukit/score/cpu/c4x/preinstall.am +++ /dev/null @@ -1,54 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/tic4x - @: > $(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/tic4x/c4xio.h: rtems/tic4x/c4xio.h $(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/tic4x/c4xio.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/tic4x/c4xio.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/c4x.h: rtems/score/c4x.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/c4x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/c4x.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - diff --git a/cpukit/score/cpu/c4x/rtems/asm.h b/cpukit/score/cpu/c4x/rtems/asm.h deleted file mode 100644 index d99484e96c..0000000000 --- a/cpukit/score/cpu/c4x/rtems/asm.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/c4x/rtems/score/c4x.h b/cpukit/score/cpu/c4x/rtems/score/c4x.h deleted file mode 100644 index 13559b29e5..0000000000 --- a/cpukit/score/cpu/c4x/rtems/score/c4x.h +++ /dev/null @@ -1,367 +0,0 @@ -/** - * @file rtems/score/c4x.h - */ - -/* - * This file is an example (i.e. "no CPU") of the file which is - * created for each CPU family port of RTEMS. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - * - */ - -#ifndef _RTEMS_SCORE_C4X_H -#define _RTEMS_SCORE_C4X_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(_C30) -#define CPU_MODEL_NAME "C30" - -#elif defined(_C31) -#define CPU_MODEL_NAME "C31" - -#elif defined(_C32) -#define CPU_MODEL_NAME "C32" - -#elif defined(_C33) -#define CPU_MODEL_NAME "C33" - -#elif defined(_C40) -#define CPU_MODEL_NAME "C40" - -#elif defined(_C44) -#define CPU_MODEL_NAME "C44" - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Texas Instruments C3x/C4x" - -/* - * This port is a little unusual in that even though there are "floating - * point registers", the notion of floating point is very inherent to - * applications. In addition, the calling conventions require that - * only a few extended registers be preserved across subroutine calls. - * The overhead of including these few registers in the basic - * context is small compared to the overhead of managing the notion - * of separate floating point contexts. So we decided to pretend that - * there is no FPU on the C3x or C4x. - */ - -#define C4X_HAS_FPU 0 - -/* - * Routines to manipulate the bits in the Status Word (ST). - */ - -#define C4X_ST_C 0x0001 -#define C4X_ST_V 0x0002 -#define C4X_ST_Z 0x0004 -#define C4X_ST_N 0x0008 -#define C4X_ST_UF 0x0010 -#define C4X_ST_LV 0x0020 -#define C4X_ST_LUF 0x0040 -#define C4X_ST_OVM 0x0080 -#define C4X_ST_RM 0x0100 -#define C4X_ST_CF 0x0400 -#define C4X_ST_CE 0x0800 -#define C4X_ST_CC 0x1000 -#define C4X_ST_GIE 0x2000 - -#ifndef _TMS320C40 -#define C3X_IE_INTERRUPT_MASK_BITS 0xffff -#define C3x_IE_INTERRUPTS_ALL_ENABLED 0x0000 -#define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff -#endif - -#ifndef ASM - -/* - * A nop macro. - */ - -#define c4x_nop() \ - __asm__("nop"); - -/* - * Routines to set and clear individual bits in the ST (status word). - * - * cpu_st_bit_clear - clear bit in ST - * cpu_st_bit_set - set bit in ST - * cpu_st_get - obtain entire ST - */ - -#ifdef _TMS320C40 -#define c4x_gie_nop() -#else -#define c4x_gie_nop() { c4x_nop(); c4x_nop(); } -#endif - -#define cpu_st_bit_clear(_st_bit) \ - do { \ - __asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \ - c4x_gie_nop(); \ - } while (0) - -#define cpu_st_bit_set(_st_bit) \ - do { \ - __asm__("or %0,st" : : "g" (_st_bit) : "cc"); \ - c4x_gie_nop(); \ - } while (0) - -static inline unsigned int cpu_st_get(void) -{ - register unsigned int st_value; - __asm__("ldi st, %0" : "=r" (st_value)); - return st_value; -} - -/* - * Routines to manipulate the Global Interrupt Enable (GIE) bit in - * the Status Word (ST). - * - * c4x_global_interrupts_get - returns current GIE setting - * c4x_global_interrupts_disable - disables global interrupts - * c4x_global_interrupts_enable - enables global interrupts - * c4x_global_interrupts_restore - restores GIE to pre-disable state - * c4x_global_interrupts_flash - temporarily enable global interrupts - */ - -#define c4x_global_interrupts_get() \ - (cpu_st_get() & C4X_ST_GIE) - -#define c4x_global_interrupts_disable() \ - cpu_st_bit_clear(C4X_ST_GIE) - -#define c4x_global_interrupts_enable() \ - cpu_st_bit_set(C4X_ST_GIE) - -#define c4x_global_interrupts_restore(_old_level) \ - cpu_st_bit_set(_old_level) - -#define c4x_global_interrupts_flash(_old_level) \ - do { \ - cpu_st_bit_set(_old_level); \ - cpu_st_bit_clear(C4X_ST_GIE); \ - } while (0) - -#ifndef _TMS320C40 - -/* - * Routines to set and get the IF register - * - * c3x_get_if - obtains IF register - * c3x_set_if - sets IF register - */ - -static inline unsigned int c3x_get_if(void) -{ - register unsigned int _if_value; - - __asm__( "ldi if, %0" : "=r" (_if_value) ); - return _if_value; -} - -static inline void c3x_set_if(unsigned int _if_value) -{ - __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); -} - -/* - * Routines to set and get the IE register - * - * c3x_get_ie - obtains IE register - * c3x_set_ie - sets IE register - */ - -static inline unsigned int c3x_get_ie(void) -{ - register unsigned int _ie_value; - - __asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) ); - return _ie_value; -} - -static inline void c3x_set_ie(unsigned int _ie_value) -{ - __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); -} - -/* - * Routines to manipulates the mask portion of the IE register. - * - * c3x_ie_mask_all - returns previous IE mask - * c3x_ie_mask_restore - restores previous IE mask - * c3x_ie_mask_flash - temporarily restores previous IE mask - * c3x_ie_mask_set - sets a specific set of the IE mask - */ - -#define c3x_ie_mask_all( _isr_cookie ) \ - do { \ - __asm__("ldi ie,%0\n" \ - "\tandn 0ffffh, ie" \ - : "=r" (_isr_cookie): : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_restore( _isr_cookie ) \ - do { \ - __asm__("or %0, ie" \ - : : "g" (_isr_cookie) : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_flash( _isr_cookie ) \ - do { \ - __asm__("or %0, ie\n" \ - "\tandn 0ffffh, ie" \ - : : "g" (_isr_cookie) : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_set( _new_mask ) \ - do { unsigned int _ie_mask; \ - unsigned int _ie_value; \ - \ - if ( _new_mask == 0 ) _ie_mask = 0; \ - else _ie_mask = 0xffff; \ - _ie_value = c3x_get_ie(); \ - _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \ - _ie_value |= _ie_mask; \ - c3x_set_ie(_ie_value); \ - } while (0) -#endif -/* end of C3x specific interrupt flag routines */ - -/* - * This is a section of C4x specific interrupt flag management routines. - */ - -#ifdef _TMS320C40 - -/* - * Routines to set and get the IIF register - * - * c4x_get_iif - obtains IIF register - * c4x_set_iif - sets IIF register - */ - -static inline unsigned int c4x_get_iif(void) -{ - register unsigned int _iif_value; - - __asm__( "ldi iif, %0" : "=r" (_iif_value) ); - return _iif_value; -} - -static inline void c4x_set_iif(unsigned int _iif_value) -{ - __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); -} - -/* - * Routines to set and get the IIE register - * - * c4x_get_iie - obtains IIE register - * c4x_set_iie - sets IIE register - */ - -static inline unsigned int c4x_get_iie(void) -{ - register unsigned int _iie_value; - - __asm__( "ldi iie, %0" : "=r" (_iie_value) ); - return _iie_value; -} - -static inline void c4x_set_iie(unsigned int _iie_value) -{ - __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); -} - -/* - * Routines to manipulates the mask portion of the IIE register. - * - * c4x_ie_mask_all - returns previous IIE mask - * c4x_ie_mask_restore - restores previous IIE mask - * c4x_ie_mask_flash - temporarily restores previous IIE mask - * c4x_ie_mask_set - sets a specific set of the IIE mask - */ - -#if 0 -#warning "C4x IIE masking routines not implemented." -#define c4x_iie_mask_all( _isr_cookie ) -#define c4x_iie_mask_restore( _isr_cookie ) -#define c4x_iie_mask_flash( _isr_cookie ) -#define c4x_iie_mask_set( _new_mask ) -#endif - -#endif -/* end of C4x specific interrupt flag routines */ - -/* - * Routines to access the Interrupt Trap Table Pointer - * - * c4x_get_ittp - get ITTP - * c4x_set_ittp - set ITTP - */ - -static inline void * c4x_get_ittp(void) -{ - register unsigned int _if_value; - - __asm__( "ldi if, %0" : "=r" (_if_value) ); - return (void *)((_if_value & 0xffff0000) >> 8); -} - -static inline void c4x_set_ittp(void *_ittp_value) -{ - unsigned int _if_value; - unsigned int _ittp_field; - -#ifdef _TMS320C40 - _if_value = c4x_get_iif(); -#else - _if_value = c3x_get_if(); -#endif - _if_value &= 0xffff; - _ittp_field = (((unsigned int) _ittp_value) >> 8); - _if_value |= _ittp_field << 16 ; -#ifdef _TMS320C40 - c4x_set_iif( _if_value ); -#else - c3x_set_if( _if_value ); -#endif -} - -#endif /* ifndef ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_C4X_H */ diff --git a/cpukit/score/cpu/c4x/rtems/score/cpu.h b/cpukit/score/cpu/c4x/rtems/score/cpu.h deleted file mode 100644 index fb30a04b5d..0000000000 --- a/cpukit/score/cpu/c4x/rtems/score/cpu.h +++ /dev/null @@ -1,1225 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the C4x - * processor. - * - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include /* pick up machine definitions */ -#ifndef ASM -#include -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * C4x Specific Information: - * - * We might as well try to inline this code until there is a - * code space problem. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * C4x Specific Information: - * - * We might as well unroll this loop until there is a reason not to do so. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * C4x Specific Information: - * - * Initial investigation indicates a software managed stack will be needed. - * But the implementation does not currently include support for one. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * C4x Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * C4x Specific Information: - * - * XXXanswer - * - * Initial investigation indicates a software managed stack will be needed. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * C4x Specific Information: - * - * XXXanswer - * - * Until we know what to do with the memory, we should not allocated it. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * C4x Specific Information: - * - * XXXanswer - * - * The interrupt code will have to be written before this is answered - * but the answer should be yes. - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "C4X_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * C4x Specific Information: - * - * See c4x.h for more details but the bottom line is that the - * few extended registers required to be preserved across subroutines - * calls are considered part of the integer context. This eliminates - * overhead. - * - * The C4X_HAS_FPU refers to the extended precision registers R0-R7 - * (plus R8-R11 on some models). - * - * XXX check that we even need to have the context area pointer in - * the TCB in this case. - */ - -#if ( C4X_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * C4x Specific Information: - * - * There is no known reason to make all tasks include the extended - * precision registers (i.e. floating point context). - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * C4x Specific Information: - * - * There is no known reason to make the IDLE task floating point and - * no point in wasting the memory or increasing the context switch - * time for the IDLE task. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * C4x Specific Information: - * - * There is no reason to avoid the deferred FP switch logic on this - * CPU family. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * C4x Specific Information: - * - * There is currently no reason to avoid using the generic implementation. - * In the future, a C4x specific IDLE thread body may be added to take - * advantage of low power modes. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * C4x Specific Information: - * - * The system stack grows from low to high memory. - * - * C4x Specific Information: - * - * This setting was derived from the discussion of stack management - * in section 6.1 (p. 6-29) System and User Stack Management of the - * TMS32C3x User's Guide (rev L, July 1997) which states: "A push - * performs a preincrement, and a pop performs a postdecrement of the - * system-stack pointer." There are instructions for making "a stack" - * run from high to low memory but this appears to be the exception. - */ - -#define CPU_STACK_GROWS_UP TRUE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * C4x Specific Information: - * - * The C4x is word oriented and there should be no alignment issues. - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * C4x Specific Information: - * - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * C4x Specific Information: - * - * Currently we are only supporting interrupt levels 0 (all on) and - * 1 (all off). Levels 2-255 COULD be looked up in a user provided - * table that gives GIE and IE Mask settings. But this is not the - * case today. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000FF - -/* - * Processor defined structures required for cpukit/score. - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * C4x Specific Information: - * - * From email with Michael Hayes: - * > > But what are the rules for what is passed in what registers? - * - * Args are passed in the following registers (in order): - * - * AR2, R2, R3, RC, RS, RE - * - * However, the first and second floating point values are always in R2 - * and R3 (and all other floats are on the stack). Structs are always - * passed on the stack. If the last argument is an ellipsis, the - * previous argument is passed on the stack so that its address can be - * taken for the stdargs macros. - * - * > > What is assumed to be preserved across calls? - * - * AR3, AR4, AR5, AR6, AR7 - * R4, R5, R8 (using STI/LDI) - * R6, R7 (using STF/LDF) - * - * > > What is assumed to be scratch registers? - * - * R0, R1, R2, R3, AR0, AR1, AR2, IR0, IR1, BK, RS, RE, RC, R9, R10, R11 - * - * Based on this information, the task specific context is quite small - * but the interrupt context is much larger. In fact, it could - * easily be argued that there is no point in distinguishing between - * integer and floating point contexts on the Cxx since there is - * so little context involved. So that is the decision made. - * - * Not Mentioned in list: DP - * - * Assumed to be global resources: - * - * C3X: IE, IF, and IOF - * C4X: DIE, IIF, and IIF - */ - - -typedef struct { - unsigned int st; - unsigned int ar3; - unsigned int ar4; - unsigned int ar5; - unsigned int ar6; - unsigned int ar7; - unsigned int r4_sti; /* other part of register is in interrupt context */ - unsigned int r5_sti; /* other part of register is in interrupt context */ - unsigned int r6_stf; /* other part of register is in interrupt context */ - unsigned int r7_stf; /* other part of register is in interrupt context */ -#ifdef _TMS320C40 - unsigned int r8_sti; /* other part of register is in interrupt context */ -#endif - unsigned int sp; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef struct { -} Context_Control_fp; - -/* - * This is the order the interrupt entry code pushes the registers. - */ - -typedef struct { - void *interrupted; - unsigned int st; - unsigned int ar2; /* because the vector numbers goes here */ - unsigned int ar0; - unsigned int ar1; - unsigned int dp; - unsigned int ir0; - unsigned int ir1; - unsigned int rs; - unsigned int re; - unsigned int rc; - unsigned int bk; - unsigned int r0_sti; - unsigned int r0_stf; - unsigned int r1_sti; - unsigned int r1_stf; - unsigned int r2_sti; - unsigned int r2_stf; - unsigned int r3_sti; - unsigned int r3_stf; - unsigned int r4_stf; /* other part of register is in basic context */ - unsigned int r5_stf; /* other part of register is in basic context */ - unsigned int r6_sti; /* other part of register is in basic context */ - unsigned int r7_sti; /* other part of register is in basic context */ - -#ifdef _TMS320C40 - unsigned int r8_sti; /* other part of register is in basic context */ - unsigned int r9_sti; - unsigned int r9_stf; - unsigned int r10_sti; - unsigned int r10_stf; - unsigned int r11_sti; - unsigned int r11_stf; -#endif - -} CPU_Interrupt_frame; - -/* - * Macros to access C4X specific additions to the CPU Table - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -#if 0 -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * C4x Specific Information: - * - * Unused - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * C4x Specific Information: - * - * XXXanswer - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * C4x Specific Information: - * - * If we decide to have a separate floating point context, then - * the answer is the size of the data structure. Otherwise, we - * need to define it as 0 to let upper level configuration work. - */ - -#if ( C4X_HAS_FPU == 1 ) -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -#else -#define CPU_CONTEXT_FP_SIZE 0 -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * C4x Specific Information: - * - * Based on the information provided in section 7.6.1 (p. 7-26) - * titled "TMS320C30 and TMS320C31 Interrupt Vector Table" and section - * 7.6.2 "TMS320C32 Interrupt Vector Table" of the TMS32C3x User's - * Guide (rev L, July 1997), vectors are numbered 0x00 - 0x3F. Thus - * there are 0x40 or 64 vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 0x40 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_STACK_MINIMUM_SIZE (1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * C4x Specific Information: - * - * XXXanswer - * As best I can tell, there are no restrictions since this is a word - * -- not byte -- oriented archtiecture. - */ - -#define CPU_ALIGNMENT 0 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - * - * A CPU_HEAP_ALIGNMENT of 2 comes close to disabling all the rounding - * while still ensuring that the least significant bit of the front - * and back flags can be used as the used bit -- not part of the size. - */ - -#define CPU_HEAP_ALIGNMENT 2 - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - * I think a CPU_PARTITION_ALIGNMENT of 1 will effectively disable all - * the rounding. - */ - -#define CPU_PARTITION_ALIGNMENT 1 - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - * - * C4x Specific Information: - * - * These macros disable interrupts using the GIE (global interrupts enable) - * bit in the status word. - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = c4x_global_interrupts_get(); \ - c4x_global_interrupts_disable(); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - c4x_global_interrupts_restore( _isr_cookie ) - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - c4x_global_interrupts_flash( _isr_cookie ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * C4x Specific Information: - * - * The C4x port probably needs to allow the BSP to define - * a mask table for all values 0-255. For now, 0 is global - * interrupts enabled and and non-zero is global interrupts - * disabled. In the future, values 1-254 could be defined as - * specific combinations of the global interrupt enabled and the IE mask. - * - * The logic for setting the mask field is something like this: - * _ie_value = c4x_get_ie(); - * _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; - * _ie_value |= _ie_mask; - * c4x_set_ie(_ie_value); - * - * NOTE: If this is implemented, then the context of each task - * must be extended to include the IE register. - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - do { \ - if ( _new_level == 0 ) c4x_global_interrupts_enable(); \ - else c4x_global_interrupts_disable(); \ - } while (0) - -/* if GIE = 1, then logical level is 0. */ -#define _CPU_ISR_Get_level() \ - (c4x_global_interrupts_get() ? 0 : 1) - - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#if ( C4X_HAS_FPU == 1 ) -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -#if ( C4X_HAS_FPU == 1 ) -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define _CPU_Fatal_halt( _error ) \ - do { \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * C4x Specific Information: - * - * There does not appear to be a simple way to do this on this - * processor family that is better than the generic algorithm. - * Almost certainly, a hand-optimized assembly version of the - * generic algorithm could be written although it is not - * worth the development effort at this time. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - do { \ - (_output) = 0; /* do something to prevent warnings */ \ - } while (0) - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * - * C4x Specific Information: - * - * XXXanswer - * is TRUE. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1) -void *_CPU_Thread_Idle_body( uint32_t ); -#endif - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#if ( C4X_HAS_FPU == 1 ) -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#if ( C4X_HAS_FPU == 1 ) -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * C4x Specific Information: - * - * XXXanswer - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/c4x/rtems/score/cpu_asm.h b/cpukit/score/cpu/c4x/rtems/score/cpu_asm.h deleted file mode 100644 index a509b36ae6..0000000000 --- a/cpukit/score/cpu/c4x/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file rtems/score/cpu_asm.h - */ - -/* - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/c4x/rtems/score/types.h b/cpukit/score/cpu/c4x/rtems/score/types.h deleted file mode 100644 index a2f13d782c..0000000000 --- a/cpukit/score/cpu/c4x/rtems/score/types.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file rtems/score/types.h - */ - -/* - * This include file contains type definitions pertaining to the - * Texas Instruments C4x processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#ifndef ASM - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef uint_least16_t Priority_Bit_map_control; -typedef void c4x_isr; -typedef void ( *c4x_isr_entry )( void ); - -#ifdef RTEMS_DEPRECATED_TYPES -typedef bool boolean; /* Boolean value */ -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h b/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h deleted file mode 100644 index 87a20ee91d..0000000000 --- a/cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * C4X IO Information - * - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -#ifndef _RTEMS_TIC4X_C4XIO_H -#define _RTEMS_TIC4X_C4XIO_H - -/* - * Address defines - */ - -#ifdef _TMS320C40 -#define C4X_TIMER_0 ((struct c4x_timer*)0x100020) -#else -#define C4X_TIMER_0 ((struct c4x_timer*)0x808020) -#define C4X_TIMER_1 ((struct c4x_timer*)0x808030) -#endif - -/* XXX how portable */ - -/* C32 Internal Control Registers */ -#define C4X_STRB0_REG 0x808064 -#define C4X_STRB1_REG 0x808068 -#define C4X_IOSTRB_REG 0x808060 - -/* C32 Internal RAM Locations */ -/* XXX how long */ -#define C4X_RAM_BLK_0 0x87fe00 -#define C4X_RAM_BLK_1 0x87ff00 - -/* - * Data Structures to Overlay the Peripherals on the CPU - */ - -struct c4x_timer { - volatile int tcontrol; - volatile int r1[3]; - volatile int tcounter; - volatile int r2[3]; - volatile int tperiod; -}; - - - - -/* - * Timer Support Routines - * - * The following section of C4x timer code is based on C40 specific - * timer code from Ran Cabell . The - * only C3x/C4x difference spotted was the address of the timer. - * The names have been changed to be more RTEMS like. - */ - -#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol) - -#define c4x_timer_set_control( _timer, _value ) \ - do { \ - (volatile int)(_timer->tcontrol) = _value; \ - } while (0); - -#define c4x_timer_start( _timer ) \ - c4x_timer_set_control(_timer, 0x02c1 ) - -#define c4x_timer_stop( _timer ) _timer->tcontrol = 0 - -#define c4x_timer_get_counter( _timer ) (volatile int)(_timer->tcounter) - -#define c4x_timer_set_counter( _timer, _value ) \ - do { \ - (volatile int)(_timer->tcounter) = _value; \ - } while (0); - -#define c4x_timer_get_period( _timer ) (volatile int)(_timer->tperiod) - -#define c4x_timer_set_period( _timer, _value ) \ - do { \ - (volatile int)(_timer->tperiod) = _value; \ - } while (0); - -/* - * IO Flags - * - * NOTE: iof on c3x, iiof on c4x - */ - -#ifdef _TMS320C40 - -#else - -static inline uint32_t c3x_get_iof( void ) -{ - register uint32_t iof_value; - - __asm__ volatile ("ldi iof, %0" : "=r" (iof_value)); - return iof_value; -} - -static inline void c3x_set_iof( uint32_t value ) -{ - __asm__ volatile ("ldi %0,iof" : : "g" (value) : "iof", "cc"); -} - -#endif - - -#endif -/* end if include file */ -- cgit v1.2.3