From ddbc3f8d83678313ca61d2936e6efd50b3e044b0 Mon Sep 17 00:00:00 2001 From: Daniel Cederman Date: Fri, 11 Jul 2014 16:37:56 +0200 Subject: score: Add SMP support to the cache manager Adds functions that allows the user to specify which cores that should perform the cache operation. SMP messages are sent to all the specified cores and the caller waits until all cores have acknowledged that they have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is defined the instruction cache invalidation function will perform the operation on all cores using the previous method. --- cpukit/score/include/rtems/score/smpimpl.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'cpukit/score/include') diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index cbc64280de..dca8a6bec8 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -21,6 +21,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -50,6 +51,13 @@ extern "C" { */ #define SMP_MESSAGE_TEST 0x2UL +/** + * @brief SMP message to request a cache manager invocation. + * + * @see _SMP_Send_message(). + */ +#define SMP_MESSAGE_CACHE_MANAGER 0x4UL + /** * @brief SMP fatal codes. */ @@ -126,6 +134,12 @@ static inline void _SMP_Set_test_message_handler( _SMP_Test_message_handler = handler; } +/** + * @brief Handles cache invalidation/flush requests from a remote processor. + * + */ +void _SMP_Cache_manager_message_handler( void ); + /** * @brief Interrupt handler for inter-processor interrupts. */ @@ -148,6 +162,11 @@ static inline void _SMP_Inter_processor_interrupt_handler( void ) if ( ( message & SMP_MESSAGE_TEST ) != 0 ) { ( *_SMP_Test_message_handler )( cpu_self ); } + + if ( ( message & SMP_MESSAGE_CACHE_MANAGER ) != 0 ) { + _SMP_Cache_manager_message_handler(); + } + } } -- cgit v1.2.3