From 4b04cb61552dbaa1a42a64e2f7b823708127e488 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 18 May 2016 08:03:05 +0200 Subject: score: Rename _ISR_Disable_without_giant() Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename _ISR_Enable_without_giant() into _ISR_Local_enable(). This is a preparation to remove the Giant lock. Update #2555. --- cpukit/score/include/rtems/score/isrlevel.h | 4 ++-- cpukit/score/include/rtems/score/isrlock.h | 4 ++-- cpukit/score/include/rtems/score/mrspimpl.h | 8 ++++---- cpukit/score/include/rtems/score/percpu.h | 12 ++++++------ cpukit/score/include/rtems/score/smplock.h | 4 ++-- cpukit/score/include/rtems/score/threaddispatch.h | 8 ++++---- cpukit/score/include/rtems/score/threadimpl.h | 4 ++-- 7 files changed, 22 insertions(+), 22 deletions(-) (limited to 'cpukit/score/include/rtems') diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h index 2823df7d27..cf8712a967 100644 --- a/cpukit/score/include/rtems/score/isrlevel.h +++ b/cpukit/score/include/rtems/score/isrlevel.h @@ -136,13 +136,13 @@ typedef uint32_t ISR_Level; RTEMS_COMPILER_MEMORY_BARRIER(); \ } while (0) -#define _ISR_Disable_without_giant( _level ) \ +#define _ISR_Local_disable( _level ) \ do { \ _CPU_ISR_Disable( _level ); \ RTEMS_COMPILER_MEMORY_BARRIER(); \ } while (0) -#define _ISR_Enable_without_giant( _level ) \ +#define _ISR_Local_enable( _level ) \ do { \ RTEMS_COMPILER_MEMORY_BARRIER(); \ _CPU_ISR_Enable( _level ); \ diff --git a/cpukit/score/include/rtems/score/isrlock.h b/cpukit/score/include/rtems/score/isrlock.h index f87f5550fc..2af75c94cd 100644 --- a/cpukit/score/include/rtems/score/isrlock.h +++ b/cpukit/score/include/rtems/score/isrlock.h @@ -351,7 +351,7 @@ typedef struct { #if defined( RTEMS_SMP ) #define _ISR_lock_ISR_disable( _context ) \ do { \ - _ISR_Disable_without_giant( ( _context )->Lock_context.isr_level ); \ + _ISR_Local_disable( ( _context )->Lock_context.isr_level ); \ _ISR_lock_ISR_disable_profile( _context ) \ } while ( 0 ) #else @@ -374,7 +374,7 @@ typedef struct { */ #if defined( RTEMS_SMP ) #define _ISR_lock_ISR_enable( _context ) \ - _ISR_Enable_without_giant( ( _context )->Lock_context.isr_level ) + _ISR_Local_enable( ( _context )->Lock_context.isr_level ) #else #define _ISR_lock_ISR_enable( _context ) \ _ISR_Enable( ( _context )->isr_level ) diff --git a/cpukit/score/include/rtems/score/mrspimpl.h b/cpukit/score/include/rtems/score/mrspimpl.h index f2570eb7fc..d5cf55dcbf 100644 --- a/cpukit/score/include/rtems/score/mrspimpl.h +++ b/cpukit/score/include/rtems/score/mrspimpl.h @@ -251,9 +251,9 @@ RTEMS_INLINE_ROUTINE MRSP_Status _MRSP_Wait_for_ownership( if ( timeout > 0 ) { _Watchdog_Preinitialize( &rival.Watchdog, cpu_self ); _Watchdog_Initialize( &rival.Watchdog, _MRSP_Timeout ); - _ISR_Disable_without_giant( level ); + _ISR_Local_disable( level ); _Watchdog_Per_CPU_insert_relative( &rival.Watchdog, cpu_self, timeout ); - _ISR_Enable_without_giant( level ); + _ISR_Local_enable( level ); } life_state = _Thread_Set_life_protection( THREAD_LIFE_PROTECTED ); @@ -269,13 +269,13 @@ RTEMS_INLINE_ROUTINE MRSP_Status _MRSP_Wait_for_ownership( _Thread_Set_life_protection( life_state ); if ( timeout > 0 ) { - _ISR_Disable_without_giant( level ); + _ISR_Local_disable( level ); _Watchdog_Per_CPU_remove( &rival.Watchdog, cpu_self, &cpu_self->Watchdog.Header[ PER_CPU_WATCHDOG_RELATIVE ] ); - _ISR_Enable_without_giant( level ); + _ISR_Local_enable( level ); if ( status == MRSP_TIMEOUT ) { _MRSP_Restore_priority( executing, initial_priority ); diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h index a4a8ffbb24..fa0c289f31 100644 --- a/cpukit/score/include/rtems/score/percpu.h +++ b/cpukit/score/include/rtems/score/percpu.h @@ -493,7 +493,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; #if defined( RTEMS_SMP ) #define _Per_CPU_ISR_disable_and_acquire( cpu, isr_cookie ) \ do { \ - _ISR_Disable_without_giant( isr_cookie ); \ + _ISR_Local_disable( isr_cookie ); \ _Per_CPU_Acquire( cpu ); \ } while ( 0 ) #else @@ -508,7 +508,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; #define _Per_CPU_Release_and_ISR_enable( cpu, isr_cookie ) \ do { \ _Per_CPU_Release( cpu ); \ - _ISR_Enable_without_giant( isr_cookie ); \ + _ISR_Local_enable( isr_cookie ); \ } while ( 0 ) #else #define _Per_CPU_Release_and_ISR_enable( cpu, isr_cookie ) \ @@ -523,7 +523,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; do { \ uint32_t ncpus = _SMP_Get_processor_count(); \ uint32_t cpu; \ - _ISR_Disable_without_giant( isr_cookie ); \ + _ISR_Local_disable( isr_cookie ); \ for ( cpu = 0 ; cpu < ncpus ; ++cpu ) { \ _Per_CPU_Acquire( _Per_CPU_Get_by_index( cpu ) ); \ } \ @@ -541,7 +541,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; for ( cpu = 0 ; cpu < ncpus ; ++cpu ) { \ _Per_CPU_Release( _Per_CPU_Get_by_index( cpu ) ); \ } \ - _ISR_Enable_without_giant( isr_cookie ); \ + _ISR_Local_enable( isr_cookie ); \ } while ( 0 ) #else #define _Per_CPU_Release_all( isr_cookie ) \ @@ -709,13 +709,13 @@ RTEMS_INLINE_ROUTINE struct _Thread_Control *_Thread_Get_executing( void ) #if defined( RTEMS_SMP ) ISR_Level level; - _ISR_Disable_without_giant( level ); + _ISR_Local_disable( level ); #endif executing = _Thread_Executing; #if defined( RTEMS_SMP ) - _ISR_Enable_without_giant( level ); + _ISR_Local_enable( level ); #endif return executing; diff --git a/cpukit/score/include/rtems/score/smplock.h b/cpukit/score/include/rtems/score/smplock.h index 173df18754..eddbb32b15 100644 --- a/cpukit/score/include/rtems/score/smplock.h +++ b/cpukit/score/include/rtems/score/smplock.h @@ -251,7 +251,7 @@ static inline void _SMP_lock_ISR_disable_and_acquire( SMP_lock_Context *context ) { - _ISR_Disable_without_giant( context->isr_level ); + _ISR_Local_disable( context->isr_level ); _SMP_lock_Acquire( lock, context ); } @@ -274,7 +274,7 @@ static inline void _SMP_lock_Release_and_ISR_enable( ) { _SMP_lock_Release( lock, context ); - _ISR_Enable_without_giant( context->isr_level ); + _ISR_Local_enable( context->isr_level ); } #endif diff --git a/cpukit/score/include/rtems/score/threaddispatch.h b/cpukit/score/include/rtems/score/threaddispatch.h index b0dd64cf18..ac8855b76c 100644 --- a/cpukit/score/include/rtems/score/threaddispatch.h +++ b/cpukit/score/include/rtems/score/threaddispatch.h @@ -54,13 +54,13 @@ RTEMS_INLINE_ROUTINE bool _Thread_Dispatch_is_enabled(void) #if defined(RTEMS_SMP) ISR_Level level; - _ISR_Disable_without_giant( level ); + _ISR_Local_disable( level ); #endif enabled = _Thread_Dispatch_disable_level == 0; #if defined(RTEMS_SMP) - _ISR_Enable_without_giant( level ); + _ISR_Local_enable( level ); #endif return enabled; @@ -325,7 +325,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self ) if ( disable_level == 1 ) { ISR_Level level; - _ISR_Disable_without_giant( level ); + _ISR_Local_disable( level ); if ( cpu_self->dispatch_necessary ) { _Thread_Do_dispatch( cpu_self, level ); @@ -334,7 +334,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self ) _Profiling_Thread_dispatch_enable( cpu_self, 0 ); } - _ISR_Enable_without_giant( level ); + _ISR_Local_enable( level ); } else { cpu_self->thread_dispatch_disable_level = disable_level - 1; } diff --git a/cpukit/score/include/rtems/score/threadimpl.h b/cpukit/score/include/rtems/score/threadimpl.h index ad87c1d3ae..73f9c9a2a9 100644 --- a/cpukit/score/include/rtems/score/threadimpl.h +++ b/cpukit/score/include/rtems/score/threadimpl.h @@ -1381,7 +1381,7 @@ RTEMS_INLINE_ROUTINE bool _Thread_Wait_flags_try_change( #if !defined(RTEMS_SMP) ISR_Level level; - _ISR_Disable_without_giant( level ); + _ISR_Local_disable( level ); #endif success = _Thread_Wait_flags_try_change_critical( @@ -1391,7 +1391,7 @@ RTEMS_INLINE_ROUTINE bool _Thread_Wait_flags_try_change( ); #if !defined(RTEMS_SMP) - _ISR_Enable_without_giant( level ); + _ISR_Local_enable( level ); #endif return success; -- cgit v1.2.3