From 258ad71e9626c16f30b40e06c321326636c976ff Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 25 Sep 2015 14:34:24 +0200 Subject: SMP: Fix and optimize thread dispatching According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator. --- cpukit/score/include/rtems/score/smpimpl.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'cpukit/score/include/rtems/score/smpimpl.h') diff --git a/cpukit/score/include/rtems/score/smpimpl.h b/cpukit/score/include/rtems/score/smpimpl.h index 97c78b02b0..3167e82a82 100644 --- a/cpukit/score/include/rtems/score/smpimpl.h +++ b/cpukit/score/include/rtems/score/smpimpl.h @@ -146,6 +146,12 @@ static inline void _SMP_Inter_processor_interrupt_handler( void ) { Per_CPU_Control *cpu_self = _Per_CPU_Get(); + /* + * In the common case the inter-processor interrupt is issued to carry out a + * thread dispatch. + */ + cpu_self->dispatch_necessary = true; + if ( _Atomic_Load_ulong( &cpu_self->message, ATOMIC_ORDER_RELAXED ) != 0 ) { unsigned long message = _Atomic_Exchange_ulong( &cpu_self->message, -- cgit v1.2.3