From 2072dd242f269ca7d3d14b8f4e2830f15e85e555 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 11 Nov 2016 15:45:10 +0100 Subject: score: Add Per_CPU_Control::isr_dispatch_disable Update #2751. --- cpukit/score/include/rtems/score/percpu.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'cpukit/score/include/rtems/score/percpu.h') diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h index ae789b85f5..d2025c0ccf 100644 --- a/cpukit/score/include/rtems/score/percpu.h +++ b/cpukit/score/include/rtems/score/percpu.h @@ -289,6 +289,16 @@ typedef struct Per_CPU_Control { */ uint32_t isr_nest_level; + /** + * @brief Indicetes if an ISR thread dispatch is disabled. + * + * This flag is context switched with each thread. It indicates that this + * thread has an interrupt stack frame on its stack. By using this flag, we + * can avoid nesting more interrupt dispatching attempts on a previously + * interrupted thread's stack. + */ + uint32_t isr_dispatch_disable; + /** * @brief The thread dispatch critical section nesting counter which is used * to prevent context switches at inopportune moments. @@ -780,8 +790,10 @@ RTEMS_INLINE_ROUTINE struct _Thread_Control *_Thread_Get_executing( void ) */ #define PER_CPU_ISR_NEST_LEVEL \ PER_CPU_END_STACK -#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \ +#define PER_CPU_ISR_DISPATCH_DISABLE \ PER_CPU_ISR_NEST_LEVEL + 4 +#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \ + PER_CPU_ISR_DISPATCH_DISABLE + 4 #define PER_CPU_OFFSET_EXECUTING \ PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL + 4 #define PER_CPU_OFFSET_HEIR \ -- cgit v1.2.3