From f8ad6c6f7f8b591e54db77b1fae81ab5e143f8e3 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 2 Aug 2013 14:12:55 +0200 Subject: sparc: Make _CPU_ISR_Dispatch_disable per-CPU This variable must be available for each processor in the system. --- cpukit/score/cpu/sparc/cpu.c | 14 +++++++------- cpukit/score/cpu/sparc/rtems/score/cpu.h | 24 ++++++++++++++---------- 2 files changed, 21 insertions(+), 17 deletions(-) (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index baa15c0cbb..1865a21ee8 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -19,8 +19,15 @@ #include #include +#include #include +RTEMS_STATIC_ASSERT( + offsetof( Per_CPU_Control, cpu_per_cpu.isr_dispatch_disable) + == SPARC_PER_CPU_ISR_DISPATCH_DISABLE, + SPARC_PER_CPU_ISR_DISPATCH_DISABLE +); + /* * This initializes the set of opcodes placed in each trap * table entry. The routine which installs a handler is responsible @@ -65,13 +72,6 @@ void _CPU_Initialize(void) pointer = &_CPU_Null_fp_context; _CPU_Context_save_fp( &pointer ); #endif - - /* - * Since no tasks have been created yet and no interrupts have occurred, - * there is no way that the currently executing thread can have an - * _ISR_Dispatch stack frame on its stack. - */ - _CPU_ISR_Dispatch_disable = 0; } uint32_t _CPU_ISR_Get_level( void ) diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 61f041005f..690ddcf90c 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -357,7 +357,13 @@ typedef struct { /** This defines the size of the minimum stack frame. */ #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 -#define CPU_PER_CPU_CONTROL_SIZE 0 +#define CPU_PER_CPU_CONTROL_SIZE 4 + +/** + * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field + * relative to the Per_CPU_Control begin. + */ +#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 /** * @defgroup Contexts SPARC Context Structures @@ -383,7 +389,13 @@ typedef struct { #ifndef ASM typedef struct { - /* There is no CPU specific per-CPU state */ + /** + * This flag is context switched with each thread. It indicates + * that THIS thread has an _ISR_Dispatch stack frame on its stack. + * By using this flag, we can avoid nesting more interrupt dispatching + * attempts on a previously interrupted thread's stack. + */ + uint32_t isr_dispatch_disable; } CPU_Per_CPU_control; /** @@ -768,14 +780,6 @@ typedef struct { */ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; -/** - * This flag is context switched with each thread. It indicates - * that THIS thread has an _ISR_Dispatch stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ -SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable; - /** * The following type defines an entry in the SPARC's trap table. * -- cgit v1.2.3