From cf1f72ea339287cf6f780b2e34b8092ce08da6b0 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 13 Jun 2000 21:53:38 +0000 Subject: Moved i386 and m68k cache management code to libcpu. Everything now is an implementation of the prototypes in rtems/rtems/cache.h. The libcpu/i386/wrapup directory is no longer needed. The PowerPC needs this done to it. --- cpukit/score/cpu/i386/rtems/score/i386.h | 95 -------------- cpukit/score/cpu/m68k/rtems/score/m68k.h | 211 ------------------------------- 2 files changed, 306 deletions(-) (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/i386/rtems/score/i386.h b/cpukit/score/cpu/i386/rtems/score/i386.h index ca1af66fff..bc486da473 100644 --- a/cpukit/score/cpu/i386/rtems/score/i386.h +++ b/cpukit/score/cpu/i386/rtems/score/i386.h @@ -185,101 +185,6 @@ static inline void i386_set_cr3(unsigned int segment) asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); } -/* - * Disable the entire cache - */ -void _CPU_disable_cache() { - cr0 regCr0; - - regCr0.i = i386_get_cr0(); - regCr0.cr0.page_level_cache_disable = 1; - regCr0.cr0.no_write_through = 1; - i386_set_cr0( regCr0.i ); - rtems_flush_entire_data_cache(); -} - -/* - * Enable the entire cache - */ -static inline void _CPU_enable_cache() { - cr0 regCr0; - - regCr0.i = i386_get_cr0(); - regCr0.cr0.page_level_cache_disable = 0; - regCr0.cr0.no_write_through = 0; - i386_set_cr0( regCr0.i ); - /*rtems_flush_entire_data_cache();*/ -} - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for - * each CPU. The routines below should be implemented per CPU, - * to accomodate the capabilities of each. - */ - -/* FIXME: I don't belong here. */ -#define I386_CACHE_ALIGNMENT 16 - -#if defined(I386_CACHE_ALIGNMENT) -#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT - -static inline void _CPU_flush_1_data_cache_line (const void * d_addr) {} -static inline void _CPU_invalidate_1_data_cache_line (const void * d_addr) {} -static inline void _CPU_freeze_data_cache (void) {} -static inline void _CPU_unfreeze_data_cache (void) {} -static inline void _CPU_invalidate_1_inst_cache_line const void * d_addr() {} -static inline void _CPU_freeze_inst_cache (void) {} -static inline void _CPU_unfreeze_inst_cache (void) {} - -static inline void _CPU_flush_entire_data_cache ( - const void * d_addr ) -{ - asm ("wbinvd"); -} -static inline void _CPU_invalidate_entire_data_cache ( - const void * d_addr ) -{ - asm ("invd"); -} - -static inline void _CPU_enable_data_cache ( - void ) -{ - _CPU_enable_cache(); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - _CPU_disable_cache(); -} - -static inline void _CPU_invalidate_entire_inst_cache ( - const void * i_addr ) -{ - asm ("invd"); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - _CPU_enable_cache(); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - _CPU_disable_cache(); -} -#endif - - /* routines */ /* diff --git a/cpukit/score/cpu/m68k/rtems/score/m68k.h b/cpukit/score/cpu/m68k/rtems/score/m68k.h index c38a9a13ed..bd8ec20475 100644 --- a/cpukit/score/cpu/m68k/rtems/score/m68k.h +++ b/cpukit/score/cpu/m68k/rtems/score/m68k.h @@ -373,217 +373,6 @@ static inline void * _CPU_virtual_to_physical ( } -/* - * Since the cacr is common to all mc680x0, provide macros - * for masking values in that register. - */ - -/* - * Used to clear bits in the cacr. - */ -#define _CPU_CACR_AND(mask) \ - { \ - register unsigned long _value = mask; \ - register unsigned long _ctl = 0; \ - asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ - andl %2, %0; /* and with _val */ \ - movec %1, %%cacr" /* write the cacr */ \ - : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ - } - - -/* - * Used to set bits in the cacr. - */ -#define _CPU_CACR_OR(mask) \ - { \ - register unsigned long _value = mask; \ - register unsigned long _ctl = 0; \ - asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ - orl %2, %0; /* or with _val */ \ - movec %1, %%cacr" /* write the cacr */ \ - : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ - } - - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - */ -#if ( defined(__mc68020__) || defined(__mc68030__) ) -#define M68K_INST_CACHE_ALIGNMENT 16 - -#if defined(__mc68030__) -#define M68K_DATA_CACHE_ALIGNMENT 16 - -/* Only the mc68030 has a data cache; it is writethrough only. */ - -static inline void _CPU_flush_1_data_cache_line ( const void * d_addr ) {} -static inline void _CPU_flush_entire_data_cache ( const void * d_addr ) {} - -static inline void _CPU_invalidate_1_data_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ - _CPU_CACR_OR(0x00000400); -} - -static inline void _CPU_invalidate_entire_data_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000800 ); -} - -static inline void _CPU_freeze_data_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000200 ); -} - -static inline void _CPU_unfreeze_data_cache ( - void ) -{ - _CPU_CACR_AND( 0xFFFFFDFF ); -} - -static inline void _CPU_enable_data_cache ( void ) -{ - _CPU_CACR_OR( 0x00000100 ); -} -static inline void _CPU_disable_data_cache ( void ) -{ - _CPU_CACR_AND( 0xFFFFFEFF ); -} -#endif - - -/* Both the 68020 and 68030 have instruction caches */ - -static inline void _CPU_invalidate_1_inst_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ - _CPU_CACR_OR( 0x00000004 ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000008 ); -} - -static inline void _CPU_freeze_inst_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000002); -} - -static inline void _CPU_unfreeze_inst_cache ( - void ) -{ - _CPU_CACR_AND( 0xFFFFFFFD ); -} - -static inline void _CPU_enable_inst_cache ( void ) -{ - _CPU_CACR_OR( 0x00000001 ); -} - -static inline void _CPU_disable_inst_cache ( void ) -{ - _CPU_CACR_AND( 0xFFFFFFFE ); -} - - -#elif ( defined(__mc68040__) || defined (__mc68060__) ) - -#define M68K_INST_CACHE_ALIGNMENT 16 -#define M68K_DATA_CACHE_ALIGNMENT 16 - -/* Cannot be frozen */ -static inline void _CPU_freeze_data_cache ( void ) {} -static inline void _CPU_unfreeze_data_cache ( void ) {} -static inline void _CPU_freeze_inst_cache ( void ) {} -static inline void _CPU_unfreeze_inst_cache ( void ) {} - -static inline void _CPU_flush_1_data_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); -} - -static inline void _CPU_invalidate_1_data_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); -} - -static inline void _CPU_flush_entire_data_cache ( - void ) -{ - asm volatile ( "cpusha %%dc" :: ); -} - -static inline void _CPU_invalidate_entire_data_cache ( - void ) -{ - asm volatile ( "cinva %%dc" :: ); -} - -static inline void _CPU_enable_data_cache ( - void ) -{ - _CPU_CACR_OR( 0x80000000 ); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - _CPU_CACR_AND( 0x7FFFFFFF ); -} - -static inline void _CPU_invalidate_1_inst_cache_line ( - const void * i_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); - asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( - void ) -{ - asm volatile ( "cinva %%ic" :: ); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - _CPU_CACR_OR( 0x00008000 ); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - _CPU_CACR_AND( 0xFFFF7FFF ); -} -#endif - - -#if defined(M68K_DATA_CACHE_ALIGNMENT) -#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT -#endif - -#if defined(M68K_INST_CACHE_ALIGNMENT) -#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT -#endif - - #endif /* !ASM */ #ifdef __cplusplus -- cgit v1.2.3