From ae7325bdc85e1dd39f039b66ba20ca681712dcc3 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 27 Oct 1999 17:25:53 +0000 Subject: rxgen960 now compiles -- may not link. --- cpukit/score/cpu/i960/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/i960/cpu.c b/cpukit/score/cpu/i960/cpu.c index 07ca05f69b..b1f29ff1bf 100644 --- a/cpukit/score/cpu/i960/cpu.c +++ b/cpukit/score/cpu/i960/cpu.c @@ -67,10 +67,10 @@ unsigned32 _CPU_ISR_Get_level( void ) */ #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) -#define _Is_vector_caching_enabled( _prcb ) \ +#define i960_vector_caching_enabled( _prcb ) \ ((_prcb)->control_tbl->icon & 0x2000) #elif defined(__i960RP__) -#define _Is_vector_caching_enabled( _prcb ) \ +#define i960_vector_caching_enabled( _prcb ) \ ((*((unsigned int *) ICON_ADDR)) & 0x2000) #endif @@ -93,7 +93,7 @@ void _CPU_ISR_install_raw_handler( prcb->intr_tbl[ vector + 1 ] = new_handler; - if ( _Is_vector_caching_enabled( prcb ) ) + if ( i960_vector_caching_enabled( prcb ) ) if ( (vector & 0xf) == 0x2 ) /* cacheable? */ cached_intr_tbl[ vector >> 4 ] = new_handler; } -- cgit v1.2.3