From a660e9dc47c522fe1a1b7f6e4af1795dbd6c20b1 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 8 Sep 2022 10:37:05 +0200 Subject: Do not use RTEMS_INLINE_ROUTINE Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935. --- cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 2 +- .../score/cpu/aarch64/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/arm/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/bfin/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/i386/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/i386/include/rtems/score/i386.h | 4 ++-- cpukit/score/cpu/lm32/include/rtems/score/cpu.h | 4 ++-- cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/m68k/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h | 10 +++++----- .../score/cpu/microblaze/include/rtems/score/cpu.h | 2 +- .../cpu/microblaze/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/mips/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/moxie/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/nios2/nios2-iic-irq.c | 2 +- cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h | 2 +- .../score/cpu/no_cpu/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/or1k/include/rtems/score/cpu.h | 4 ++-- cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/powerpc/include/rtems/score/cpu.h | 2 +- .../score/cpu/powerpc/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 4 ++-- cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/sh/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/sparc/include/libcpu/byteorder.h | 16 ++++++++-------- cpukit/score/cpu/sparc/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h | 6 +++--- cpukit/score/cpu/sparc64/include/rtems/score/cpu.h | 2 +- .../score/cpu/sparc64/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/v850/include/rtems/score/cpu.h | 2 +- cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h | 10 +++++----- cpukit/score/cpu/x86_64/include/rtems/score/cpu.h | 6 +++--- .../score/cpu/x86_64/include/rtems/score/cpu_asm.h | 20 ++++++++++---------- .../score/cpu/x86_64/include/rtems/score/cpuimpl.h | 10 +++++----- 41 files changed, 121 insertions(+), 121 deletions(-) (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h index da91ba96e1..399e0fc802 100644 --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h @@ -260,7 +260,7 @@ static inline void AArch64_interrupt_flash( uint64_t isr_cookie ) #define _CPU_ISR_Flash( _isr_cookie ) \ AArch64_interrupt_flash( _isr_cookie ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t isr_cookie ) +static inline bool _CPU_ISR_Is_enabled( uint64_t isr_cookie ) { return ( isr_cookie & AARCH64_PSTATE_I ) == 0; } diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h index 14836965ef..880ae7d9f7 100644 --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h @@ -152,17 +152,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".inst 0x0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h index 3715031d06..beb917a0b7 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h @@ -402,7 +402,7 @@ static inline void arm_interrupt_flash( uint32_t level ) #define _CPU_ISR_Flash( _isr_cookie ) \ arm_interrupt_flash( _isr_cookie ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { #if defined(ARM_MULTILIB_ARCH_V4) return ( level & 0x80 ) == 0; diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h index 4f20113b71..6e8230ce30 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h @@ -150,17 +150,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "udf" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h index f49f8928d3..72e6d14433 100644 --- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h @@ -355,7 +355,7 @@ typedef struct { : : "d"(_level) : "R0" ); \ } -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return level != 0; } diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h index 91e57da4a0..a03bc596ba 100644 --- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h @@ -37,29 +37,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h b/cpukit/score/cpu/i386/include/rtems/score/cpu.h index 715180fbd7..6aa97d309e 100644 --- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h @@ -428,7 +428,7 @@ extern Context_Control_fp _CPU_Null_fp_context; #define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) #endif -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & EFLAGS_INTR_ENABLE ) != 0; } diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h index 71f2679dde..4f99f64711 100644 --- a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h @@ -58,29 +58,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/i386/include/rtems/score/i386.h b/cpukit/score/cpu/i386/include/rtems/score/i386.h index 6b0ae5d6c2..7598204a64 100644 --- a/cpukit/score/cpu/i386/include/rtems/score/i386.h +++ b/cpukit/score/cpu/i386/include/rtems/score/i386.h @@ -223,7 +223,7 @@ void *i386_Physical_to_logical( * @param[in] offset used with \p segment to compute physical address * @retval physical address */ -RTEMS_INLINE_ROUTINE void *i386_Real_to_physical( +static inline void *i386_Real_to_physical( uint16_t segment, uint16_t offset) { @@ -577,7 +577,7 @@ extern segment_descriptors* i386_get_gdt_entry (uint16_t sgmnt_selector); * @param[in] gdt_entry pointer to entry from which base should be retrieved * @retval base address from GDT entry */ -RTEMS_INLINE_ROUTINE void* i386_base_gdt_entry (segment_descriptors* gdt_entry) +static inline void* i386_base_gdt_entry (segment_descriptors* gdt_entry) { return (void*)(gdt_entry->base_address_15_0 | (gdt_entry->base_address_23_16<<16) | diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h index 073e2da733..335d3407fe 100644 --- a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h @@ -456,7 +456,7 @@ extern Context_Control_fp _CPU_Null_fp_context; #define _CPU_ISR_Flash( _isr_cookie ) \ lm32_flash_interrupts( _isr_cookie ); -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & 0x0001 ) != 0; } @@ -612,7 +612,7 @@ void _CPU_Initialize(void); typedef void ( *CPU_ISR_raw_handler )( void ); -RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler( +static inline void _CPU_ISR_install_raw_handler( uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h index 24e8e5cb41..dce0cc6017 100644 --- a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h @@ -36,29 +36,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h index 2f9869a959..8fdcb8c15a 100644 --- a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h @@ -384,7 +384,7 @@ extern void* _VBR; #define _CPU_ISR_Flash( _level ) \ m68k_flash_interrupts( _level ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & 0x0700 ) == 0; } diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h index 5c7c35943a..b94c846bf2 100644 --- a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h @@ -56,29 +56,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "illegal" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h index f65c18dde3..1325962f7c 100644 --- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h @@ -264,7 +264,7 @@ void _CPU_ISR_Set_level( uint32_t level ); uint32_t _CPU_ISR_Get_level( void ); -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & MICROBLAZE_MSR_IE ) != 0; } diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h index e4f0303ad8..0b9e06cfa8 100644 --- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h @@ -76,17 +76,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0x0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpu.h b/cpukit/score/cpu/mips/include/rtems/score/cpu.h index 4dbb053584..447a384c88 100644 --- a/cpukit/score/cpu/mips/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/include/rtems/score/cpu.h @@ -602,7 +602,7 @@ uint32_t mips_interrupt_mask( void ); _xlevel = _scratch2; \ } while(0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0; } diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h index 23d3f35960..cb4c925630 100644 --- a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h @@ -56,29 +56,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word -1" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h index 3a8a3087c6..b94d47ab31 100644 --- a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h @@ -317,7 +317,7 @@ typedef struct { _CPU_ISR_Disable( _isr_cookie ); \ } while (0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return true; } diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h index a54824f16b..9c6ae11d74 100644 --- a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h @@ -56,29 +56,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h index 518fac4308..56c2cb0108 100644 --- a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h @@ -60,17 +60,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/nios2/nios2-iic-irq.c b/cpukit/score/cpu/nios2/nios2-iic-irq.c index 561ba3865e..8215e16a4c 100644 --- a/cpukit/score/cpu/nios2/nios2-iic-irq.c +++ b/cpukit/score/cpu/nios2/nios2-iic-irq.c @@ -60,7 +60,7 @@ void __Exception_Handler(CPU_Exception_frame *efr); register unsigned long *stack_ptr __asm__ ("sp"); -RTEMS_INLINE_ROUTINE void __IIC_Handler(void) +static inline void __IIC_Handler(void) { uint32_t active; uint32_t mask; diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h index 63829b5272..962fc486fc 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h @@ -695,7 +695,7 @@ extern Context_Control_fp _CPU_Null_fp_context; * @retval true Interrupts are enabled in the ISR level. * @retval false Otherwise. */ -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return false; } diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h index 1eec4e6b7a..d5082383e8 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h @@ -151,7 +151,7 @@ void _CPU_Context_validate( uintptr_t pattern ); * * This function is used only in test sptests/spfatal26. */ -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } @@ -161,7 +161,7 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) * * This function is used only in test sptests/spcache01. */ -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } @@ -176,7 +176,7 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) * @param context is the processor context defining the thread-local storage * area to use. */ -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h index 8d9aaee4f9..ce1aa301b3 100644 --- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h @@ -316,7 +316,7 @@ static inline void or1k_interrupt_enable(uint32_t level) _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ } while(0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & CPU_OR1K_SPR_SR ) != 0; } @@ -468,7 +468,7 @@ void _CPU_ISR_install_raw_handler( typedef void ( *CPU_ISR_handler )( uint32_t ); -RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector( +static inline void _CPU_ISR_install_vector( uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h index 35d186990d..352f14589a 100644 --- a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h @@ -60,17 +60,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "l.nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h index 4e606f45d8..84f0bf3f65 100644 --- a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h @@ -608,7 +608,7 @@ typedef struct { #ifndef ASM -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & MSR_EE ) != 0; } diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h index 4a88fe18b1..c81675b53d 100644 --- a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h @@ -273,17 +273,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".long 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 03f2ed8120..f0f3da05da 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -186,12 +186,12 @@ static inline void riscv_interrupt_enable( uint32_t level ) riscv_interrupt_disable(); \ } while(0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) +static inline bool _CPU_ISR_Is_enabled( unsigned long level ) { return ( level & RISCV_MSTATUS_MIE ) != 0; } -RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level ) +static inline void _CPU_ISR_Set_level( uint32_t level ) { if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) { __asm__ volatile ( diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index ca09832d0e..c38d21495a 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -420,17 +420,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "unimp" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h b/cpukit/score/cpu/sh/include/rtems/score/cpu.h index 9ed7d584ff..f2b59a8713 100644 --- a/cpukit/score/cpu/sh/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/sh/include/rtems/score/cpu.h @@ -393,7 +393,7 @@ void CPU_delay( uint32_t microseconds ); #define _CPU_ISR_Flash( _level) \ sh_flash_interrupts( _level) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { sh_get_interrupt_level( level ); return level == 0; diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h index cb20bab616..295b01eeaa 100644 --- a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h @@ -37,29 +37,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/sparc/include/libcpu/byteorder.h b/cpukit/score/cpu/sparc/include/libcpu/byteorder.h index 38b1f18f63..0c469ba36b 100644 --- a/cpukit/score/cpu/sparc/include/libcpu/byteorder.h +++ b/cpukit/score/cpu/sparc/include/libcpu/byteorder.h @@ -37,42 +37,42 @@ extern "C" { #endif -RTEMS_INLINE_ROUTINE uint16_t ld_le16(volatile uint16_t *addr) +static inline uint16_t ld_le16(volatile uint16_t *addr) { return CPU_swap_u16(*addr); } -RTEMS_INLINE_ROUTINE void st_le16(volatile uint16_t *addr, uint16_t val) +static inline void st_le16(volatile uint16_t *addr, uint16_t val) { *addr = CPU_swap_u16(val); } -RTEMS_INLINE_ROUTINE uint32_t ld_le32(volatile uint32_t *addr) +static inline uint32_t ld_le32(volatile uint32_t *addr) { return CPU_swap_u32(*addr); } -RTEMS_INLINE_ROUTINE void st_le32(volatile uint32_t *addr, uint32_t val) +static inline void st_le32(volatile uint32_t *addr, uint32_t val) { *addr = CPU_swap_u32(val); } -RTEMS_INLINE_ROUTINE uint16_t ld_be16(volatile uint16_t *addr) +static inline uint16_t ld_be16(volatile uint16_t *addr) { return *addr; } -RTEMS_INLINE_ROUTINE void st_be16(volatile uint16_t *addr, uint16_t val) +static inline void st_be16(volatile uint16_t *addr, uint16_t val) { *addr = val; } -RTEMS_INLINE_ROUTINE uint32_t ld_be32(volatile uint32_t *addr) +static inline uint32_t ld_be32(volatile uint32_t *addr) { return *addr; } -RTEMS_INLINE_ROUTINE void st_be32(volatile uint32_t *addr, uint32_t val) +static inline void st_be32(volatile uint32_t *addr, uint32_t val) { *addr = val; } diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h index c90071e01d..9044294304 100644 --- a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h @@ -797,7 +797,7 @@ void _SPARC_Interrupt_dispatch( uint32_t irq ); #define _CPU_ISR_Is_enabled( _isr_cookie ) \ sparc_interrupt_is_enabled( _isr_cookie ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & SPARC_PSR_PIL_MASK ) == 0; } diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h index 2a200be7e3..e98a75cf32 100644 --- a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h @@ -224,17 +224,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "unimp 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h index eefe8f0510..90ffe96341 100644 --- a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h @@ -697,7 +697,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template; #define _CPU_ISR_Flash( _level ) \ sparc_flash_interrupts( _level ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & SPARC_PSTATE_IE_MASK ) != 0; } diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h index 23aed1a8d6..8df4c8814c 100644 --- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h @@ -56,29 +56,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "unimp" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpu.h b/cpukit/score/cpu/v850/include/rtems/score/cpu.h index 76fd7869a3..00addf0bc6 100644 --- a/cpukit/score/cpu/v850/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/v850/include/rtems/score/cpu.h @@ -346,7 +346,7 @@ typedef struct { __asm__ __volatile__( "di" ); \ } while (0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & V850_PSW_INTERRUPT_DISABLE_MASK ) != V850_PSW_INTERRUPT_DISABLE; diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h index 8f73b45ad6..4b0f78c845 100644 --- a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h @@ -56,29 +56,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h index 23891acff3..2671c607a7 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h @@ -177,12 +177,12 @@ typedef struct { (void) _level; /* Prevent -Wunused-but-set-variable */ \ } -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled(uint32_t level) +static inline bool _CPU_ISR_Is_enabled(uint32_t level) { return (level & EFLAGS_INTR_ENABLE) != 0; } -RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level) +static inline void _CPU_ISR_Set_level(uint32_t new_level) { if ( new_level ) { amd64_disable_interrupts(); @@ -192,7 +192,7 @@ RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level) } } -RTEMS_INLINE_ROUTINE uint32_t _CPU_ISR_Get_level(void) +static inline uint32_t _CPU_ISR_Get_level(void) { uint64_t rflags; diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h index 4ad50b9f42..10e0887cb9 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h @@ -31,7 +31,7 @@ #include -RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port) +static inline uint8_t inport_byte(uint16_t port) { uint8_t ret; __asm__ volatile ( "inb %1, %0" @@ -40,12 +40,12 @@ RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port) return ret; } -RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val) +static inline void outport_byte(uint16_t port, uint8_t val) { __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) ); } -RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void) +static inline uint16_t amd64_get_cs(void) { uint16_t segment = 0; @@ -54,12 +54,12 @@ RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void) return segment; } -RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment) +static inline void amd64_set_cr3(uint64_t segment) { __asm__ volatile ( "movq %0, %%cr3" : "=r" (segment) : "0" (segment) ); } -RTEMS_INLINE_ROUTINE void cpuid( +static inline void cpuid( uint32_t code, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx ) { __asm__ volatile ( "cpuid" @@ -67,7 +67,7 @@ RTEMS_INLINE_ROUTINE void cpuid( : "a" (code) ); } -RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr) +static inline uint64_t rdmsr(uint32_t msr) { uint32_t low, high; __asm__ volatile ( "rdmsr" : @@ -76,23 +76,23 @@ RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr) return low | (uint64_t) high << 32; } -RTEMS_INLINE_ROUTINE void wrmsr(uint32_t msr, uint32_t low, uint32_t high) +static inline void wrmsr(uint32_t msr, uint32_t low, uint32_t high) { __asm__ volatile ( "wrmsr" : : "a" (low), "d" (high), "c" (msr) ); } -RTEMS_INLINE_ROUTINE void amd64_enable_interrupts(void) +static inline void amd64_enable_interrupts(void) { __asm__ volatile ( "sti" ); } -RTEMS_INLINE_ROUTINE void amd64_disable_interrupts(void) +static inline void amd64_disable_interrupts(void) { __asm__ volatile ( "cli" ); } -RTEMS_INLINE_ROUTINE void stub_io_wait(void) +static inline void stub_io_wait(void) { /* XXX: This likely won't be required on any modern boards, but this function * exists so it's easier to find all the places it may be used. diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h index 680c61ae20..742763c168 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h @@ -40,29 +40,29 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { -- cgit v1.2.3