From 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 Mon Sep 17 00:00:00 2001 From: Chris Johns Date: Sat, 23 Dec 2017 18:18:56 +1100 Subject: Remove make preinstall A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254. --- cpukit/score/cpu/arm/Makefile.am | 18 +- cpukit/score/cpu/arm/headers.am | 24 + cpukit/score/cpu/arm/include/machine/elf_machdep.h | 132 ++ cpukit/score/cpu/arm/include/rtems/asm.h | 231 +++ cpukit/score/cpu/arm/include/rtems/score/arm.h | 94 ++ cpukit/score/cpu/arm/include/rtems/score/armv4.h | 98 ++ cpukit/score/cpu/arm/include/rtems/score/armv7m.h | 620 ++++++++ cpukit/score/cpu/arm/include/rtems/score/cpu.h | 702 +++++++++ cpukit/score/cpu/arm/include/rtems/score/cpu_asm.h | 39 + .../score/cpu/arm/include/rtems/score/cpuatomic.h | 14 + cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h | 111 ++ cpukit/score/cpu/arm/include/rtems/score/types.h | 51 + cpukit/score/cpu/arm/preinstall.am | 70 - cpukit/score/cpu/arm/rtems/asm.h | 231 --- cpukit/score/cpu/arm/rtems/score/arm.h | 94 -- cpukit/score/cpu/arm/rtems/score/armv4.h | 98 -- cpukit/score/cpu/arm/rtems/score/armv7m.h | 620 -------- cpukit/score/cpu/arm/rtems/score/cpu.h | 702 --------- cpukit/score/cpu/arm/rtems/score/cpu_asm.h | 39 - cpukit/score/cpu/arm/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/arm/rtems/score/cpuimpl.h | 111 -- cpukit/score/cpu/arm/rtems/score/types.h | 51 - cpukit/score/cpu/bfin/Makefile.am | 18 +- cpukit/score/cpu/bfin/headers.am | 24 + .../score/cpu/bfin/include/machine/elf_machdep.h | 28 + cpukit/score/cpu/bfin/include/rtems/asm.h | 127 ++ cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h | 430 ++++++ cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h | 396 +++++ cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h | 88 ++ cpukit/score/cpu/bfin/include/rtems/score/bfin.h | 69 + cpukit/score/cpu/bfin/include/rtems/score/cpu.h | 1001 +++++++++++++ .../score/cpu/bfin/include/rtems/score/cpu_asm.h | 27 + .../score/cpu/bfin/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/bfin/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/bfin/include/rtems/score/types.h | 49 + cpukit/score/cpu/bfin/preinstall.am | 70 - cpukit/score/cpu/bfin/rtems/asm.h | 127 -- cpukit/score/cpu/bfin/rtems/bfin/bf52x.h | 430 ------ cpukit/score/cpu/bfin/rtems/bfin/bf533.h | 396 ----- cpukit/score/cpu/bfin/rtems/bfin/bfin.h | 88 -- cpukit/score/cpu/bfin/rtems/score/bfin.h | 69 - cpukit/score/cpu/bfin/rtems/score/cpu.h | 1001 ------------- cpukit/score/cpu/bfin/rtems/score/cpu_asm.h | 27 - cpukit/score/cpu/bfin/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/bfin/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/bfin/rtems/score/types.h | 49 - cpukit/score/cpu/epiphany/Makefile.am | 17 +- cpukit/score/cpu/epiphany/headers.am | 15 + cpukit/score/cpu/epiphany/include/rtems/asm.h | 120 ++ .../score/cpu/epiphany/include/rtems/score/cpu.h | 873 +++++++++++ .../cpu/epiphany/include/rtems/score/cpu_asm.h | 74 + .../cpu/epiphany/include/rtems/score/cpuatomic.h | 14 + .../cpu/epiphany/include/rtems/score/cpuimpl.h | 34 + .../include/rtems/score/epiphany-utility.h | 180 +++ .../cpu/epiphany/include/rtems/score/epiphany.h | 64 + .../score/cpu/epiphany/include/rtems/score/types.h | 67 + cpukit/score/cpu/epiphany/preinstall.am | 57 - cpukit/score/cpu/epiphany/rtems/asm.h | 120 -- cpukit/score/cpu/epiphany/rtems/score/cpu.h | 873 ----------- cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h | 74 - cpukit/score/cpu/epiphany/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h | 34 - .../cpu/epiphany/rtems/score/epiphany-utility.h | 180 --- cpukit/score/cpu/epiphany/rtems/score/epiphany.h | 64 - cpukit/score/cpu/epiphany/rtems/score/types.h | 67 - cpukit/score/cpu/h8300/headers.am | 5 + .../score/cpu/h8300/include/machine/elf_machdep.h | 59 + cpukit/score/cpu/i386/Makefile.am | 15 +- cpukit/score/cpu/i386/headers.am | 20 + .../score/cpu/i386/include/machine/elf_machdep.h | 63 + cpukit/score/cpu/i386/include/rtems/asm.h | 140 ++ cpukit/score/cpu/i386/include/rtems/score/cpu.h | 700 +++++++++ .../score/cpu/i386/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/i386/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/i386/include/rtems/score/i386.h | 670 +++++++++ cpukit/score/cpu/i386/include/rtems/score/idtr.h | 66 + .../cpu/i386/include/rtems/score/interrupts.h | 85 ++ .../score/cpu/i386/include/rtems/score/registers.h | 72 + cpukit/score/cpu/i386/include/rtems/score/types.h | 46 + cpukit/score/cpu/i386/preinstall.am | 61 - cpukit/score/cpu/i386/rtems/asm.h | 140 -- cpukit/score/cpu/i386/rtems/score/cpu.h | 700 --------- cpukit/score/cpu/i386/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/i386/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/i386/rtems/score/i386.h | 670 --------- cpukit/score/cpu/i386/rtems/score/idtr.h | 66 - cpukit/score/cpu/i386/rtems/score/interrupts.h | 85 -- cpukit/score/cpu/i386/rtems/score/registers.h | 72 - cpukit/score/cpu/i386/rtems/score/types.h | 46 - cpukit/score/cpu/lm32/Makefile.am | 13 +- cpukit/score/cpu/lm32/headers.am | 18 + .../score/cpu/lm32/include/machine/elf_machdep.h | 34 + cpukit/score/cpu/lm32/include/rtems/asm.h | 127 ++ cpukit/score/cpu/lm32/include/rtems/score/cpu.h | 1035 +++++++++++++ .../score/cpu/lm32/include/rtems/score/cpu_asm.h | 74 + .../score/cpu/lm32/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/lm32/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/lm32/include/rtems/score/lm32.h | 112 ++ cpukit/score/cpu/lm32/include/rtems/score/types.h | 46 + cpukit/score/cpu/lm32/preinstall.am | 53 - cpukit/score/cpu/lm32/rtems/asm.h | 127 -- cpukit/score/cpu/lm32/rtems/score/cpu.h | 1035 ------------- cpukit/score/cpu/lm32/rtems/score/cpu_asm.h | 74 - cpukit/score/cpu/lm32/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/lm32/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/lm32/rtems/score/lm32.h | 112 -- cpukit/score/cpu/lm32/rtems/score/types.h | 46 - cpukit/score/cpu/m32c/Makefile.am | 15 +- cpukit/score/cpu/m32c/headers.am | 17 + cpukit/score/cpu/m32c/include/rtems/asm.h | 124 ++ cpukit/score/cpu/m32c/include/rtems/score/cpu.h | 985 +++++++++++++ .../score/cpu/m32c/include/rtems/score/cpu_asm.h | 72 + .../score/cpu/m32c/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/m32c/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/m32c/include/rtems/score/m32c.h | 76 + cpukit/score/cpu/m32c/include/rtems/score/types.h | 49 + cpukit/score/cpu/m32c/include/varvects.h | 58 + cpukit/score/cpu/m32c/preinstall.am | 62 - cpukit/score/cpu/m32c/rtems/asm.h | 124 -- cpukit/score/cpu/m32c/rtems/score/cpu.h | 985 ------------- cpukit/score/cpu/m32c/rtems/score/cpu_asm.h | 72 - cpukit/score/cpu/m32c/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/m32c/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/m32c/rtems/score/m32c.h | 76 - cpukit/score/cpu/m32c/rtems/score/types.h | 49 - cpukit/score/cpu/m32c/varvects.h | 58 - cpukit/score/cpu/m68k/Makefile.am | 18 +- cpukit/score/cpu/m68k/headers.am | 24 + .../score/cpu/m68k/include/machine/elf_machdep.h | 47 + cpukit/score/cpu/m68k/include/rtems/asm.h | 152 ++ cpukit/score/cpu/m68k/include/rtems/m68k/m68302.h | 659 +++++++++ cpukit/score/cpu/m68k/include/rtems/m68k/m68360.h | 899 ++++++++++++ cpukit/score/cpu/m68k/include/rtems/m68k/qsm.h | 204 +++ cpukit/score/cpu/m68k/include/rtems/m68k/sim.h | 333 +++++ cpukit/score/cpu/m68k/include/rtems/score/cpu.h | 735 ++++++++++ .../score/cpu/m68k/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/m68k/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/m68k/include/rtems/score/m68k.h | 502 +++++++ cpukit/score/cpu/m68k/include/rtems/score/types.h | 43 + cpukit/score/cpu/m68k/preinstall.am | 70 - cpukit/score/cpu/m68k/rtems/asm.h | 152 -- cpukit/score/cpu/m68k/rtems/m68k/m68302.h | 659 --------- cpukit/score/cpu/m68k/rtems/m68k/m68360.h | 899 ------------ cpukit/score/cpu/m68k/rtems/m68k/qsm.h | 204 --- cpukit/score/cpu/m68k/rtems/m68k/sim.h | 333 ----- cpukit/score/cpu/m68k/rtems/score/cpu.h | 735 ---------- cpukit/score/cpu/m68k/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/m68k/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/m68k/rtems/score/m68k.h | 502 ------- cpukit/score/cpu/m68k/rtems/score/types.h | 43 - cpukit/score/cpu/mips/Makefile.am | 16 +- cpukit/score/cpu/mips/headers.am | 22 + .../score/cpu/mips/include/machine/elf_machdep.h | 199 +++ cpukit/score/cpu/mips/include/rtems/asm.h | 160 ++ cpukit/score/cpu/mips/include/rtems/mips/idtcpu.h | 708 +++++++++ cpukit/score/cpu/mips/include/rtems/mips/iregdef.h | 337 +++++ cpukit/score/cpu/mips/include/rtems/score/cpu.h | 1010 +++++++++++++ .../score/cpu/mips/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/mips/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/mips/include/rtems/score/mips.h | 299 ++++ cpukit/score/cpu/mips/include/rtems/score/types.h | 56 + cpukit/score/cpu/mips/preinstall.am | 62 - cpukit/score/cpu/mips/rtems/asm.h | 160 -- cpukit/score/cpu/mips/rtems/mips/idtcpu.h | 708 --------- cpukit/score/cpu/mips/rtems/mips/iregdef.h | 337 ----- cpukit/score/cpu/mips/rtems/score/cpu.h | 1010 ------------- cpukit/score/cpu/mips/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/mips/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/mips/rtems/score/mips.h | 299 ---- cpukit/score/cpu/mips/rtems/score/types.h | 56 - cpukit/score/cpu/moxie/Makefile.am | 11 +- cpukit/score/cpu/moxie/headers.am | 17 + .../score/cpu/moxie/include/machine/elf_machdep.h | 15 + cpukit/score/cpu/moxie/include/rtems/asm.h | 116 ++ cpukit/score/cpu/moxie/include/rtems/score/cpu.h | 852 +++++++++++ .../cpu/moxie/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/moxie/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/moxie/include/rtems/score/moxie.h | 43 + cpukit/score/cpu/moxie/include/rtems/score/types.h | 56 + cpukit/score/cpu/moxie/preinstall.am | 49 - cpukit/score/cpu/moxie/rtems/asm.h | 116 -- cpukit/score/cpu/moxie/rtems/score/cpu.h | 852 ----------- cpukit/score/cpu/moxie/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/moxie/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/moxie/rtems/score/moxie.h | 43 - cpukit/score/cpu/moxie/rtems/score/types.h | 56 - cpukit/score/cpu/nios2/Makefile.am | 18 +- cpukit/score/cpu/nios2/headers.am | 20 + .../score/cpu/nios2/include/machine/elf_machdep.h | 46 + cpukit/score/cpu/nios2/include/rtems/asm.h | 98 ++ cpukit/score/cpu/nios2/include/rtems/score/cpu.h | 372 +++++ .../score/cpu/nios2/include/rtems/score/cpu_asm.h | 74 + .../cpu/nios2/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/nios2/include/rtems/score/cpuimpl.h | 34 + .../nios2/include/rtems/score/nios2-count-zeros.h | 70 + .../cpu/nios2/include/rtems/score/nios2-utility.h | 516 +++++++ cpukit/score/cpu/nios2/include/rtems/score/nios2.h | 65 + cpukit/score/cpu/nios2/include/rtems/score/types.h | 46 + cpukit/score/cpu/nios2/preinstall.am | 61 - cpukit/score/cpu/nios2/rtems/asm.h | 98 -- cpukit/score/cpu/nios2/rtems/score/cpu.h | 372 ----- cpukit/score/cpu/nios2/rtems/score/cpu_asm.h | 74 - cpukit/score/cpu/nios2/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/nios2/rtems/score/cpuimpl.h | 34 - .../cpu/nios2/rtems/score/nios2-count-zeros.h | 70 - cpukit/score/cpu/nios2/rtems/score/nios2-utility.h | 516 ------- cpukit/score/cpu/nios2/rtems/score/nios2.h | 65 - cpukit/score/cpu/nios2/rtems/score/types.h | 46 - cpukit/score/cpu/no_cpu/Makefile.am | 12 +- cpukit/score/cpu/no_cpu/headers.am | 13 + cpukit/score/cpu/no_cpu/include/rtems/asm.h | 133 ++ cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h | 1501 +++++++++++++++++++ .../score/cpu/no_cpu/include/rtems/score/cpu_asm.h | 74 + .../score/cpu/no_cpu/include/rtems/score/cpuimpl.h | 82 ++ .../score/cpu/no_cpu/include/rtems/score/no_cpu.h | 67 + .../score/cpu/no_cpu/include/rtems/score/types.h | 43 + cpukit/score/cpu/no_cpu/preinstall.am | 49 - cpukit/score/cpu/no_cpu/rtems/asm.h | 133 -- cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 1501 ------------------- cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h | 74 - cpukit/score/cpu/no_cpu/rtems/score/cpuimpl.h | 82 -- cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h | 67 - cpukit/score/cpu/no_cpu/rtems/score/types.h | 43 - cpukit/score/cpu/or1k/Makefile.am | 17 +- cpukit/score/cpu/or1k/headers.am | 15 + cpukit/score/cpu/or1k/include/rtems/asm.h | 99 ++ cpukit/score/cpu/or1k/include/rtems/score/cpu.h | 872 +++++++++++ .../score/cpu/or1k/include/rtems/score/cpu_asm.h | 74 + .../score/cpu/or1k/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/or1k/include/rtems/score/cpuimpl.h | 34 + .../cpu/or1k/include/rtems/score/or1k-utility.h | 396 +++++ cpukit/score/cpu/or1k/include/rtems/score/or1k.h | 49 + cpukit/score/cpu/or1k/include/rtems/score/types.h | 53 + cpukit/score/cpu/or1k/preinstall.am | 57 - cpukit/score/cpu/or1k/rtems/asm.h | 99 -- cpukit/score/cpu/or1k/rtems/score/cpu.h | 872 ----------- cpukit/score/cpu/or1k/rtems/score/cpu_asm.h | 74 - cpukit/score/cpu/or1k/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/or1k/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 396 ----- cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 - cpukit/score/cpu/or1k/rtems/score/types.h | 53 - cpukit/score/cpu/powerpc/Makefile.am | 15 +- cpukit/score/cpu/powerpc/headers.am | 21 + .../cpu/powerpc/include/machine/elf_machdep.h | 105 ++ cpukit/score/cpu/powerpc/include/rtems/asm.h | 310 ++++ .../cpu/powerpc/include/rtems/powerpc/registers.h | 774 ++++++++++ cpukit/score/cpu/powerpc/include/rtems/score/cpu.h | 1257 ++++++++++++++++ .../cpu/powerpc/include/rtems/score/cpuatomic.h | 14 + .../cpu/powerpc/include/rtems/score/cpuimpl.h | 247 ++++ .../cpu/powerpc/include/rtems/score/powerpc.h | 187 +++ .../score/cpu/powerpc/include/rtems/score/types.h | 62 + cpukit/score/cpu/powerpc/preinstall.am | 58 - cpukit/score/cpu/powerpc/rtems/asm.h | 310 ---- cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 774 ---------- cpukit/score/cpu/powerpc/rtems/score/cpu.h | 1257 ---------------- cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h | 247 ---- cpukit/score/cpu/powerpc/rtems/score/powerpc.h | 187 --- cpukit/score/cpu/powerpc/rtems/score/types.h | 62 - cpukit/score/cpu/riscv/Makefile.am | 14 +- cpukit/score/cpu/riscv/headers.am | 15 + cpukit/score/cpu/riscv/include/rtems/asm.h | 120 ++ cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 604 ++++++++ .../score/cpu/riscv/include/rtems/score/cpu_asm.h | 90 ++ .../cpu/riscv/include/rtems/score/cpuatomic.h | 31 + .../score/cpu/riscv/include/rtems/score/cpuimpl.h | 51 + .../cpu/riscv/include/rtems/score/riscv-utility.h | 1526 ++++++++++++++++++++ cpukit/score/cpu/riscv/include/rtems/score/riscv.h | 66 + cpukit/score/cpu/riscv/include/rtems/score/types.h | 70 + cpukit/score/cpu/riscv/preinstall.am | 57 - cpukit/score/cpu/riscv/rtems/asm.h | 120 -- cpukit/score/cpu/riscv/rtems/score/cpu.h | 604 -------- cpukit/score/cpu/riscv/rtems/score/cpu_asm.h | 90 -- cpukit/score/cpu/riscv/rtems/score/cpuatomic.h | 31 - cpukit/score/cpu/riscv/rtems/score/cpuimpl.h | 51 - cpukit/score/cpu/riscv/rtems/score/riscv-utility.h | 1526 -------------------- cpukit/score/cpu/riscv/rtems/score/riscv.h | 66 - cpukit/score/cpu/riscv/rtems/score/types.h | 70 - cpukit/score/cpu/sh/Makefile.am | 13 +- cpukit/score/cpu/sh/headers.am | 14 + cpukit/score/cpu/sh/include/rtems/asm.h | 137 ++ cpukit/score/cpu/sh/include/rtems/score/cpu.h | 738 ++++++++++ .../score/cpu/sh/include/rtems/score/cpuatomic.h | 14 + cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h | 34 + cpukit/score/cpu/sh/include/rtems/score/sh.h | 277 ++++ cpukit/score/cpu/sh/include/rtems/score/sh_io.h | 51 + cpukit/score/cpu/sh/include/rtems/score/types.h | 56 + cpukit/score/cpu/sh/preinstall.am | 53 - cpukit/score/cpu/sh/rtems/asm.h | 137 -- cpukit/score/cpu/sh/rtems/score/cpu.h | 738 ---------- cpukit/score/cpu/sh/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/sh/rtems/score/cpuimpl.h | 34 - cpukit/score/cpu/sh/rtems/score/sh.h | 277 ---- cpukit/score/cpu/sh/rtems/score/sh_io.h | 51 - cpukit/score/cpu/sh/rtems/score/types.h | 56 - cpukit/score/cpu/sparc/Makefile.am | 16 +- cpukit/score/cpu/sparc/headers.am | 22 + .../score/cpu/sparc/include/machine/elf_machdep.h | 92 ++ cpukit/score/cpu/sparc/include/rtems/asm.h | 120 ++ cpukit/score/cpu/sparc/include/rtems/score/cpu.h | 1202 +++++++++++++++ .../cpu/sparc/include/rtems/score/cpuatomic.h | 14 + .../score/cpu/sparc/include/rtems/score/cpuimpl.h | 155 ++ cpukit/score/cpu/sparc/include/rtems/score/sparc.h | 418 ++++++ .../cpu/sparc/include/rtems/score/sparcimpl.h | 90 ++ cpukit/score/cpu/sparc/include/rtems/score/types.h | 53 + cpukit/score/cpu/sparc/preinstall.am | 62 - cpukit/score/cpu/sparc/rtems/asm.h | 120 -- cpukit/score/cpu/sparc/rtems/score/cpu.h | 1202 --------------- cpukit/score/cpu/sparc/rtems/score/cpuatomic.h | 14 - cpukit/score/cpu/sparc/rtems/score/cpuimpl.h | 155 -- cpukit/score/cpu/sparc/rtems/score/sparc.h | 418 ------ cpukit/score/cpu/sparc/rtems/score/sparcimpl.h | 90 -- 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cpukit/score/cpu/v850/preinstall.am delete mode 100644 cpukit/score/cpu/v850/rtems/asm.h delete mode 100644 cpukit/score/cpu/v850/rtems/score/cpu.h delete mode 100644 cpukit/score/cpu/v850/rtems/score/cpu_asm.h delete mode 100644 cpukit/score/cpu/v850/rtems/score/cpuatomic.h delete mode 100644 cpukit/score/cpu/v850/rtems/score/cpuimpl.h delete mode 100644 cpukit/score/cpu/v850/rtems/score/types.h delete mode 100644 cpukit/score/cpu/v850/rtems/score/v850.h (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/arm/Makefile.am b/cpukit/score/cpu/arm/Makefile.am index a0881e80e9..865a750477 100644 --- a/cpukit/score/cpu/arm/Makefile.am +++ b/cpukit/score/cpu/arm/Makefile.am @@ -1,20 +1,4 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/arm.h -include_rtems_score_HEADERS += rtems/score/armv4.h -include_rtems_score_HEADERS += rtems/score/armv7m.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - -include_libcpudir = $(includedir)/libcpu -include_libcpu_HEADERS = include/libcpu/arm-cp15.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) libscorecpu_a_SOURCES = @@ -48,5 +32,5 @@ libscorecpu_a_SOURCES += armv7m-isr-level-set.c libscorecpu_a_SOURCES += armv7m-isr-vector-install.c libscorecpu_a_SOURCES += armv7m-multitasking-start-stop.c -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/arm/headers.am b/cpukit/score/cpu/arm/headers.am new file mode 100644 index 0000000000..61a055f79a --- /dev/null +++ b/cpukit/score/cpu/arm/headers.am @@ -0,0 +1,24 @@ +## This file was generated by "./boostrap -H". + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += include/libcpu/arm-cp15.h + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/arm.h +include_rtems_score_HEADERS += include/rtems/score/armv4.h +include_rtems_score_HEADERS += include/rtems/score/armv7m.h +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/arm/include/machine/elf_machdep.h b/cpukit/score/cpu/arm/include/machine/elf_machdep.h new file mode 100644 index 0000000000..8f01d05212 --- /dev/null +++ b/cpukit/score/cpu/arm/include/machine/elf_machdep.h @@ -0,0 +1,132 @@ +/* $NetBSD: elf_machdep.h,v 1.8 2009/05/30 05:56:52 skrll Exp $ */ + +#if defined(__ARMEB__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#else +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#endif + +#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ +#define ELF64_MACHDEP_ID_CASES \ + /* no 64-bit ELF machine types supported */ + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x00000001 +#define EF_ARM_HASENTRY 0x00000002 +#define EF_ARM_INTERWORK 0x00000004 /* GNU binutils 000413 */ +#define EF_ARM_SYMSARESORTED 0x00000004 /* ARM ELF A08 */ +#define EF_ARM_APCS_26 0x00000008 /* GNU binutils 000413 */ +#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ARM ELF B01 */ +#define EF_ARM_APCS_FLOAT 0x00000010 /* GNU binutils 000413 */ +#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ARM ELF B01 */ +#define EF_ARM_PIC 0x00000020 +#define EF_ARM_ALIGN8 0x00000040 /* 8-bit structure alignment. */ +#define EF_ARM_NEW_ABI 0x00000080 +#define EF_ARM_OLD_ABI 0x00000100 +#define EF_ARM_SOFT_FLOAT 0x00000200 +#define EF_ARM_EABIMASK 0xff000000 + +#define ELF32_MACHDEP_ID_CASES \ + case EM_ARM: \ + break; + +#define ELF32_MACHDEP_ID EM_ARM + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +/* Processor specific relocation types */ + +#define R_ARM_NONE 0 +#define R_ARM_PC24 1 +#define R_ARM_ABS32 2 +#define R_ARM_REL32 3 +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 +#define R_ARM_ABS12 6 +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 +#define R_ARM_SBREL32 9 +#define R_ARM_THM_CALL 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 + +/* TLS relocations */ +#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ +#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ +#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ + +/* 20-31 are reserved for ARM Linux. */ +#define R_ARM_COPY 20 +#define R_ARM_GLOB_DAT 21 +#define R_ARM_JUMP_SLOT 22 +#define R_ARM_RELATIVE 23 +#define R_ARM_GOTOFF 24 +#define R_ARM_GOTPC 25 +#define R_ARM_GOT32 26 +#define R_ARM_PLT32 27 +#define R_ARM_CALL 28 +#define R_ARM_JUMP24 29 +#define R_ARM_THM_JUMP24 30 +#define R_ARM_BASE_ABS 31 + +#define R_ARM_ALU_PCREL_7_0 32 +#define R_ARM_ALU_PCREL_15_8 33 +#define R_ARM_ALU_PCREL_23_15 34 +#define R_ARM_ALU_SBREL_11_0 35 +#define R_ARM_ALU_SBREL_19_12 36 +#define R_ARM_ALU_SBREL_27_20 37 +#define R_ARM_V4BX 40 +#define R_ARM_TARGET2 41 +#define R_ARM_PREL31 42 + +#define R_ARM_MOVW_ABS_NC 43 +#define R_ARM_MOVT_ABS 44 + +#define R_ARM_THM_MOVW_ABS_NC 47 +#define R_ARM_THM_MOVT_ABS 48 + +#define R_ARM_THM_JUMP19 51 + +/* 96-111 are reserved to G++. */ +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_JUMP11 102 +#define R_ARM_THM_JUMP8 103 + +/* More TLS relocations */ +#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic */ +#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic */ +#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS */ +#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of */ +#define R_ARM_TLS_LE32 108 +#define R_ARM_TLS_LDO12 109 +#define R_ARM_TLS_LE12 110 +#define R_ARM_TLS_IE12GP 111 + +/* 112-127 are reserved for private experiments. */ + +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS32 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 + +#define R_TYPE(name) __CONCAT(R_ARM_,name) + +/* Processor specific program header flags */ +#define PF_ARM_SB 0x10000000 +#define PF_ARM_PI 0x20000000 +#define PF_ARM_ENTRY 0x80000000 + +/* Processor specific section header flags */ +#define SHF_ENTRYSECT 0x10000000 +#define SHF_COMDEF 0x80000000 + +/* Processor specific symbol types */ +#define STT_ARM_TFUNC STT_LOPROC diff --git a/cpukit/score/cpu/arm/include/rtems/asm.h b/cpukit/score/cpu/arm/include/rtems/asm.h new file mode 100644 index 0000000000..f72df32325 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/asm.h @@ -0,0 +1,231 @@ +/** + * @file + * + * @brief ARM Assembler Support API + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include + +/** + * @defgroup ScoreCPUARMASM ARM Assembler Support + * + * @ingroup ScoreCPU + * + * @brief ARM Assembler Support + */ +/**@{**/ + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +#define r0 REG(r0) +#define r1 REG(r1) +#define r2 REG(r2) +#define r3 REG(r3) +#define r4 REG(r4) +#define r5 REG(r5) +#define r6 REG(r6) +#define r7 REG(r7) +#define r8 REG(r8) +#define r9 REG(r9) +#define r10 REG(r10) +#define r11 REG(r11) +#define r12 REG(r12) +#define r13 REG(r13) +#define r14 REG(r14) +#define r15 REG(r15) + +#define CPSR REG(CPSR) + +#define SPSR REG(SPSR) + +#define NUM_IRQ_VECTOR 6 // IRQ number +#define NUM_FIQ_VECTOR 7 // IRQ number + // // +#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1 +#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 +#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 +#define CPSR_FIQ_MODE 0x11 +#define CPSR_IRQ_MODE 0x12 +#define CPSR_SUPERVISOR_MODE 0x13 +#define CPSR_UNDEF_MODE 0x1B + +#define CPSR_MODE_BITS 0x1F + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#define FUNCTION_THUMB_ENTRY(name) \ + .thumb; \ + .thumb_func; \ + .align 2; \ + .globl name; \ + .type name, %function; \ + name: + +#define FUNCTION_ENTRY(name) \ + .align 2; \ + .globl name; \ + .type name, %function; \ + name: + +#define FUNCTION_END(name) \ + .size name, . - name + +#if defined(ARM_MULTILIB_ARCH_V7M) + #define DEFINE_FUNCTION_ARM(name) \ + .thumb_func ; .globl name ; name: +#elif defined(__thumb__) + #define DEFINE_FUNCTION_ARM(name) \ + .thumb_func ; .globl name ; name: ; bx pc ; \ + .arm ; .globl name ## _arm ; name ## _arm: +#else + #define DEFINE_FUNCTION_ARM(name) \ + .globl name ; name: ; .globl name ## _arm ; name ## _arm: +#endif + +.macro SWITCH_FROM_THUMB_TO_ARM +#ifdef __thumb__ +.align 2 + bx pc +.arm +#endif /* __thumb__ */ +.endm + +.macro SWITCH_FROM_ARM_TO_THUMB REG +#ifdef __thumb__ + add \REG, pc, #1 + bx \REG +.thumb +#endif /* __thumb__ */ +.endm + +.macro SWITCH_FROM_THUMB_2_TO_ARM +#ifdef __thumb2__ +.align 2 + bx pc +.arm +#endif /* __thumb__ */ +.endm + +.macro SWITCH_FROM_ARM_TO_THUMB_2 REG +#ifdef __thumb2__ + add \REG, pc, #1 + bx \REG +.thumb +#endif /* __thumb__ */ +.endm + +.macro BLX_TO_THUMB_1 TARGET +#if defined(__thumb__) && !defined(__thumb2__) + add lr, pc, #1 + bx lr +.thumb + bl \TARGET +.align 2 + bx pc +.arm +#else + bl \TARGET +#endif +.endm + +.macro GET_SELF_CPU_CONTROL REG +#ifdef RTEMS_SMP + /* Use PL1 only Thread ID Register (TPIDRPRW) */ + mrc p15, 0, \REG, c13, c0, 4 +#else + ldr \REG, =_Per_CPU_Information +#endif +.endm + +/** @} */ + +#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/arm.h b/cpukit/score/cpu/arm/include/rtems/score/arm.h new file mode 100755 index 0000000000..f08da1dc57 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/arm.h @@ -0,0 +1,94 @@ +/** + * @file + * + * @brief ARM Assembler Support API + */ + +/* + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Copyright (c) 2002 Advent Networks, Inc. + * Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_ARM_H +#define _RTEMS_SCORE_ARM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + #define CPU_MODEL_NAME "ARMv7M" + #define ARM_MULTILIB_ARCH_V7M +#elif defined(__ARM_ARCH_6M__) + #define CPU_MODEL_NAME "ARMv6M" + #define ARM_MULTILIB_ARCH_V6M +#else + #define CPU_MODEL_NAME "ARMv4" + #define ARM_MULTILIB_ARCH_V4 +#endif + +#if defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7R__) \ + || defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) + #define ARM_MULTILIB_HAS_WFI + #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE + #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS +#endif + +#if defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7R__) + #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER +#endif + +#if defined(__ARM_ARCH_7A__) + #define ARM_MULTILIB_CACHE_LINE_MAX_64 +#endif + +#if defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) + #define ARM_MULTILIB_HAS_CPACR +#endif + +#if !defined(__SOFTFP__) + #if defined(__ARM_NEON__) + #define ARM_MULTILIB_VFP_D32 + #elif defined(__VFP_FP__) + #define ARM_MULTILIB_VFP_D16 + #else + #error "FPU support not implemented" + #endif +#endif + +#if defined(ARM_MULTILIB_VFP_D16) \ + || defined(ARM_MULTILIB_VFP_D32) + #define ARM_MULTILIB_VFP +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "ARM" + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_ARM_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv4.h b/cpukit/score/cpu/arm/include/rtems/score/armv4.h new file mode 100644 index 0000000000..caeaa3e553 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/armv4.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef RTEMS_SCORE_ARMV4_H +#define RTEMS_SCORE_ARMV4_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef ARM_MULTILIB_ARCH_V4 + +void bsp_interrupt_dispatch( void ); + +void _ARMV4_Exception_interrupt( void ); + +typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame ); + +void _ARMV4_Exception_data_abort_set_handler( + ARMV4_Exception_abort_handler handler +); + +void _ARMV4_Exception_data_abort( void ); + +void _ARMV4_Exception_prefetch_abort_set_handler( + ARMV4_Exception_abort_handler handler +); + +void _ARMV4_Exception_prefetch_abort( void ); + +void _ARMV4_Exception_undef_default( void ); + +void _ARMV4_Exception_swi_default( void ); + +void _ARMV4_Exception_data_abort_default( void ); + +void _ARMV4_Exception_pref_abort_default( void ); + +void _ARMV4_Exception_reserved_default( void ); + +void _ARMV4_Exception_irq_default( void ); + +void _ARMV4_Exception_fiq_default( void ); + +static inline uint32_t _ARMV4_Status_irq_enable( void ) +{ + uint32_t arm_switch_reg; + uint32_t psr; + + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[psr], cpsr\n" + "bic %[arm_switch_reg], %[psr], #0x80\n" + "msr cpsr, %[arm_switch_reg]\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr) + ); + + return psr; +} + +static inline void _ARMV4_Status_restore( uint32_t psr ) +{ + ARM_SWITCH_REGISTERS; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "msr cpsr, %[psr]\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [psr] "r" (psr) + ); + + RTEMS_COMPILER_MEMORY_BARRIER(); +} + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* RTEMS_SCORE_ARMV4_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h new file mode 100644 index 0000000000..a6cc8a34ac --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h @@ -0,0 +1,620 @@ +/** + * @file + * + * @brief ARMV7M Architecture Support + */ + +/* + * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef RTEMS_SCORE_ARMV7M_H +#define RTEMS_SCORE_ARMV7M_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef ARM_MULTILIB_ARCH_V7M + +/* Coprocessor Access Control Register, CPACR */ +#define ARMV7M_CPACR 0xe000ed88 + +#ifndef ASM + +typedef struct { + uint32_t reserved_0; + uint32_t ictr; + uint32_t actlr; + uint32_t reserved_1; +} ARMV7M_ICTAC; + +typedef void (*ARMV7M_Exception_handler)(void); + +typedef struct { + uint32_t register_r0; + uint32_t register_r1; + uint32_t register_r2; + uint32_t register_r3; + uint32_t register_r12; + void *register_lr; + void *register_pc; + uint32_t register_xpsr; +#ifdef ARM_MULTILIB_VFP + uint32_t register_s0; + uint32_t register_s1; + uint32_t register_s2; + uint32_t register_s3; + uint32_t register_s4; + uint32_t register_s5; + uint32_t register_s6; + uint32_t register_s7; + uint32_t register_s8; + uint32_t register_s9; + uint32_t register_s10; + uint32_t register_s11; + uint32_t register_s12; + uint32_t register_s13; + uint32_t register_s14; + uint32_t register_s15; + uint32_t register_fpscr; + uint32_t reserved; +#endif +} ARMV7M_Exception_frame; + +typedef struct { + uint32_t comp; + uint32_t mask; + uint32_t function; + uint32_t reserved; +} ARMV7M_DWT_comparator; + +typedef struct { +#define ARMV7M_DWT_CTRL_NOCYCCNT (1U << 25) +#define ARMV7M_DWT_CTRL_CYCCNTENA (1U << 0) + uint32_t ctrl; + uint32_t cyccnt; + uint32_t cpicnt; + uint32_t exccnt; + uint32_t sleepcnt; + uint32_t lsucnt; + uint32_t foldcnt; + uint32_t pcsr; + ARMV7M_DWT_comparator comparator[249]; +#define ARMV7M_DWT_LAR_UNLOCK_MAGIC 0xc5acce55U + uint32_t lar; + uint32_t lsr; +} ARMV7M_DWT; + +typedef struct { + uint32_t cpuid; + +#define ARMV7M_SCB_ICSR_NMIPENDSET (1U << 31) +#define ARMV7M_SCB_ICSR_PENDSVSET (1U << 28) +#define ARMV7M_SCB_ICSR_PENDSVCLR (1U << 27) +#define ARMV7M_SCB_ICSR_PENDSTSET (1U << 26) +#define ARMV7M_SCB_ICSR_PENDSTCLR (1U << 25) +#define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23) +#define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22) +#define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU) +#define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11) +#define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU) + uint32_t icsr; + + ARMV7M_Exception_handler *vtor; + +#define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16) +#define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15) +#define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8 +#define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \ + ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) +#define ARMV7M_SCB_AIRCR_PRIGROUP(val) \ + (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) +#define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \ + (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) +#define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \ + (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val)) +#define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2) +#define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1) +#define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0) + uint32_t aircr; + + uint32_t scr; + uint32_t ccr; + uint8_t shpr [12]; + +#define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18) +#define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17) +#define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16) + uint32_t shcsr; + + uint32_t cfsr; + uint32_t hfsr; + uint32_t dfsr; + uint32_t mmfar; + uint32_t bfar; + uint32_t afsr; + uint32_t reserved_e000ed40[18]; + uint32_t cpacr; + uint32_t reserved_e000ed8c[106]; + uint32_t fpccr; + uint32_t fpcar; + uint32_t fpdscr; + uint32_t mvfr0; + uint32_t mvfr1; +} ARMV7M_SCB; + +typedef struct { +#define ARMV7M_SYSTICK_CSR_COUNTFLAG (1U << 16) +#define ARMV7M_SYSTICK_CSR_CLKSOURCE (1U << 2) +#define ARMV7M_SYSTICK_CSR_TICKINT (1U << 1) +#define ARMV7M_SYSTICK_CSR_ENABLE (1U << 0) + uint32_t csr; + + uint32_t rvr; + uint32_t cvr; + +#define ARMV7M_SYSTICK_CALIB_NOREF (1U << 31) +#define ARMV7M_SYSTICK_CALIB_SKEW (1U << 30) +#define ARMV7M_SYSTICK_CALIB_TENMS_GET(reg) ((reg) & 0xffffffU) + uint32_t calib; +} ARMV7M_Systick; + +typedef struct { + uint32_t iser [8]; + uint32_t reserved_0 [24]; + uint32_t icer [8]; + uint32_t reserved_1 [24]; + uint32_t ispr [8]; + uint32_t reserved_2 [24]; + uint32_t icpr [8]; + uint32_t reserved_3 [24]; + uint32_t iabr [8]; + uint32_t reserved_4 [56]; + uint8_t ipr [240]; + uint32_t reserved_5 [644]; + uint32_t stir; +} ARMV7M_NVIC; + +typedef struct { +#define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU) +#define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU) +#define ARMV7M_MPU_TYPE_SEPARATE (1U << 0) + uint32_t type; + +#define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2) +#define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1) +#define ARMV7M_MPU_CTRL_ENABLE (1U << 0) + uint32_t ctrl; + + uint32_t rnr; + +#define ARMV7M_MPU_RBAR_ADDR_SHIFT 5 +#define ARMV7M_MPU_RBAR_ADDR_MASK \ + ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT) +#define ARMV7M_MPU_RBAR_ADDR(val) \ + (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK) +#define ARMV7M_MPU_RBAR_ADDR_GET(reg) \ + (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT) +#define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \ + (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val)) +#define ARMV7M_MPU_RBAR_VALID (1U << 4) +#define ARMV7M_MPU_RBAR_REGION_SHIFT 0 +#define ARMV7M_MPU_RBAR_REGION_MASK \ + ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT) +#define ARMV7M_MPU_RBAR_REGION(val) \ + (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK) +#define ARMV7M_MPU_RBAR_REGION_GET(reg) \ + (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT) +#define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \ + (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val)) + uint32_t rbar; + +#define ARMV7M_MPU_RASR_XN (1U << 28) +#define ARMV7M_MPU_RASR_AP_SHIFT 24 +#define ARMV7M_MPU_RASR_AP_MASK \ + ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT) +#define ARMV7M_MPU_RASR_AP(val) \ + (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK) +#define ARMV7M_MPU_RASR_AP_GET(reg) \ + (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT) +#define ARMV7M_MPU_RASR_AP_SET(reg, val) \ + (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val)) +#define ARMV7M_MPU_RASR_TEX_SHIFT 19 +#define ARMV7M_MPU_RASR_TEX_MASK \ + ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT) +#define ARMV7M_MPU_RASR_TEX(val) \ + (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK) +#define ARMV7M_MPU_RASR_TEX_GET(reg) \ + (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT) +#define ARMV7M_MPU_RASR_TEX_SET(reg, val) \ + (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val)) +#define ARMV7M_MPU_RASR_S (1U << 18) +#define ARMV7M_MPU_RASR_C (1U << 17) +#define ARMV7M_MPU_RASR_B (1U << 16) +#define ARMV7M_MPU_RASR_SRD_SHIFT 8 +#define ARMV7M_MPU_RASR_SRD_MASK \ + ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT) +#define ARMV7M_MPU_RASR_SRD(val) \ + (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK) +#define ARMV7M_MPU_RASR_SRD_GET(reg) \ + (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT) +#define ARMV7M_MPU_RASR_SRD_SET(reg, val) \ + (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val)) +#define ARMV7M_MPU_RASR_SIZE_SHIFT 1 +#define ARMV7M_MPU_RASR_SIZE_MASK \ + ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT) +#define ARMV7M_MPU_RASR_SIZE(val) \ + (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK) +#define ARMV7M_MPU_RASR_SIZE_GET(reg) \ + (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT) +#define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \ + (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val)) +#define ARMV7M_MPU_RASR_ENABLE (1U << 0) + uint32_t rasr; + + uint32_t rbar_a1; + uint32_t rasr_a1; + uint32_t rbar_a2; + uint32_t rasr_a2; + uint32_t rbar_a3; + uint32_t rasr_a3; +} ARMV7M_MPU; + +typedef enum { + ARMV7M_MPU_AP_PRIV_NO_USER_NO, + ARMV7M_MPU_AP_PRIV_RW_USER_NO, + ARMV7M_MPU_AP_PRIV_RW_USER_RO, + ARMV7M_MPU_AP_PRIV_RW_USER_RW, + ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5, + ARMV7M_MPU_AP_PRIV_RO_USER_RO, +} ARMV7M_MPU_Access_permissions; + +typedef enum { + ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO) + | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN, + ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) + | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B, + ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) + | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B, + ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO) + | ARMV7M_MPU_RASR_C, + ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO) + | ARMV7M_MPU_RASR_C, + ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) + | ARMV7M_MPU_RASR_XN, +} ARMV7M_MPU_Attributes; + +typedef enum { + ARMV7M_MPU_SIZE_32_B = 0x4, + ARMV7M_MPU_SIZE_64_B, + ARMV7M_MPU_SIZE_128_B, + ARMV7M_MPU_SIZE_256_B, + ARMV7M_MPU_SIZE_512_B, + ARMV7M_MPU_SIZE_1_KB, + ARMV7M_MPU_SIZE_2_KB, + ARMV7M_MPU_SIZE_4_KB, + ARMV7M_MPU_SIZE_8_KB, + ARMV7M_MPU_SIZE_16_KB, + ARMV7M_MPU_SIZE_32_KB, + ARMV7M_MPU_SIZE_64_KB, + ARMV7M_MPU_SIZE_128_KB, + ARMV7M_MPU_SIZE_256_KB, + ARMV7M_MPU_SIZE_512_KB, + ARMV7M_MPU_SIZE_1_MB, + ARMV7M_MPU_SIZE_2_MB, + ARMV7M_MPU_SIZE_4_MB, + ARMV7M_MPU_SIZE_8_MB, + ARMV7M_MPU_SIZE_16_MB, + ARMV7M_MPU_SIZE_32_MB, + ARMV7M_MPU_SIZE_64_MB, + ARMV7M_MPU_SIZE_128_MB, + ARMV7M_MPU_SIZE_256_MB, + ARMV7M_MPU_SIZE_512_MB, + ARMV7M_MPU_SIZE_1_GB, + ARMV7M_MPU_SIZE_2_GB, + ARMV7M_MPU_SIZE_4_GB +} ARMV7M_MPU_Size; + +typedef struct { + uint32_t rbar; + uint32_t rasr; +} ARMV7M_MPU_Region; + +#define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \ + { \ + ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \ + | ARMV7M_MPU_RBAR_VALID \ + | ARMV7M_MPU_RBAR_REGION(idx), \ + ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \ + } + +#define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \ + { \ + ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \ + 0 \ + } + +typedef struct { + uint32_t dhcsr; + uint32_t dcrsr; + uint32_t dcrdr; +#define ARMV7M_DEBUG_DEMCR_VC_CORERESET (1U << 0) +#define ARMV7M_DEBUG_DEMCR_VC_MMERR (1U << 4) +#define ARMV7M_DEBUG_DEMCR_VC_NOCPERR (1U << 5) +#define ARMV7M_DEBUG_DEMCR_VC_CHKERR (1U << 6) +#define ARMV7M_DEBUG_DEMCR_VC_STATERR (1U << 7) +#define ARMV7M_DEBUG_DEMCR_VC_BUSERR (1U << 8) +#define ARMV7M_DEBUG_DEMCR_VC_INTERR (1U << 9) +#define ARMV7M_DEBUG_DEMCR_VC_HARDERR (1U << 10) +#define ARMV7M_DEBUG_DEMCR_MON_EN (1U << 16) +#define ARMV7M_DEBUG_DEMCR_MON_PEND (1U << 17) +#define ARMV7M_DEBUG_DEMCR_MON_STEP (1U << 18) +#define ARMV7M_DEBUG_DEMCR_MON_REQ (1U << 19) +#define ARMV7M_DEBUG_DEMCR_TRCENA (1U << 24) + uint32_t demcr; +} ARMV7M_DEBUG; + +#define ARMV7M_DWT_BASE 0xe0001000 +#define ARMV7M_SCS_BASE 0xe000e000 +#define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0) +#define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10) +#define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100) +#define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00) +#define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90) +#define ARMV7M_DEBUG_BASE (ARMV7M_SCS_BASE + 0xdf0) + +#define _ARMV7M_DWT \ + ((volatile ARMV7M_DWT *) ARMV7M_DWT_BASE) +#define _ARMV7M_ICTAC \ + ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE) +#define _ARMV7M_SCB \ + ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE) +#define _ARMV7M_Systick \ + ((volatile ARMV7M_Systick *) ARMV7M_SYSTICK_BASE) +#define _ARMV7M_NVIC \ + ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE) +#define _ARMV7M_MPU \ + ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE) +#define _ARMV7M_DEBUG \ + ((volatile ARMV7M_DEBUG *) ARMV7M_DEBUG_BASE) + +#define ARMV7M_VECTOR_MSP 0 +#define ARMV7M_VECTOR_RESET 1 +#define ARMV7M_VECTOR_NMI 2 +#define ARMV7M_VECTOR_HARD_FAULT 3 +#define ARMV7M_VECTOR_MEM_MANAGE 4 +#define ARMV7M_VECTOR_BUS_FAULT 5 +#define ARMV7M_VECTOR_USAGE_FAULT 6 +#define ARMV7M_VECTOR_SVC 11 +#define ARMV7M_VECTOR_DEBUG_MONITOR 12 +#define ARMV7M_VECTOR_PENDSV 14 +#define ARMV7M_VECTOR_SYSTICK 15 +#define ARMV7M_VECTOR_IRQ(n) ((n) + 16) +#define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16) + +#define ARMV7M_EXCEPTION_PRIORITY_LOWEST 255 + +static inline bool _ARMV7M_Is_vector_an_irq( int vector ) +{ + /* External (i.e. non-system) IRQs start after the SysTick vector. */ + return vector > ARMV7M_VECTOR_SYSTICK; +} + +static inline uint32_t _ARMV7M_Get_basepri(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], basepri\n" : [val] "=&r" (val)); + return val; +} + +static inline void _ARMV7M_Set_basepri(uint32_t val) +{ + __asm__ volatile ("msr basepri, %[val]\n" : : [val] "r" (val)); +} + +static inline uint32_t _ARMV7M_Get_primask(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], primask\n" : [val] "=&r" (val)); + return val; +} + +static inline void _ARMV7M_Set_primask(uint32_t val) +{ + __asm__ volatile ("msr primask, %[val]\n" : : [val] "r" (val)); +} + +static inline uint32_t _ARMV7M_Get_faultmask(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], faultmask\n" : [val] "=&r" (val)); + return val; +} + +static inline void _ARMV7M_Set_faultmask(uint32_t val) +{ + __asm__ volatile ("msr faultmask, %[val]\n" : : [val] "r" (val)); +} + +static inline uint32_t _ARMV7M_Get_control(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], control\n" : [val] "=&r" (val)); + return val; +} + +static inline void _ARMV7M_Set_control(uint32_t val) +{ + __asm__ volatile ("msr control, %[val]\n" : : [val] "r" (val)); +} + +static inline uint32_t _ARMV7M_Get_MSP(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], msp\n" : [val] "=&r" (val)); + return val; +} + +static inline void _ARMV7M_Set_MSP(uint32_t val) +{ + __asm__ volatile ("msr msp, %[val]\n" : : [val] "r" (val)); +} + +static inline uint32_t _ARMV7M_Get_PSP(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], psp\n" : [val] "=&r" (val)); + return val; +} + +static inline void _ARMV7M_Set_PSP(uint32_t val) +{ + __asm__ volatile ("msr psp, %[val]\n" : : [val] "r" (val)); +} + +static inline uint32_t _ARMV7M_Get_XPSR(void) +{ + uint32_t val; + __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val)); + return val; +} + +static inline bool _ARMV7M_NVIC_Is_enabled( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + return (_ARMV7M_NVIC->iser [index] & bit) != 0; +} + +static inline void _ARMV7M_NVIC_Set_enable( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + _ARMV7M_NVIC->iser [index] = bit; +} + +static inline void _ARMV7M_NVIC_Clear_enable( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + _ARMV7M_NVIC->icer [index] = bit; +} + +static inline bool _ARMV7M_NVIC_Is_pending( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + return (_ARMV7M_NVIC->ispr [index] & bit) != 0; +} + +static inline void _ARMV7M_NVIC_Set_pending( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + _ARMV7M_NVIC->ispr [index] = bit; +} + +static inline void _ARMV7M_NVIC_Clear_pending( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + _ARMV7M_NVIC->icpr [index] = bit; +} + +static inline bool _ARMV7M_NVIC_Is_active( int irq ) +{ + int index = irq >> 5; + uint32_t bit = 1U << (irq & 0x1f); + + return (_ARMV7M_NVIC->iabr [index] & bit) != 0; +} + +static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority ) +{ + _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority; +} + +static inline int _ARMV7M_NVIC_Get_priority( int irq ) +{ + return _ARMV7M_NVIC->ipr [irq]; +} + +static inline bool _ARMV7M_DWT_Enable_CYCCNT( void ) +{ + uint32_t demcr; + uint32_t dwt_ctrl; + + demcr = _ARMV7M_DEBUG->demcr; + _ARMV7M_DEBUG->demcr = demcr | ARMV7M_DEBUG_DEMCR_TRCENA; + _ARM_Data_synchronization_barrier(); + + dwt_ctrl = _ARMV7M_DWT->ctrl; + if ((dwt_ctrl & ARMV7M_DWT_CTRL_NOCYCCNT) == 0) { + _ARMV7M_DWT->lar = ARMV7M_DWT_LAR_UNLOCK_MAGIC; + _ARM_Data_synchronization_barrier(); + _ARMV7M_DWT->ctrl = dwt_ctrl | ARMV7M_DWT_CTRL_CYCCNTENA; + return true; + } else { + _ARMV7M_DEBUG->demcr = demcr; + return false; + } +} + +int _ARMV7M_Get_exception_priority( int vector ); + +void _ARMV7M_Set_exception_priority( int vector, int priority ); + +ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index ); + +void _ARMV7M_Set_exception_handler( + int index, + ARMV7M_Exception_handler handler +); + +/** + * @brief ARMV7M set exception priority and handler. + */ +void _ARMV7M_Set_exception_priority_and_handler( + int index, + int priority, + ARMV7M_Exception_handler handler +); + +void _ARMV7M_Exception_default( void ); + +void _ARMV7M_Interrupt_service_enter( void ); + +void _ARMV7M_Interrupt_service_leave( void ); + +void _ARMV7M_Pendable_service_call( void ); + +void _ARMV7M_Supervisor_call( void ); + +#endif /* ASM */ + +#endif /* ARM_MULTILIB_ARCH_V7M */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* RTEMS_SCORE_ARMV7M_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h new file mode 100644 index 0000000000..05e236c75a --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h @@ -0,0 +1,702 @@ +/** + * @file + * + * @brief ARM Architecture Support API + */ + +/* + * This include file contains information pertaining to the ARM + * processor. + * + * Copyright (c) 2009, 2017 embedded brains GmbH + * + * Copyright (c) 2007 Ray Xu + * + * Copyright (c) 2006 OAR Corporation + * + * Copyright (c) 2002 Advent Networks, Inc. + * Jay Monkman + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#include +#include + +#if defined(ARM_MULTILIB_ARCH_V4) + +/** + * @defgroup ScoreCPUARM ARM Specific Support + * + * @ingroup ScoreCPU + * + * @brief ARM specific support. + */ +/**@{**/ + +#if defined(__thumb__) && !defined(__thumb2__) + #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg + #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" + #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" + #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) + #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT +#else + #define ARM_SWITCH_REGISTERS + #define ARM_SWITCH_TO_ARM + #define ARM_SWITCH_BACK + #define ARM_SWITCH_OUTPUT + #define ARM_SWITCH_ADDITIONAL_OUTPUT +#endif + +/** + * @name Program Status Register + */ +/**@{**/ + +#define ARM_PSR_N (1 << 31) +#define ARM_PSR_Z (1 << 30) +#define ARM_PSR_C (1 << 29) +#define ARM_PSR_V (1 << 28) +#define ARM_PSR_Q (1 << 27) +#define ARM_PSR_J (1 << 24) +#define ARM_PSR_GE_SHIFT 16 +#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) +#define ARM_PSR_E (1 << 9) +#define ARM_PSR_A (1 << 8) +#define ARM_PSR_I (1 << 7) +#define ARM_PSR_F (1 << 6) +#define ARM_PSR_T (1 << 5) +#define ARM_PSR_M_SHIFT 0 +#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) +#define ARM_PSR_M_USR 0x10 +#define ARM_PSR_M_FIQ 0x11 +#define ARM_PSR_M_IRQ 0x12 +#define ARM_PSR_M_SVC 0x13 +#define ARM_PSR_M_ABT 0x17 +#define ARM_PSR_M_HYP 0x1a +#define ARM_PSR_M_UND 0x1b +#define ARM_PSR_M_SYS 0x1f + +/** @} */ + +/** @} */ + +#endif /* defined(ARM_MULTILIB_ARCH_V4) */ + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * The ARM uses the PIC interrupt model. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +#define CPU_HARDWARE_FP FALSE + +#define CPU_SOFTWARE_FP FALSE + +#define CPU_ALL_TASKS_ARE_FP FALSE + +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE + +#if defined(ARM_MULTILIB_HAS_WFI) + #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE +#else + #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE +#endif + +#define CPU_STACK_GROWS_UP FALSE + +#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) + #define CPU_CACHE_LINE_BYTES 64 +#else + #define CPU_CACHE_LINE_BYTES 32 +#endif + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +#define CPU_MODES_INTERRUPT_MASK 0x1 + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +#define CPU_STACK_MINIMUM_SIZE (1024 * 4) + +/* AAPCS, section 4.1, Fundamental Data Types */ +#define CPU_SIZEOF_POINTER 4 + +/* AAPCS, section 4.1, Fundamental Data Types */ +#define CPU_ALIGNMENT 8 + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* AAPCS, section 4.3.1, Aggregates */ +#define CPU_PARTITION_ALIGNMENT 4 + +/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ +#define CPU_STACK_ALIGNMENT 8 + +/* + * Bitfield handler macros. + * + * If we had a particularly fast function for finding the first + * bit set in a word, it would go here. Since we don't (*), we'll + * just use the universal macros. + * + * (*) On ARM V5 and later, there's a CLZ function which could be + * used to implement much quicker than the default macro. + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#define CPU_MAXIMUM_PROCESSORS 32 + +/** @} */ + +#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER + #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 +#endif + +#ifdef ARM_MULTILIB_VFP + #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 +#endif + +#ifdef ARM_MULTILIB_ARCH_V4 + #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40 +#endif + +#ifdef RTEMS_SMP + #if defined(ARM_MULTILIB_VFP) + #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 + #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER) + #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 + #else + #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44 + #endif +#endif + +#define ARM_EXCEPTION_FRAME_SIZE 80 + +#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 + +#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 + +#define ARM_VFP_CONTEXT_SIZE 264 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +typedef struct { +#if defined(ARM_MULTILIB_ARCH_V4) + uint32_t register_r4; + uint32_t register_r5; + uint32_t register_r6; + uint32_t register_r7; + uint32_t register_r8; + uint32_t register_r9; + uint32_t register_r10; + uint32_t register_fp; + uint32_t register_sp; + uint32_t register_lr; + uint32_t isr_dispatch_disable; +#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) + uint32_t register_r4; + uint32_t register_r5; + uint32_t register_r6; + uint32_t register_r7; + uint32_t register_r8; + uint32_t register_r9; + uint32_t register_r10; + uint32_t register_r11; + void *register_lr; + void *register_sp; + uint32_t isr_nest_level; +#else + void *register_sp; +#endif +#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER + uint32_t thread_id; +#endif +#ifdef ARM_MULTILIB_VFP + uint64_t register_d8; + uint64_t register_d9; + uint64_t register_d10; + uint64_t register_d11; + uint64_t register_d12; + uint64_t register_d13; + uint64_t register_d14; + uint64_t register_d15; +#endif +#ifdef RTEMS_SMP + volatile bool is_executing; +#endif +} Context_Control; + +typedef struct { + /* Not supported */ +} Context_Control_fp; + +static inline void _ARM_Data_memory_barrier( void ) +{ +#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS + __asm__ volatile ( "dmb" : : : "memory" ); +#else + RTEMS_COMPILER_MEMORY_BARRIER(); +#endif +} + +static inline void _ARM_Data_synchronization_barrier( void ) +{ +#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS + __asm__ volatile ( "dsb" : : : "memory" ); +#else + RTEMS_COMPILER_MEMORY_BARRIER(); +#endif +} + +static inline void _ARM_Instruction_synchronization_barrier( void ) +{ +#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS + __asm__ volatile ( "isb" : : : "memory" ); +#else + RTEMS_COMPILER_MEMORY_BARRIER(); +#endif +} + +static inline uint32_t arm_interrupt_disable( void ) +{ + uint32_t level; + +#if defined(ARM_MULTILIB_ARCH_V4) + uint32_t arm_switch_reg; + + /* + * Disable only normal interrupts (IRQ). + * + * In order to support fast interrupts (FIQ) such that they can do something + * useful, we have to disable the operating system support for FIQs. Having + * operating system support for them would require that FIQs are disabled + * during critical sections of the operating system and application. At this + * level IRQs and FIQs would be equal. It is true that FIQs could interrupt + * the non critical sections of IRQs, so here they would have a small + * advantage. Without operating system support, the FIQs can execute at any + * time (of course not during the service of another FIQ). If someone needs + * operating system support for a FIQ, she can trigger a software interrupt and + * service the request in a two-step process. + */ + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[level], cpsr\n" + "orr %[arm_switch_reg], %[level], #0x80\n" + "msr cpsr, %[arm_switch_reg]\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) + ); +#elif defined(ARM_MULTILIB_ARCH_V7M) + uint32_t basepri = 0x80; + + __asm__ volatile ( + "mrs %[level], basepri\n" + "msr basepri_max, %[basepri]\n" + : [level] "=&r" (level) + : [basepri] "r" (basepri) + ); +#endif + + return level; +} + +static inline void arm_interrupt_enable( uint32_t level ) +{ +#if defined(ARM_MULTILIB_ARCH_V4) + ARM_SWITCH_REGISTERS; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "msr cpsr, %[level]\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [level] "r" (level) + ); +#elif defined(ARM_MULTILIB_ARCH_V7M) + __asm__ volatile ( + "msr basepri, %[level]\n" + : + : [level] "r" (level) + ); +#endif +} + +static inline void arm_interrupt_flash( uint32_t level ) +{ +#if defined(ARM_MULTILIB_ARCH_V4) + uint32_t arm_switch_reg; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[arm_switch_reg], cpsr\n" + "msr cpsr, %[level]\n" + "msr cpsr, %[arm_switch_reg]\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg) + : [level] "r" (level) + ); +#elif defined(ARM_MULTILIB_ARCH_V7M) + uint32_t basepri; + + __asm__ volatile ( + "mrs %[basepri], basepri\n" + "msr basepri, %[level]\n" + "msr basepri, %[basepri]\n" + : [basepri] "=&r" (basepri) + : [level] "r" (level) + ); +#endif +} + +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + _isr_cookie = arm_interrupt_disable(); \ + } while (0) + +#define _CPU_ISR_Enable( _isr_cookie ) \ + arm_interrupt_enable( _isr_cookie ) + +#define _CPU_ISR_Flash( _isr_cookie ) \ + arm_interrupt_flash( _isr_cookie ) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ +#if defined(ARM_MULTILIB_ARCH_V4) + return ( level & 0x80 ) == 0; +#elif defined(ARM_MULTILIB_ARCH_V7M) + return level == 0; +#endif +} + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->register_sp + +#ifdef RTEMS_SMP + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + { + return context->is_executing; + } + + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + context->is_executing = is_executing; + } +#endif + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } while (0) + +#define _CPU_Fatal_halt( _source, _err ) \ + do { \ + uint32_t _level; \ + uint32_t _error = _err; \ + _CPU_ISR_Disable( _level ); \ + (void) _level; \ + __asm__ volatile ("mov r0, %0\n" \ + : "=r" (_error) \ + : "0" (_error) \ + : "r0" ); \ + while (1); \ + } while (0); + +/** + * @brief CPU initialization. + */ +void _CPU_Initialize( void ); + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @brief CPU switch context. + */ +void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); + +void _CPU_Context_restore( Context_Control *new_context ) + RTEMS_NO_RETURN; + +#if defined(ARM_MULTILIB_ARCH_V7M) + void _ARMV7M_Start_multitasking( Context_Control *heir ) + RTEMS_NO_RETURN; + #define _CPU_Start_multitasking _ARMV7M_Start_multitasking +#endif + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +#ifdef RTEMS_SMP + uint32_t _CPU_SMP_Initialize( void ); + + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + void _CPU_SMP_Prepare_start_multitasking( void ); + + static inline uint32_t _CPU_SMP_Get_current_processor( void ) + { + uint32_t mpidr; + + /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ + __asm__ volatile ( + "mrc p15, 0, %[mpidr], c0, c0, 5\n" + : [mpidr] "=&r" (mpidr) + ); + + return mpidr & 0xffU; + } + + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + static inline void _ARM_Send_event( void ) + { + __asm__ volatile ( "sev" : : : "memory" ); + } + + static inline void _ARM_Wait_for_event( void ) + { + __asm__ volatile ( "wfe" : : : "memory" ); + } + + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + _ARM_Data_synchronization_barrier(); + _ARM_Send_event(); + } + + static inline void _CPU_SMP_Processor_event_receive( void ) + { + _ARM_Wait_for_event(); + _ARM_Data_memory_barrier(); + } +#endif + + +static inline uint32_t CPU_swap_u32( uint32_t value ) +{ +#if defined(__thumb2__) + __asm__ volatile ( + "rev %0, %0" + : "=r" (value) + : "0" (value) + ); + return value; +#elif defined(__thumb__) + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +#else + uint32_t tmp = value; /* make compiler warnings go away */ + __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" + "BIC %1, %1, #0xff0000\n" + "MOV %0, %0, ROR #8\n" + "EOR %0, %0, %1, LSR #8\n" + : "=r" (value), "=r" (tmp) + : "0" (value), "1" (tmp)); + return value; +#endif +} + +static inline uint16_t CPU_swap_u16( uint16_t value ) +{ +#if defined(__thumb2__) + __asm__ volatile ( + "rev16 %0, %0" + : "=r" (value) + : "0" (value) + ); + return value; +#else + return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); +#endif +} + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +#if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE + void *_CPU_Thread_Idle_body( uintptr_t ignored ); +#endif + +/** @} */ + +/** + * @addtogroup ScoreCPUARM + */ +/**@{**/ + +#if defined(ARM_MULTILIB_ARCH_V4) + +typedef enum { + ARM_EXCEPTION_RESET = 0, + ARM_EXCEPTION_UNDEF = 1, + ARM_EXCEPTION_SWI = 2, + ARM_EXCEPTION_PREF_ABORT = 3, + ARM_EXCEPTION_DATA_ABORT = 4, + ARM_EXCEPTION_RESERVED = 5, + ARM_EXCEPTION_IRQ = 6, + ARM_EXCEPTION_FIQ = 7, + MAX_EXCEPTIONS = 8, + ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff +} Arm_symbolic_exception_name; + +#endif /* defined(ARM_MULTILIB_ARCH_V4) */ + +typedef struct { + uint32_t register_fpexc; + uint32_t register_fpscr; + uint64_t register_d0; + uint64_t register_d1; + uint64_t register_d2; + uint64_t register_d3; + uint64_t register_d4; + uint64_t register_d5; + uint64_t register_d6; + uint64_t register_d7; + uint64_t register_d8; + uint64_t register_d9; + uint64_t register_d10; + uint64_t register_d11; + uint64_t register_d12; + uint64_t register_d13; + uint64_t register_d14; + uint64_t register_d15; + uint64_t register_d16; + uint64_t register_d17; + uint64_t register_d18; + uint64_t register_d19; + uint64_t register_d20; + uint64_t register_d21; + uint64_t register_d22; + uint64_t register_d23; + uint64_t register_d24; + uint64_t register_d25; + uint64_t register_d26; + uint64_t register_d27; + uint64_t register_d28; + uint64_t register_d29; + uint64_t register_d30; + uint64_t register_d31; +} ARM_VFP_context; + +typedef struct { + uint32_t register_r0; + uint32_t register_r1; + uint32_t register_r2; + uint32_t register_r3; + uint32_t register_r4; + uint32_t register_r5; + uint32_t register_r6; + uint32_t register_r7; + uint32_t register_r8; + uint32_t register_r9; + uint32_t register_r10; + uint32_t register_r11; + uint32_t register_r12; + uint32_t register_sp; + void *register_lr; + void *register_pc; +#if defined(ARM_MULTILIB_ARCH_V4) + uint32_t register_cpsr; + Arm_symbolic_exception_name vector; +#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) + uint32_t register_xpsr; + uint32_t vector; +#endif + const ARM_VFP_context *vfp_context; + uint32_t reserved_for_stack_alignment; +} CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +void _ARM_Exception_default( CPU_Exception_frame *frame ); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/arm/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..c430911373 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/cpu_asm.h @@ -0,0 +1,39 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM Assembler Support API + */ + +/* + * COPYRIGHT (c) 2002 by Advent Networks, Inc. + * Jay Monkman + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * This file is the include file for cpu_asm.S + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + + +/* Registers saved in context switch: */ +.set REG_CPSR, 0 +.set REG_R4, 4 +.set REG_R5, 8 +.set REG_R6, 12 +.set REG_R7, 16 +.set REG_R8, 20 +.set REG_R9, 24 +.set REG_R10, 28 +.set REG_R11, 32 +.set REG_SP, 36 +.set REG_LR, 40 +.set REG_PC, 44 +.set SIZE_REGS, REG_PC + 4 + +#endif diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..0885c2ef39 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h @@ -0,0 +1,111 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013, 2016 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifdef ARM_MULTILIB_ARCH_V4 + +#if defined(ARM_MULTILIB_VFP_D32) +#define CPU_INTERRUPT_FRAME_SIZE 240 +#elif defined(ARM_MULTILIB_VFP) +#define CPU_INTERRUPT_FRAME_SIZE 112 +#else +#define CPU_INTERRUPT_FRAME_SIZE 40 +#endif + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ARM_MULTILIB_ARCH_V4 + +typedef struct { +#ifdef ARM_MULTILIB_VFP + uint32_t fpscr; +#ifdef ARM_MULTILIB_VFP_D32 + double d16; + double d17; + double d18; + double d19; + double d20; + double d21; + double d22; + double d23; + double d24; + double d25; + double d26; + double d27; + double d28; + double d29; + double d30; + double d31; +#endif /* ARM_MULTILIB_VFP_D32 */ + double d0; + double d1; + double d2; + double d3; + double d4; + double d5; + double d6; + double d7; +#endif /* ARM_MULTILIB_VFP */ + uint32_t r9; + uint32_t lr; + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t return_pc; + uint32_t return_cpsr; + uint32_t r7; + uint32_t r12; +} CPU_Interrupt_frame; + +#ifdef RTEMS_SMP + +static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void ) +{ + struct Per_CPU_Control *cpu_self; + + /* Use PL1 only Thread ID Register (TPIDRPRW) */ + __asm__ volatile ( + "mrc p15, 0, %0, c13, c0, 4" + : "=r" ( cpu_self ) + ); + + return cpu_self; +} + +#define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control() + +#endif /* RTEMS_SMP */ + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/types.h b/cpukit/score/cpu/arm/include/rtems/score/types.h new file mode 100644 index 0000000000..37a56df029 --- /dev/null +++ b/cpukit/score/cpu/arm/include/rtems/score/types.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @brief ARM Architecture Types API + */ + +/* + * This include file contains type definitions pertaining to the + * arm processor family. + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/arm/preinstall.am b/cpukit/score/cpu/arm/preinstall.am deleted file mode 100644 index 3bdbb63561..0000000000 --- a/cpukit/score/cpu/arm/preinstall.am +++ /dev/null @@ -1,70 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/arm.h: rtems/score/arm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/arm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/arm.h - -$(PROJECT_INCLUDE)/rtems/score/armv4.h: rtems/score/armv4.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/armv4.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/armv4.h - -$(PROJECT_INCLUDE)/rtems/score/armv7m.h: rtems/score/armv7m.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/armv7m.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/armv7m.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: include/libcpu/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h - diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h deleted file mode 100644 index f72df32325..0000000000 --- a/cpukit/score/cpu/arm/rtems/asm.h +++ /dev/null @@ -1,231 +0,0 @@ -/** - * @file - * - * @brief ARM Assembler Support API - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include - -/** - * @defgroup ScoreCPUARMASM ARM Assembler Support - * - * @ingroup ScoreCPU - * - * @brief ARM Assembler Support - */ -/**@{**/ - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) -#define r14 REG(r14) -#define r15 REG(r15) - -#define CPSR REG(CPSR) - -#define SPSR REG(SPSR) - -#define NUM_IRQ_VECTOR 6 // IRQ number -#define NUM_FIQ_VECTOR 7 // IRQ number - // // -#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1 -#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 -#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 -#define CPSR_FIQ_MODE 0x11 -#define CPSR_IRQ_MODE 0x12 -#define CPSR_SUPERVISOR_MODE 0x13 -#define CPSR_UNDEF_MODE 0x1B - -#define CPSR_MODE_BITS 0x1F - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#define FUNCTION_THUMB_ENTRY(name) \ - .thumb; \ - .thumb_func; \ - .align 2; \ - .globl name; \ - .type name, %function; \ - name: - -#define FUNCTION_ENTRY(name) \ - .align 2; \ - .globl name; \ - .type name, %function; \ - name: - -#define FUNCTION_END(name) \ - .size name, . - name - -#if defined(ARM_MULTILIB_ARCH_V7M) - #define DEFINE_FUNCTION_ARM(name) \ - .thumb_func ; .globl name ; name: -#elif defined(__thumb__) - #define DEFINE_FUNCTION_ARM(name) \ - .thumb_func ; .globl name ; name: ; bx pc ; \ - .arm ; .globl name ## _arm ; name ## _arm: -#else - #define DEFINE_FUNCTION_ARM(name) \ - .globl name ; name: ; .globl name ## _arm ; name ## _arm: -#endif - -.macro SWITCH_FROM_THUMB_TO_ARM -#ifdef __thumb__ -.align 2 - bx pc -.arm -#endif /* __thumb__ */ -.endm - -.macro SWITCH_FROM_ARM_TO_THUMB REG -#ifdef __thumb__ - add \REG, pc, #1 - bx \REG -.thumb -#endif /* __thumb__ */ -.endm - -.macro SWITCH_FROM_THUMB_2_TO_ARM -#ifdef __thumb2__ -.align 2 - bx pc -.arm -#endif /* __thumb__ */ -.endm - -.macro SWITCH_FROM_ARM_TO_THUMB_2 REG -#ifdef __thumb2__ - add \REG, pc, #1 - bx \REG -.thumb -#endif /* __thumb__ */ -.endm - -.macro BLX_TO_THUMB_1 TARGET -#if defined(__thumb__) && !defined(__thumb2__) - add lr, pc, #1 - bx lr -.thumb - bl \TARGET -.align 2 - bx pc -.arm -#else - bl \TARGET -#endif -.endm - -.macro GET_SELF_CPU_CONTROL REG -#ifdef RTEMS_SMP - /* Use PL1 only Thread ID Register (TPIDRPRW) */ - mrc p15, 0, \REG, c13, c0, 4 -#else - ldr \REG, =_Per_CPU_Information -#endif -.endm - -/** @} */ - -#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h deleted file mode 100755 index f08da1dc57..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * @file - * - * @brief ARM Assembler Support API - */ - -/* - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_ARM_H -#define _RTEMS_SCORE_ARM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - #define CPU_MODEL_NAME "ARMv7M" - #define ARM_MULTILIB_ARCH_V7M -#elif defined(__ARM_ARCH_6M__) - #define CPU_MODEL_NAME "ARMv6M" - #define ARM_MULTILIB_ARCH_V6M -#else - #define CPU_MODEL_NAME "ARMv4" - #define ARM_MULTILIB_ARCH_V4 -#endif - -#if defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) \ - || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) - #define ARM_MULTILIB_HAS_WFI - #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE - #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS -#endif - -#if defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) - #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER -#endif - -#if defined(__ARM_ARCH_7A__) - #define ARM_MULTILIB_CACHE_LINE_MAX_64 -#endif - -#if defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) - #define ARM_MULTILIB_HAS_CPACR -#endif - -#if !defined(__SOFTFP__) - #if defined(__ARM_NEON__) - #define ARM_MULTILIB_VFP_D32 - #elif defined(__VFP_FP__) - #define ARM_MULTILIB_VFP_D16 - #else - #error "FPU support not implemented" - #endif -#endif - -#if defined(ARM_MULTILIB_VFP_D16) \ - || defined(ARM_MULTILIB_VFP_D32) - #define ARM_MULTILIB_VFP -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "ARM" - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_ARM_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/armv4.h b/cpukit/score/cpu/arm/rtems/score/armv4.h deleted file mode 100644 index caeaa3e553..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/armv4.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef RTEMS_SCORE_ARMV4_H -#define RTEMS_SCORE_ARMV4_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef ARM_MULTILIB_ARCH_V4 - -void bsp_interrupt_dispatch( void ); - -void _ARMV4_Exception_interrupt( void ); - -typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame ); - -void _ARMV4_Exception_data_abort_set_handler( - ARMV4_Exception_abort_handler handler -); - -void _ARMV4_Exception_data_abort( void ); - -void _ARMV4_Exception_prefetch_abort_set_handler( - ARMV4_Exception_abort_handler handler -); - -void _ARMV4_Exception_prefetch_abort( void ); - -void _ARMV4_Exception_undef_default( void ); - -void _ARMV4_Exception_swi_default( void ); - -void _ARMV4_Exception_data_abort_default( void ); - -void _ARMV4_Exception_pref_abort_default( void ); - -void _ARMV4_Exception_reserved_default( void ); - -void _ARMV4_Exception_irq_default( void ); - -void _ARMV4_Exception_fiq_default( void ); - -static inline uint32_t _ARMV4_Status_irq_enable( void ) -{ - uint32_t arm_switch_reg; - uint32_t psr; - - RTEMS_COMPILER_MEMORY_BARRIER(); - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[psr], cpsr\n" - "bic %[arm_switch_reg], %[psr], #0x80\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr) - ); - - return psr; -} - -static inline void _ARMV4_Status_restore( uint32_t psr ) -{ - ARM_SWITCH_REGISTERS; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "msr cpsr, %[psr]\n" - ARM_SWITCH_BACK - : ARM_SWITCH_OUTPUT - : [psr] "r" (psr) - ); - - RTEMS_COMPILER_MEMORY_BARRIER(); -} - -#endif /* ARM_MULTILIB_ARCH_V4 */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* RTEMS_SCORE_ARMV4_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/armv7m.h b/cpukit/score/cpu/arm/rtems/score/armv7m.h deleted file mode 100644 index a6cc8a34ac..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/armv7m.h +++ /dev/null @@ -1,620 +0,0 @@ -/** - * @file - * - * @brief ARMV7M Architecture Support - */ - -/* - * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef RTEMS_SCORE_ARMV7M_H -#define RTEMS_SCORE_ARMV7M_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef ARM_MULTILIB_ARCH_V7M - -/* Coprocessor Access Control Register, CPACR */ -#define ARMV7M_CPACR 0xe000ed88 - -#ifndef ASM - -typedef struct { - uint32_t reserved_0; - uint32_t ictr; - uint32_t actlr; - uint32_t reserved_1; -} ARMV7M_ICTAC; - -typedef void (*ARMV7M_Exception_handler)(void); - -typedef struct { - uint32_t register_r0; - uint32_t register_r1; - uint32_t register_r2; - uint32_t register_r3; - uint32_t register_r12; - void *register_lr; - void *register_pc; - uint32_t register_xpsr; -#ifdef ARM_MULTILIB_VFP - uint32_t register_s0; - uint32_t register_s1; - uint32_t register_s2; - uint32_t register_s3; - uint32_t register_s4; - uint32_t register_s5; - uint32_t register_s6; - uint32_t register_s7; - uint32_t register_s8; - uint32_t register_s9; - uint32_t register_s10; - uint32_t register_s11; - uint32_t register_s12; - uint32_t register_s13; - uint32_t register_s14; - uint32_t register_s15; - uint32_t register_fpscr; - uint32_t reserved; -#endif -} ARMV7M_Exception_frame; - -typedef struct { - uint32_t comp; - uint32_t mask; - uint32_t function; - uint32_t reserved; -} ARMV7M_DWT_comparator; - -typedef struct { -#define ARMV7M_DWT_CTRL_NOCYCCNT (1U << 25) -#define ARMV7M_DWT_CTRL_CYCCNTENA (1U << 0) - uint32_t ctrl; - uint32_t cyccnt; - uint32_t cpicnt; - uint32_t exccnt; - uint32_t sleepcnt; - uint32_t lsucnt; - uint32_t foldcnt; - uint32_t pcsr; - ARMV7M_DWT_comparator comparator[249]; -#define ARMV7M_DWT_LAR_UNLOCK_MAGIC 0xc5acce55U - uint32_t lar; - uint32_t lsr; -} ARMV7M_DWT; - -typedef struct { - uint32_t cpuid; - -#define ARMV7M_SCB_ICSR_NMIPENDSET (1U << 31) -#define ARMV7M_SCB_ICSR_PENDSVSET (1U << 28) -#define ARMV7M_SCB_ICSR_PENDSVCLR (1U << 27) -#define ARMV7M_SCB_ICSR_PENDSTSET (1U << 26) -#define ARMV7M_SCB_ICSR_PENDSTCLR (1U << 25) -#define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23) -#define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22) -#define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU) -#define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11) -#define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU) - uint32_t icsr; - - ARMV7M_Exception_handler *vtor; - -#define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16) -#define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15) -#define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8 -#define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \ - ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) -#define ARMV7M_SCB_AIRCR_PRIGROUP(val) \ - (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) -#define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \ - (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) -#define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \ - (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val)) -#define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2) -#define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1) -#define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0) - uint32_t aircr; - - uint32_t scr; - uint32_t ccr; - uint8_t shpr [12]; - -#define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18) -#define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17) -#define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16) - uint32_t shcsr; - - uint32_t cfsr; - uint32_t hfsr; - uint32_t dfsr; - uint32_t mmfar; - uint32_t bfar; - uint32_t afsr; - uint32_t reserved_e000ed40[18]; - uint32_t cpacr; - uint32_t reserved_e000ed8c[106]; - uint32_t fpccr; - uint32_t fpcar; - uint32_t fpdscr; - uint32_t mvfr0; - uint32_t mvfr1; -} ARMV7M_SCB; - -typedef struct { -#define ARMV7M_SYSTICK_CSR_COUNTFLAG (1U << 16) -#define ARMV7M_SYSTICK_CSR_CLKSOURCE (1U << 2) -#define ARMV7M_SYSTICK_CSR_TICKINT (1U << 1) -#define ARMV7M_SYSTICK_CSR_ENABLE (1U << 0) - uint32_t csr; - - uint32_t rvr; - uint32_t cvr; - -#define ARMV7M_SYSTICK_CALIB_NOREF (1U << 31) -#define ARMV7M_SYSTICK_CALIB_SKEW (1U << 30) -#define ARMV7M_SYSTICK_CALIB_TENMS_GET(reg) ((reg) & 0xffffffU) - uint32_t calib; -} ARMV7M_Systick; - -typedef struct { - uint32_t iser [8]; - uint32_t reserved_0 [24]; - uint32_t icer [8]; - uint32_t reserved_1 [24]; - uint32_t ispr [8]; - uint32_t reserved_2 [24]; - uint32_t icpr [8]; - uint32_t reserved_3 [24]; - uint32_t iabr [8]; - uint32_t reserved_4 [56]; - uint8_t ipr [240]; - uint32_t reserved_5 [644]; - uint32_t stir; -} ARMV7M_NVIC; - -typedef struct { -#define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU) -#define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU) -#define ARMV7M_MPU_TYPE_SEPARATE (1U << 0) - uint32_t type; - -#define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2) -#define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1) -#define ARMV7M_MPU_CTRL_ENABLE (1U << 0) - uint32_t ctrl; - - uint32_t rnr; - -#define ARMV7M_MPU_RBAR_ADDR_SHIFT 5 -#define ARMV7M_MPU_RBAR_ADDR_MASK \ - ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT) -#define ARMV7M_MPU_RBAR_ADDR(val) \ - (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK) -#define ARMV7M_MPU_RBAR_ADDR_GET(reg) \ - (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT) -#define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \ - (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val)) -#define ARMV7M_MPU_RBAR_VALID (1U << 4) -#define ARMV7M_MPU_RBAR_REGION_SHIFT 0 -#define ARMV7M_MPU_RBAR_REGION_MASK \ - ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT) -#define ARMV7M_MPU_RBAR_REGION(val) \ - (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK) -#define ARMV7M_MPU_RBAR_REGION_GET(reg) \ - (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT) -#define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \ - (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val)) - uint32_t rbar; - -#define ARMV7M_MPU_RASR_XN (1U << 28) -#define ARMV7M_MPU_RASR_AP_SHIFT 24 -#define ARMV7M_MPU_RASR_AP_MASK \ - ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT) -#define ARMV7M_MPU_RASR_AP(val) \ - (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK) -#define ARMV7M_MPU_RASR_AP_GET(reg) \ - (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT) -#define ARMV7M_MPU_RASR_AP_SET(reg, val) \ - (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val)) -#define ARMV7M_MPU_RASR_TEX_SHIFT 19 -#define ARMV7M_MPU_RASR_TEX_MASK \ - ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT) -#define ARMV7M_MPU_RASR_TEX(val) \ - (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK) -#define ARMV7M_MPU_RASR_TEX_GET(reg) \ - (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT) -#define ARMV7M_MPU_RASR_TEX_SET(reg, val) \ - (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val)) -#define ARMV7M_MPU_RASR_S (1U << 18) -#define ARMV7M_MPU_RASR_C (1U << 17) -#define ARMV7M_MPU_RASR_B (1U << 16) -#define ARMV7M_MPU_RASR_SRD_SHIFT 8 -#define ARMV7M_MPU_RASR_SRD_MASK \ - ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT) -#define ARMV7M_MPU_RASR_SRD(val) \ - (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK) -#define ARMV7M_MPU_RASR_SRD_GET(reg) \ - (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT) -#define ARMV7M_MPU_RASR_SRD_SET(reg, val) \ - (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val)) -#define ARMV7M_MPU_RASR_SIZE_SHIFT 1 -#define ARMV7M_MPU_RASR_SIZE_MASK \ - ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT) -#define ARMV7M_MPU_RASR_SIZE(val) \ - (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK) -#define ARMV7M_MPU_RASR_SIZE_GET(reg) \ - (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT) -#define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \ - (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val)) -#define ARMV7M_MPU_RASR_ENABLE (1U << 0) - uint32_t rasr; - - uint32_t rbar_a1; - uint32_t rasr_a1; - uint32_t rbar_a2; - uint32_t rasr_a2; - uint32_t rbar_a3; - uint32_t rasr_a3; -} ARMV7M_MPU; - -typedef enum { - ARMV7M_MPU_AP_PRIV_NO_USER_NO, - ARMV7M_MPU_AP_PRIV_RW_USER_NO, - ARMV7M_MPU_AP_PRIV_RW_USER_RO, - ARMV7M_MPU_AP_PRIV_RW_USER_RW, - ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5, - ARMV7M_MPU_AP_PRIV_RO_USER_RO, -} ARMV7M_MPU_Access_permissions; - -typedef enum { - ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO) - | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN, - ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) - | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B, - ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) - | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B, - ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO) - | ARMV7M_MPU_RASR_C, - ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO) - | ARMV7M_MPU_RASR_C, - ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) - | ARMV7M_MPU_RASR_XN, -} ARMV7M_MPU_Attributes; - -typedef enum { - ARMV7M_MPU_SIZE_32_B = 0x4, - ARMV7M_MPU_SIZE_64_B, - ARMV7M_MPU_SIZE_128_B, - ARMV7M_MPU_SIZE_256_B, - ARMV7M_MPU_SIZE_512_B, - ARMV7M_MPU_SIZE_1_KB, - ARMV7M_MPU_SIZE_2_KB, - ARMV7M_MPU_SIZE_4_KB, - ARMV7M_MPU_SIZE_8_KB, - ARMV7M_MPU_SIZE_16_KB, - ARMV7M_MPU_SIZE_32_KB, - ARMV7M_MPU_SIZE_64_KB, - ARMV7M_MPU_SIZE_128_KB, - ARMV7M_MPU_SIZE_256_KB, - ARMV7M_MPU_SIZE_512_KB, - ARMV7M_MPU_SIZE_1_MB, - ARMV7M_MPU_SIZE_2_MB, - ARMV7M_MPU_SIZE_4_MB, - ARMV7M_MPU_SIZE_8_MB, - ARMV7M_MPU_SIZE_16_MB, - ARMV7M_MPU_SIZE_32_MB, - ARMV7M_MPU_SIZE_64_MB, - ARMV7M_MPU_SIZE_128_MB, - ARMV7M_MPU_SIZE_256_MB, - ARMV7M_MPU_SIZE_512_MB, - ARMV7M_MPU_SIZE_1_GB, - ARMV7M_MPU_SIZE_2_GB, - ARMV7M_MPU_SIZE_4_GB -} ARMV7M_MPU_Size; - -typedef struct { - uint32_t rbar; - uint32_t rasr; -} ARMV7M_MPU_Region; - -#define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \ - { \ - ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \ - | ARMV7M_MPU_RBAR_VALID \ - | ARMV7M_MPU_RBAR_REGION(idx), \ - ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \ - } - -#define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \ - { \ - ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \ - 0 \ - } - -typedef struct { - uint32_t dhcsr; - uint32_t dcrsr; - uint32_t dcrdr; -#define ARMV7M_DEBUG_DEMCR_VC_CORERESET (1U << 0) -#define ARMV7M_DEBUG_DEMCR_VC_MMERR (1U << 4) -#define ARMV7M_DEBUG_DEMCR_VC_NOCPERR (1U << 5) -#define ARMV7M_DEBUG_DEMCR_VC_CHKERR (1U << 6) -#define ARMV7M_DEBUG_DEMCR_VC_STATERR (1U << 7) -#define ARMV7M_DEBUG_DEMCR_VC_BUSERR (1U << 8) -#define ARMV7M_DEBUG_DEMCR_VC_INTERR (1U << 9) -#define ARMV7M_DEBUG_DEMCR_VC_HARDERR (1U << 10) -#define ARMV7M_DEBUG_DEMCR_MON_EN (1U << 16) -#define ARMV7M_DEBUG_DEMCR_MON_PEND (1U << 17) -#define ARMV7M_DEBUG_DEMCR_MON_STEP (1U << 18) -#define ARMV7M_DEBUG_DEMCR_MON_REQ (1U << 19) -#define ARMV7M_DEBUG_DEMCR_TRCENA (1U << 24) - uint32_t demcr; -} ARMV7M_DEBUG; - -#define ARMV7M_DWT_BASE 0xe0001000 -#define ARMV7M_SCS_BASE 0xe000e000 -#define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0) -#define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10) -#define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100) -#define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00) -#define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90) -#define ARMV7M_DEBUG_BASE (ARMV7M_SCS_BASE + 0xdf0) - -#define _ARMV7M_DWT \ - ((volatile ARMV7M_DWT *) ARMV7M_DWT_BASE) -#define _ARMV7M_ICTAC \ - ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE) -#define _ARMV7M_SCB \ - ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE) -#define _ARMV7M_Systick \ - ((volatile ARMV7M_Systick *) ARMV7M_SYSTICK_BASE) -#define _ARMV7M_NVIC \ - ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE) -#define _ARMV7M_MPU \ - ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE) -#define _ARMV7M_DEBUG \ - ((volatile ARMV7M_DEBUG *) ARMV7M_DEBUG_BASE) - -#define ARMV7M_VECTOR_MSP 0 -#define ARMV7M_VECTOR_RESET 1 -#define ARMV7M_VECTOR_NMI 2 -#define ARMV7M_VECTOR_HARD_FAULT 3 -#define ARMV7M_VECTOR_MEM_MANAGE 4 -#define ARMV7M_VECTOR_BUS_FAULT 5 -#define ARMV7M_VECTOR_USAGE_FAULT 6 -#define ARMV7M_VECTOR_SVC 11 -#define ARMV7M_VECTOR_DEBUG_MONITOR 12 -#define ARMV7M_VECTOR_PENDSV 14 -#define ARMV7M_VECTOR_SYSTICK 15 -#define ARMV7M_VECTOR_IRQ(n) ((n) + 16) -#define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16) - -#define ARMV7M_EXCEPTION_PRIORITY_LOWEST 255 - -static inline bool _ARMV7M_Is_vector_an_irq( int vector ) -{ - /* External (i.e. non-system) IRQs start after the SysTick vector. */ - return vector > ARMV7M_VECTOR_SYSTICK; -} - -static inline uint32_t _ARMV7M_Get_basepri(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], basepri\n" : [val] "=&r" (val)); - return val; -} - -static inline void _ARMV7M_Set_basepri(uint32_t val) -{ - __asm__ volatile ("msr basepri, %[val]\n" : : [val] "r" (val)); -} - -static inline uint32_t _ARMV7M_Get_primask(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], primask\n" : [val] "=&r" (val)); - return val; -} - -static inline void _ARMV7M_Set_primask(uint32_t val) -{ - __asm__ volatile ("msr primask, %[val]\n" : : [val] "r" (val)); -} - -static inline uint32_t _ARMV7M_Get_faultmask(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], faultmask\n" : [val] "=&r" (val)); - return val; -} - -static inline void _ARMV7M_Set_faultmask(uint32_t val) -{ - __asm__ volatile ("msr faultmask, %[val]\n" : : [val] "r" (val)); -} - -static inline uint32_t _ARMV7M_Get_control(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], control\n" : [val] "=&r" (val)); - return val; -} - -static inline void _ARMV7M_Set_control(uint32_t val) -{ - __asm__ volatile ("msr control, %[val]\n" : : [val] "r" (val)); -} - -static inline uint32_t _ARMV7M_Get_MSP(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], msp\n" : [val] "=&r" (val)); - return val; -} - -static inline void _ARMV7M_Set_MSP(uint32_t val) -{ - __asm__ volatile ("msr msp, %[val]\n" : : [val] "r" (val)); -} - -static inline uint32_t _ARMV7M_Get_PSP(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], psp\n" : [val] "=&r" (val)); - return val; -} - -static inline void _ARMV7M_Set_PSP(uint32_t val) -{ - __asm__ volatile ("msr psp, %[val]\n" : : [val] "r" (val)); -} - -static inline uint32_t _ARMV7M_Get_XPSR(void) -{ - uint32_t val; - __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val)); - return val; -} - -static inline bool _ARMV7M_NVIC_Is_enabled( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - return (_ARMV7M_NVIC->iser [index] & bit) != 0; -} - -static inline void _ARMV7M_NVIC_Set_enable( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - _ARMV7M_NVIC->iser [index] = bit; -} - -static inline void _ARMV7M_NVIC_Clear_enable( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - _ARMV7M_NVIC->icer [index] = bit; -} - -static inline bool _ARMV7M_NVIC_Is_pending( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - return (_ARMV7M_NVIC->ispr [index] & bit) != 0; -} - -static inline void _ARMV7M_NVIC_Set_pending( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - _ARMV7M_NVIC->ispr [index] = bit; -} - -static inline void _ARMV7M_NVIC_Clear_pending( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - _ARMV7M_NVIC->icpr [index] = bit; -} - -static inline bool _ARMV7M_NVIC_Is_active( int irq ) -{ - int index = irq >> 5; - uint32_t bit = 1U << (irq & 0x1f); - - return (_ARMV7M_NVIC->iabr [index] & bit) != 0; -} - -static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority ) -{ - _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority; -} - -static inline int _ARMV7M_NVIC_Get_priority( int irq ) -{ - return _ARMV7M_NVIC->ipr [irq]; -} - -static inline bool _ARMV7M_DWT_Enable_CYCCNT( void ) -{ - uint32_t demcr; - uint32_t dwt_ctrl; - - demcr = _ARMV7M_DEBUG->demcr; - _ARMV7M_DEBUG->demcr = demcr | ARMV7M_DEBUG_DEMCR_TRCENA; - _ARM_Data_synchronization_barrier(); - - dwt_ctrl = _ARMV7M_DWT->ctrl; - if ((dwt_ctrl & ARMV7M_DWT_CTRL_NOCYCCNT) == 0) { - _ARMV7M_DWT->lar = ARMV7M_DWT_LAR_UNLOCK_MAGIC; - _ARM_Data_synchronization_barrier(); - _ARMV7M_DWT->ctrl = dwt_ctrl | ARMV7M_DWT_CTRL_CYCCNTENA; - return true; - } else { - _ARMV7M_DEBUG->demcr = demcr; - return false; - } -} - -int _ARMV7M_Get_exception_priority( int vector ); - -void _ARMV7M_Set_exception_priority( int vector, int priority ); - -ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index ); - -void _ARMV7M_Set_exception_handler( - int index, - ARMV7M_Exception_handler handler -); - -/** - * @brief ARMV7M set exception priority and handler. - */ -void _ARMV7M_Set_exception_priority_and_handler( - int index, - int priority, - ARMV7M_Exception_handler handler -); - -void _ARMV7M_Exception_default( void ); - -void _ARMV7M_Interrupt_service_enter( void ); - -void _ARMV7M_Interrupt_service_leave( void ); - -void _ARMV7M_Pendable_service_call( void ); - -void _ARMV7M_Supervisor_call( void ); - -#endif /* ASM */ - -#endif /* ARM_MULTILIB_ARCH_V7M */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* RTEMS_SCORE_ARMV7M_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h deleted file mode 100644 index 05e236c75a..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ /dev/null @@ -1,702 +0,0 @@ -/** - * @file - * - * @brief ARM Architecture Support API - */ - -/* - * This include file contains information pertaining to the ARM - * processor. - * - * Copyright (c) 2009, 2017 embedded brains GmbH - * - * Copyright (c) 2007 Ray Xu - * - * Copyright (c) 2006 OAR Corporation - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include -#include - -#if defined(ARM_MULTILIB_ARCH_V4) - -/** - * @defgroup ScoreCPUARM ARM Specific Support - * - * @ingroup ScoreCPU - * - * @brief ARM specific support. - */ -/**@{**/ - -#if defined(__thumb__) && !defined(__thumb2__) - #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg - #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" - #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" - #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) - #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT -#else - #define ARM_SWITCH_REGISTERS - #define ARM_SWITCH_TO_ARM - #define ARM_SWITCH_BACK - #define ARM_SWITCH_OUTPUT - #define ARM_SWITCH_ADDITIONAL_OUTPUT -#endif - -/** - * @name Program Status Register - */ -/**@{**/ - -#define ARM_PSR_N (1 << 31) -#define ARM_PSR_Z (1 << 30) -#define ARM_PSR_C (1 << 29) -#define ARM_PSR_V (1 << 28) -#define ARM_PSR_Q (1 << 27) -#define ARM_PSR_J (1 << 24) -#define ARM_PSR_GE_SHIFT 16 -#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) -#define ARM_PSR_E (1 << 9) -#define ARM_PSR_A (1 << 8) -#define ARM_PSR_I (1 << 7) -#define ARM_PSR_F (1 << 6) -#define ARM_PSR_T (1 << 5) -#define ARM_PSR_M_SHIFT 0 -#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) -#define ARM_PSR_M_USR 0x10 -#define ARM_PSR_M_FIQ 0x11 -#define ARM_PSR_M_IRQ 0x12 -#define ARM_PSR_M_SVC 0x13 -#define ARM_PSR_M_ABT 0x17 -#define ARM_PSR_M_HYP 0x1a -#define ARM_PSR_M_UND 0x1b -#define ARM_PSR_M_SYS 0x1f - -/** @} */ - -/** @} */ - -#endif /* defined(ARM_MULTILIB_ARCH_V4) */ - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * The ARM uses the PIC interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE - -#if defined(ARM_MULTILIB_HAS_WFI) - #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#else - #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#endif - -#define CPU_STACK_GROWS_UP FALSE - -#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) - #define CPU_CACHE_LINE_BYTES 64 -#else - #define CPU_CACHE_LINE_BYTES 32 -#endif - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -#define CPU_MODES_INTERRUPT_MASK 0x1 - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -#define CPU_STACK_MINIMUM_SIZE (1024 * 4) - -/* AAPCS, section 4.1, Fundamental Data Types */ -#define CPU_SIZEOF_POINTER 4 - -/* AAPCS, section 4.1, Fundamental Data Types */ -#define CPU_ALIGNMENT 8 - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* AAPCS, section 4.3.1, Aggregates */ -#define CPU_PARTITION_ALIGNMENT 4 - -/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ -#define CPU_STACK_ALIGNMENT 8 - -/* - * Bitfield handler macros. - * - * If we had a particularly fast function for finding the first - * bit set in a word, it would go here. Since we don't (*), we'll - * just use the universal macros. - * - * (*) On ARM V5 and later, there's a CLZ function which could be - * used to implement much quicker than the default macro. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_MAXIMUM_PROCESSORS 32 - -/** @} */ - -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 -#endif - -#ifdef ARM_MULTILIB_VFP - #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 -#endif - -#ifdef ARM_MULTILIB_ARCH_V4 - #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40 -#endif - -#ifdef RTEMS_SMP - #if defined(ARM_MULTILIB_VFP) - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 - #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER) - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 - #else - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44 - #endif -#endif - -#define ARM_EXCEPTION_FRAME_SIZE 80 - -#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 - -#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 - -#define ARM_VFP_CONTEXT_SIZE 264 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -typedef struct { -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_fp; - uint32_t register_sp; - uint32_t register_lr; - uint32_t isr_dispatch_disable; -#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_r11; - void *register_lr; - void *register_sp; - uint32_t isr_nest_level; -#else - void *register_sp; -#endif -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - uint32_t thread_id; -#endif -#ifdef ARM_MULTILIB_VFP - uint64_t register_d8; - uint64_t register_d9; - uint64_t register_d10; - uint64_t register_d11; - uint64_t register_d12; - uint64_t register_d13; - uint64_t register_d14; - uint64_t register_d15; -#endif -#ifdef RTEMS_SMP - volatile bool is_executing; -#endif -} Context_Control; - -typedef struct { - /* Not supported */ -} Context_Control_fp; - -static inline void _ARM_Data_memory_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "dmb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline void _ARM_Data_synchronization_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "dsb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline void _ARM_Instruction_synchronization_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "isb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline uint32_t arm_interrupt_disable( void ) -{ - uint32_t level; - -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - - /* - * Disable only normal interrupts (IRQ). - * - * In order to support fast interrupts (FIQ) such that they can do something - * useful, we have to disable the operating system support for FIQs. Having - * operating system support for them would require that FIQs are disabled - * during critical sections of the operating system and application. At this - * level IRQs and FIQs would be equal. It is true that FIQs could interrupt - * the non critical sections of IRQs, so here they would have a small - * advantage. Without operating system support, the FIQs can execute at any - * time (of course not during the service of another FIQ). If someone needs - * operating system support for a FIQ, she can trigger a software interrupt and - * service the request in a two-step process. - */ - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[level], cpsr\n" - "orr %[arm_switch_reg], %[level], #0x80\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - uint32_t basepri = 0x80; - - __asm__ volatile ( - "mrs %[level], basepri\n" - "msr basepri_max, %[basepri]\n" - : [level] "=&r" (level) - : [basepri] "r" (basepri) - ); -#endif - - return level; -} - -static inline void arm_interrupt_enable( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - ARM_SWITCH_REGISTERS; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "msr cpsr, %[level]\n" - ARM_SWITCH_BACK - : ARM_SWITCH_OUTPUT - : [level] "r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - __asm__ volatile ( - "msr basepri, %[level]\n" - : - : [level] "r" (level) - ); -#endif -} - -static inline void arm_interrupt_flash( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[arm_switch_reg], cpsr\n" - "msr cpsr, %[level]\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg) - : [level] "r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - uint32_t basepri; - - __asm__ volatile ( - "mrs %[basepri], basepri\n" - "msr basepri, %[level]\n" - "msr basepri, %[basepri]\n" - : [basepri] "=&r" (basepri) - : [level] "r" (level) - ); -#endif -} - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - _isr_cookie = arm_interrupt_disable(); \ - } while (0) - -#define _CPU_ISR_Enable( _isr_cookie ) \ - arm_interrupt_enable( _isr_cookie ) - -#define _CPU_ISR_Flash( _isr_cookie ) \ - arm_interrupt_flash( _isr_cookie ) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - return ( level & 0x80 ) == 0; -#elif defined(ARM_MULTILIB_ARCH_V7M) - return level == 0; -#endif -} - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -#define _CPU_Fatal_halt( _source, _err ) \ - do { \ - uint32_t _level; \ - uint32_t _error = _err; \ - _CPU_ISR_Disable( _level ); \ - (void) _level; \ - __asm__ volatile ("mov r0, %0\n" \ - : "=r" (_error) \ - : "0" (_error) \ - : "r0" ); \ - while (1); \ - } while (0); - -/** - * @brief CPU initialization. - */ -void _CPU_Initialize( void ); - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief CPU switch context. - */ -void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); - -void _CPU_Context_restore( Context_Control *new_context ) - RTEMS_NO_RETURN; - -#if defined(ARM_MULTILIB_ARCH_V7M) - void _ARMV7M_Start_multitasking( Context_Control *heir ) - RTEMS_NO_RETURN; - #define _CPU_Start_multitasking _ARMV7M_Start_multitasking -#endif - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t mpidr; - - /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ - __asm__ volatile ( - "mrc p15, 0, %[mpidr], c0, c0, 5\n" - : [mpidr] "=&r" (mpidr) - ); - - return mpidr & 0xffU; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _ARM_Send_event( void ) - { - __asm__ volatile ( "sev" : : : "memory" ); - } - - static inline void _ARM_Wait_for_event( void ) - { - __asm__ volatile ( "wfe" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - _ARM_Data_synchronization_barrier(); - _ARM_Send_event(); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - _ARM_Wait_for_event(); - _ARM_Data_memory_barrier(); - } -#endif - - -static inline uint32_t CPU_swap_u32( uint32_t value ) -{ -#if defined(__thumb2__) - __asm__ volatile ( - "rev %0, %0" - : "=r" (value) - : "0" (value) - ); - return value; -#elif defined(__thumb__) - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -#else - uint32_t tmp = value; /* make compiler warnings go away */ - __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" - "BIC %1, %1, #0xff0000\n" - "MOV %0, %0, ROR #8\n" - "EOR %0, %0, %1, LSR #8\n" - : "=r" (value), "=r" (tmp) - : "0" (value), "1" (tmp)); - return value; -#endif -} - -static inline uint16_t CPU_swap_u16( uint16_t value ) -{ -#if defined(__thumb2__) - __asm__ volatile ( - "rev16 %0, %0" - : "=r" (value) - : "0" (value) - ); - return value; -#else - return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); -#endif -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE - void *_CPU_Thread_Idle_body( uintptr_t ignored ); -#endif - -/** @} */ - -/** - * @addtogroup ScoreCPUARM - */ -/**@{**/ - -#if defined(ARM_MULTILIB_ARCH_V4) - -typedef enum { - ARM_EXCEPTION_RESET = 0, - ARM_EXCEPTION_UNDEF = 1, - ARM_EXCEPTION_SWI = 2, - ARM_EXCEPTION_PREF_ABORT = 3, - ARM_EXCEPTION_DATA_ABORT = 4, - ARM_EXCEPTION_RESERVED = 5, - ARM_EXCEPTION_IRQ = 6, - ARM_EXCEPTION_FIQ = 7, - MAX_EXCEPTIONS = 8, - ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff -} Arm_symbolic_exception_name; - -#endif /* defined(ARM_MULTILIB_ARCH_V4) */ - -typedef struct { - uint32_t register_fpexc; - uint32_t register_fpscr; - uint64_t register_d0; - uint64_t register_d1; - uint64_t register_d2; - uint64_t register_d3; - uint64_t register_d4; - uint64_t register_d5; - uint64_t register_d6; - uint64_t register_d7; - uint64_t register_d8; - uint64_t register_d9; - uint64_t register_d10; - uint64_t register_d11; - uint64_t register_d12; - uint64_t register_d13; - uint64_t register_d14; - uint64_t register_d15; - uint64_t register_d16; - uint64_t register_d17; - uint64_t register_d18; - uint64_t register_d19; - uint64_t register_d20; - uint64_t register_d21; - uint64_t register_d22; - uint64_t register_d23; - uint64_t register_d24; - uint64_t register_d25; - uint64_t register_d26; - uint64_t register_d27; - uint64_t register_d28; - uint64_t register_d29; - uint64_t register_d30; - uint64_t register_d31; -} ARM_VFP_context; - -typedef struct { - uint32_t register_r0; - uint32_t register_r1; - uint32_t register_r2; - uint32_t register_r3; - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_r11; - uint32_t register_r12; - uint32_t register_sp; - void *register_lr; - void *register_pc; -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t register_cpsr; - Arm_symbolic_exception_name vector; -#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) - uint32_t register_xpsr; - uint32_t vector; -#endif - const ARM_VFP_context *vfp_context; - uint32_t reserved_for_stack_alignment; -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -void _ARM_Exception_default( CPU_Exception_frame *frame ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h deleted file mode 100644 index c430911373..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * - * @ingroup ScoreCPU - * - * @brief ARM Assembler Support API - */ - -/* - * COPYRIGHT (c) 2002 by Advent Networks, Inc. - * Jay Monkman - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file is the include file for cpu_asm.S - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - -/* Registers saved in context switch: */ -.set REG_CPSR, 0 -.set REG_R4, 4 -.set REG_R5, 8 -.set REG_R6, 12 -.set REG_R7, 16 -.set REG_R8, 20 -.set REG_R9, 24 -.set REG_R10, 28 -.set REG_R11, 32 -.set REG_SP, 36 -.set REG_LR, 40 -.set REG_PC, 44 -.set SIZE_REGS, REG_PC + 4 - -#endif diff --git a/cpukit/score/cpu/arm/rtems/score/cpuatomic.h b/cpukit/score/cpu/arm/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h deleted file mode 100644 index 0885c2ef39..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013, 2016 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifdef ARM_MULTILIB_ARCH_V4 - -#if defined(ARM_MULTILIB_VFP_D32) -#define CPU_INTERRUPT_FRAME_SIZE 240 -#elif defined(ARM_MULTILIB_VFP) -#define CPU_INTERRUPT_FRAME_SIZE 112 -#else -#define CPU_INTERRUPT_FRAME_SIZE 40 -#endif - -#endif /* ARM_MULTILIB_ARCH_V4 */ - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef ARM_MULTILIB_ARCH_V4 - -typedef struct { -#ifdef ARM_MULTILIB_VFP - uint32_t fpscr; -#ifdef ARM_MULTILIB_VFP_D32 - double d16; - double d17; - double d18; - double d19; - double d20; - double d21; - double d22; - double d23; - double d24; - double d25; - double d26; - double d27; - double d28; - double d29; - double d30; - double d31; -#endif /* ARM_MULTILIB_VFP_D32 */ - double d0; - double d1; - double d2; - double d3; - double d4; - double d5; - double d6; - double d7; -#endif /* ARM_MULTILIB_VFP */ - uint32_t r9; - uint32_t lr; - uint32_t r0; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t return_pc; - uint32_t return_cpsr; - uint32_t r7; - uint32_t r12; -} CPU_Interrupt_frame; - -#ifdef RTEMS_SMP - -static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void ) -{ - struct Per_CPU_Control *cpu_self; - - /* Use PL1 only Thread ID Register (TPIDRPRW) */ - __asm__ volatile ( - "mrc p15, 0, %0, c13, c0, 4" - : "=r" ( cpu_self ) - ); - - return cpu_self; -} - -#define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control() - -#endif /* RTEMS_SMP */ - -#endif /* ARM_MULTILIB_ARCH_V4 */ - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/types.h b/cpukit/score/cpu/arm/rtems/score/types.h deleted file mode 100644 index 37a56df029..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/types.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file - * - * @brief ARM Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/bfin/Makefile.am b/cpukit/score/cpu/bfin/Makefile.am index 8fa75df995..3d7483a220 100644 --- a/cpukit/score/cpu/bfin/Makefile.am +++ b/cpukit/score/cpu/bfin/Makefile.am @@ -1,26 +1,10 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_bfindir = $(includedir)/rtems/bfin -include_rtems_bfin_HEADERS = rtems/bfin/bfin.h -include_rtems_bfin_HEADERS += rtems/bfin/bf533.h -include_rtems_bfin_HEADERS += rtems/bfin/bf52x.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/bfin.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c cpu_asm.S libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += bfin-exception-frame-print.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/bfin/headers.am b/cpukit/score/cpu/bfin/headers.am new file mode 100644 index 0000000000..b9eba7b181 --- /dev/null +++ b/cpukit/score/cpu/bfin/headers.am @@ -0,0 +1,24 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_bfindir = $(includedir)/rtems/bfin +include_rtems_bfin_HEADERS = +include_rtems_bfin_HEADERS += include/rtems/bfin/bf52x.h +include_rtems_bfin_HEADERS += include/rtems/bfin/bf533.h +include_rtems_bfin_HEADERS += include/rtems/bfin/bfin.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/bfin.h +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/bfin/include/machine/elf_machdep.h b/cpukit/score/cpu/bfin/include/machine/elf_machdep.h new file mode 100644 index 0000000000..cf0dc19221 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/machine/elf_machdep.h @@ -0,0 +1,28 @@ +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB + +#define ELF32_MACHDEP_ID_CASES \ + case EM_BLACKFIN: \ + break; + +#define ELF32_MACHDEP_ID EM_BLACKFIN + +#define ARCH_ELFSIZE 32 + +#define R_BFIN_UNUSED0 0 + +#define R_BFIN_RIMM16 5 +#define R_BFIN_LUIMM16 6 +#define R_BFIN_HUIMM16 7 +#define R_BFIN_PCREL12_JUMP_S 8 +#define R_BFIN_PCREL24_JUMP_X 9 +#define R_BFIN_PCREL24 10 +#define R_BFIN_PCREL24_JU 13 +#define R_BFIN_PCREL24_CALL_X 14 + +#define R_BFIN_BYTE_DATA 16 +#define R_BFIN_BYTE2_DATA 17 +#define R_BFIN_BYTE4_DATA 18 + + + +#define R_TYPE(name) __CONCAT(R_BFIN_,name) diff --git a/cpukit/score/cpu/bfin/include/rtems/asm.h b/cpukit/score/cpu/bfin/include/rtems/asm.h new file mode 100644 index 0000000000..5d133ddbdd --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/asm.h @@ -0,0 +1,127 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * @note The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-2006. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all register names. + */ +#define __REGISTER_PREFIX__ +#endif + +#include + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** This macro is used to denote the beginning of a data declaration section. */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** + * This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h b/cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h new file mode 100644 index 0000000000..86142a6c62 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h @@ -0,0 +1,430 @@ +/** + * @file + * + * @brief Basic MMR for the Blackfin 52x CPU + * + * This file defines basic MMR for the Blackfin 52x CPU. + * The MMR have been taken from the ADSP-BF52x Blackfin Processor + * Hardware Reference from Analog Devices. Mentioned Chapters + * refer to this Documentation. + * + * Based on bf533.h + */ + +/* + * COPYRIGHT (c) 2006. + * Atos Automacao Industrial LTDA. + * modified by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Author: Rohan Kangralkar, ECE Department Northeastern University + * Date: 02/15/2011 + */ + +#ifndef _RTEMS_BFIN_52x_H +#define _RTEMS_BFIN_52x_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Clock and System Control Chapter 8 */ +#define PLL_CTL 0xFFC00000L +#define PLL_DIV 0xFFC00004L +#define VR_CTL 0xFFC00008L +#define PLL_STAT 0xFFC0000CL +#define PLL_LOCKCNT 0xFFC00010L +#define SWRST 0xFFC00100L +#define SYSCR 0xFFC00104L + +/* SPI Controller Chapter 10 */ +#define SPI_CTL 0xFFC00500L +#define SPI_FLG 0xFFC00504L +#define SPI_STAT 0xFFC00508L +#define SPI_TDBR 0xFFC0050CL +#define SPI_RDBR 0xFFC00510L +#define SPI_BAUD 0xFFC00514L +#define SPI_SHADOW 0xFFC00518L + +/* SPORT0 Controller */ +#define SPORT0_TCR1 0xFFC00800L +#define SPORT0_TCR2 0xFFC00804L +#define SPORT0_TCLKDIV 0xFFC00808L +#define SPORT0_TFSDIV 0xFFC0080CL +#define SPORT0_TX 0xFFC00810L +#define SPORT0_RX 0xFFC00818L +#define SPORT0_RCR1 0xFFC00820L +#define SPORT0_RCR2 0xFFC00824L +#define SPORT0_RCLKDIV 0xFFC00828L +#define SPORT0_RFSDIV 0xFFC0082CL +#define SPORT0_STAT 0xFFC00830L +#define SPORT0_CHNL 0xFFC00834L +#define SPORT0_MCMC1 0xFFC00838L +#define SPORT0_MCMC2 0xFFC0083CL +#define SPORT0_MTCS0 0xFFC00840L +#define SPORT0_MTCS1 0xFFC00844L +#define SPORT0_MTCS2 0xFFC00848L +#define SPORT0_MTCS3 0xFFC0084CL +#define SPORT0_MRCS0 0xFFC00850L +#define SPORT0_MRCS1 0xFFC00854L +#define SPORT0_MRCS2 0xFFC00858L +#define SPORT0_MRCS3 0xFFC0085CL + +/* Parallel Peripheral Interface (PPI) Chapter 11 */ + +#define PPI_CONTROL 0xFFC01000L +#define PPI_STATUS 0xFFC01004L +#define PPI_COUNT 0xFFC01008L +#define PPI_DELAY 0xFFC0100CL +#define PPI_FRAME 0xFFC01010L + +/********* PPI MASKS ***********/ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 +#define PORT_DIR 0x00000002 +#define XFR_TYPE 0x0000000C +#define PORT_CFG 0x00000030 +#define FLD_SEL 0x00000040 +#define PACK_EN 0x00000080 +#define DMA32 0x00000100 +#define SKIP_EN 0x00000200 +#define SKIP_EO 0x00000400 +#define DLENGTH 0x00003800 +#define DLEN_8 0x0 +#define DLEN(x) (((x-9) & 0x07) << 11) +#define POL 0x0000C000 + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 +#define FT_ERR 0x00000800 +#define OVR 0x00001000 +#define UNDR 0x00002000 +#define ERR_DET 0x00004000 +#define ERR_NCOR 0x00008000 + +/* SPORT1 Controller Chapter 12 */ +#define SPORT1_TCR1 0xFFC00900L +#define SPORT1_TCR2 0xFFC00904L +#define SPORT1_TCLKDIV 0xFFC00908L +#define SPORT1_TFSDIV 0xFFC0090CL +#define SPORT1_TX 0xFFC00910L +#define SPORT1_RX 0xFFC00918L +#define SPORT1_RCR1 0xFFC00920L +#define SPORT1_RCR2 0xFFC00924L +#define SPORT1_RCLKDIV 0xFFC00928L +#define SPORT1_RFSDIV 0xFFC0092CL +#define SPORT1_STAT 0xFFC00930L +#define SPORT1_CHNL 0xFFC00934L +#define SPORT1_MCMC1 0xFFC00938L +#define SPORT1_MCMC2 0xFFC0093CL +#define SPORT1_MTCS0 0xFFC00940L +#define SPORT1_MTCS1 0xFFC00944L +#define SPORT1_MTCS2 0xFFC00948L +#define SPORT1_MTCS3 0xFFC0094CL +#define SPORT1_MRCS0 0xFFC00950L +#define SPORT1_MRCS1 0xFFC00954L +#define SPORT1_MRCS2 0xFFC00958L +#define SPORT1_MRCS3 0xFFC0095CL + +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 +#define ITCLK 0x0002 +#define TDTYPE 0x000C +#define TLSBIT 0x0010 +#define ITFS 0x0200 +#define TFSR 0x0400 +#define DITFS 0x0800 +#define LTFS 0x1000 +#define LATFS 0x2000 +#define TCKFE 0x4000 + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F +#define TXSE 0x0100 +#define TSFSE 0x0200 +#define TRFST 0x0400 + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 +#define IRCLK 0x0002 +#define RDTYPE 0x000C +#define RULAW 0x0008 +#define RALAW 0x000C +#define RLSBIT 0x0010 +#define IRFS 0x0200 +#define RFSR 0x0400 +#define LRFS 0x1000 +#define LARFS 0x2000 +#define RCKFE 0x4000 + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F +#define RXSE 0x0100 +#define RSFSE 0x0200 +#define RRFST 0x0400 + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 +#define RUVF 0x0002 +#define ROVF 0x0004 +#define TXF 0x0008 +#define TUVF 0x0010 +#define TOVF 0x0020 +#define TXHRE 0x0040 + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 +#define WOFF 0x000003FF + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 +#define MCDTXPE 0x00000004 +#define MCDRXPE 0x00000008 +#define MCMEN 0x00000010 +#define FSDR 0x00000080 +#define MFD 0x0000F000 + +/* UART Controller Chapter 13 */ +#define UART_THR 0xFFC00400L +#define UART_RBR 0xFFC00400L +#define UART_DLL 0xFFC00400L +#define UART_IER 0xFFC00404L +#define UART_DLH 0xFFC00404L +#define UART_IIR 0xFFC00408L +#define UART_LCR 0xFFC0040CL +#define UART_MCR 0xFFC00410L +#define UART_LSR 0xFFC00414L +#define UART_SCR 0xFFC0041CL +#define UART_GCTL 0xFFC00424L + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* General Purpose IO Chapter 14*/ +#define FIO_FLAG_D 0xFFC00700L +#define FIO_FLAG_C 0xFFC00704L +#define FIO_FLAG_S 0xFFC00708L +#define FIO_FLAG_T 0xFFC0070CL +#define FIO_MASKA_D 0xFFC00710L +#define FIO_MASKA_C 0xFFC00714L +#define FIO_MASKA_S 0xFFC00718L +#define FIO_MASKA_T 0xFFC0071CL +#define FIO_MASKB_D 0xFFC00720L +#define FIO_MASKB_C 0xFFC00724L +#define FIO_MASKB_S 0xFFC00728L +#define FIO_MASKB_T 0xFFC0072CL +#define FIO_DIR 0xFFC00730L +#define FIO_POLAR 0xFFC00734L +#define FIO_EDGE 0xFFC00738L +#define FIO_BOTH 0xFFC0073CL +#define FIO_INEN 0xFFC00740L + + +/* General Purpose IO Chapter 9*/ +#define PORTH_FER 0xFFC03208 +#define PORTH_MUX 0xFFC03218 +#define PORTHIO_DIR 0xFFC01730 +#define PORTHIO_INEN 0xFFC01740 +#define PORTHIO 0xFFC01700 +#define PORTHIO_SET 0xFFC01708 +#define PORTHIO_CLEAR 0xFFC01704 +#define PORTHIO_TOGGLE 0xFFC0170C + + +#define FIO_INEN 0xFFC00740L +#define FIO_POLAR 0xFFC00734L +#define FIO_EDGE 0xFFC00738L +#define FIO_BOTH 0xFFC0073CL + + + +#define FIO_FLAG_C 0xFFC00704L +#define FIO_FLAG_S 0xFFC00708L +#define FIO_FLAG_T 0xFFC0070CL +#define FIO_MASKA_D 0xFFC00710L +#define FIO_MASKA_C 0xFFC00714L +#define FIO_MASKA_S 0xFFC00718L +#define FIO_MASKA_T 0xFFC0071CL +#define FIO_MASKB_D 0xFFC00720L +#define FIO_MASKB_C 0xFFC00724L +#define FIO_MASKB_S 0xFFC00728L +#define FIO_MASKB_T 0xFFC0072CL + + +/* General Purpose IO Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + + +/* TIMER 0, 1, 2 Chapter 15 */ +#define TIMER0_CONFIG 0xFFC00600L +#define TIMER0_COUNTER 0xFFC00604L +#define TIMER0_PERIOD 0xFFC00608L +#define TIMER0_WIDTH 0xFFC0060CL + +#define TIMER1_CONFIG 0xFFC00610L +#define TIMER1_COUNTER 0xFFC00614L +#define TIMER1_PERIOD 0xFFC00618L +#define TIMER1_WIDTH 0xFFC0061CL + +#define TIMER2_CONFIG 0xFFC00620L +#define TIMER2_COUNTER 0xFFC00624L +#define TIMER2_PERIOD 0xFFC00628L +#define TIMER2_WIDTH 0xFFC0062CL + +#define TIMER_ENABLE 0xFFC00640L +#define TIMER_DISABLE 0xFFC00644L +#define TIMER_STATUS 0xFFC00648L + +/* Real Time Clock Chapter 16 */ +#define RTC_STAT 0xFFC00300L +#define RTC_ICTL 0xFFC00304L +#define RTC_ISTAT 0xFFC00308L +#define RTC_SWCNT 0xFFC0030CL +#define RTC_ALARM 0xFFC00310L +#define RTC_FAST 0xFFC00314L +#define RTC_PREN 0xFFC00314L + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 +#define PREN 0x00000001 + +/* Asynchronous Memory Controller EBUI, Chapter 17*/ +#define EBIU_AMGCTL 0xFFC00A00L +#define EBIU_AMBCTL0 0xFFC00A04L +#define EBIU_AMBCTL1 0xFFC00A08L + +/* SDRAM Controller External Bus Interface Unit */ + +#define EBIU_SDGCTL 0xFFC00A10L +#define EBIU_SDBCTL 0xFFC00A14L +#define EBIU_SDRRC 0xFFC00A18L +#define EBIU_SDSTAT 0xFFC00A1CL + + + + +/* DCPLB_DATA and ICPLB_DATA Registers */ +/*** Bit Positions */ +#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ +/*** Masks */ +#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ +#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ +#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ +#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ +#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ +#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ +/*** ICPLB_DATA only */ +#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ +/*** DCPLB_DATA only */ +#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ +#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ +#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ +#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ + /* 1= allocate cache lines on write-through writes. */ +#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h new file mode 100644 index 0000000000..682aad4bbb --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h @@ -0,0 +1,396 @@ +/** + * @file + * + * @brief Basic MMR for the Blackfin 531/532/533 CPU + * + * This file defines basic MMR for the Blackfin 531/532/533 CPU. + * The MMR have been taken from the ADSP-BF533 Blackfin Processor + * Hardware Reference from Analog Devices. Mentioned Chapters + * refer to this Documentation. + * + * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF) + * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined + * in bfin.h which is included. + */ +/* + * COPYRIGHT (c) 2006. + * Atos Automacao Industrial LTDA. + * modified by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_BFIN_533_H +#define _RTEMS_BFIN_533_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Clock and System Control Chapter 8 */ +#define PLL_CTL 0xFFC00000L +#define PLL_DIV 0xFFC00004L +#define VR_CTL 0xFFC00008L +#define PLL_STAT 0xFFC0000CL +#define PLL_LOCKCNT 0xFFC00010L +#define SWRST 0xFFC00100L +#define SYSCR 0xFFC00104L + +/* SPI Controller Chapter 10 */ +#define SPI_CTL 0xFFC00500L +#define SPI_FLG 0xFFC00504L +#define SPI_STAT 0xFFC00508L +#define SPI_TDBR 0xFFC0050CL +#define SPI_RDBR 0xFFC00510L +#define SPI_BAUD 0xFFC00514L +#define SPI_SHADOW 0xFFC00518L + +/* SPORT0 Controller */ +#define SPORT0_TCR1 0xFFC00800L +#define SPORT0_TCR2 0xFFC00804L +#define SPORT0_TCLKDIV 0xFFC00808L +#define SPORT0_TFSDIV 0xFFC0080CL +#define SPORT0_TX 0xFFC00810L +#define SPORT0_RX 0xFFC00818L +#define SPORT0_RCR1 0xFFC00820L +#define SPORT0_RCR2 0xFFC00824L +#define SPORT0_RCLKDIV 0xFFC00828L +#define SPORT0_RFSDIV 0xFFC0082CL +#define SPORT0_STAT 0xFFC00830L +#define SPORT0_CHNL 0xFFC00834L +#define SPORT0_MCMC1 0xFFC00838L +#define SPORT0_MCMC2 0xFFC0083CL +#define SPORT0_MTCS0 0xFFC00840L +#define SPORT0_MTCS1 0xFFC00844L +#define SPORT0_MTCS2 0xFFC00848L +#define SPORT0_MTCS3 0xFFC0084CL +#define SPORT0_MRCS0 0xFFC00850L +#define SPORT0_MRCS1 0xFFC00854L +#define SPORT0_MRCS2 0xFFC00858L +#define SPORT0_MRCS3 0xFFC0085CL + +/* Parallel Peripheral Interface (PPI) Chapter 11 */ + +#define PPI_CONTROL 0xFFC01000L +#define PPI_STATUS 0xFFC01004L +#define PPI_COUNT 0xFFC01008L +#define PPI_DELAY 0xFFC0100CL +#define PPI_FRAME 0xFFC01010L + +/********* PPI MASKS ***********/ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 +#define PORT_DIR 0x00000002 +#define XFR_TYPE 0x0000000C +#define PORT_CFG 0x00000030 +#define FLD_SEL 0x00000040 +#define PACK_EN 0x00000080 +#define DMA32 0x00000100 +#define SKIP_EN 0x00000200 +#define SKIP_EO 0x00000400 +#define DLENGTH 0x00003800 +#define DLEN_8 0x0 +#define DLEN(x) (((x-9) & 0x07) << 11) +#define POL 0x0000C000 + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 +#define FT_ERR 0x00000800 +#define OVR 0x00001000 +#define UNDR 0x00002000 +#define ERR_DET 0x00004000 +#define ERR_NCOR 0x00008000 + +/* SPORT1 Controller Chapter 12 */ +#define SPORT1_TCR1 0xFFC00900L +#define SPORT1_TCR2 0xFFC00904L +#define SPORT1_TCLKDIV 0xFFC00908L +#define SPORT1_TFSDIV 0xFFC0090CL +#define SPORT1_TX 0xFFC00910L +#define SPORT1_RX 0xFFC00918L +#define SPORT1_RCR1 0xFFC00920L +#define SPORT1_RCR2 0xFFC00924L +#define SPORT1_RCLKDIV 0xFFC00928L +#define SPORT1_RFSDIV 0xFFC0092CL +#define SPORT1_STAT 0xFFC00930L +#define SPORT1_CHNL 0xFFC00934L +#define SPORT1_MCMC1 0xFFC00938L +#define SPORT1_MCMC2 0xFFC0093CL +#define SPORT1_MTCS0 0xFFC00940L +#define SPORT1_MTCS1 0xFFC00944L +#define SPORT1_MTCS2 0xFFC00948L +#define SPORT1_MTCS3 0xFFC0094CL +#define SPORT1_MRCS0 0xFFC00950L +#define SPORT1_MRCS1 0xFFC00954L +#define SPORT1_MRCS2 0xFFC00958L +#define SPORT1_MRCS3 0xFFC0095CL + +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 +#define ITCLK 0x0002 +#define TDTYPE 0x000C +#define TLSBIT 0x0010 +#define ITFS 0x0200 +#define TFSR 0x0400 +#define DITFS 0x0800 +#define LTFS 0x1000 +#define LATFS 0x2000 +#define TCKFE 0x4000 + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F +#define TXSE 0x0100 +#define TSFSE 0x0200 +#define TRFST 0x0400 + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 +#define IRCLK 0x0002 +#define RDTYPE 0x000C +#define RULAW 0x0008 +#define RALAW 0x000C +#define RLSBIT 0x0010 +#define IRFS 0x0200 +#define RFSR 0x0400 +#define LRFS 0x1000 +#define LARFS 0x2000 +#define RCKFE 0x4000 + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F +#define RXSE 0x0100 +#define RSFSE 0x0200 +#define RRFST 0x0400 + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 +#define RUVF 0x0002 +#define ROVF 0x0004 +#define TXF 0x0008 +#define TUVF 0x0010 +#define TOVF 0x0020 +#define TXHRE 0x0040 + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 +#define WOFF 0x000003FF + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 +#define MCDTXPE 0x00000004 +#define MCDRXPE 0x00000008 +#define MCMEN 0x00000010 +#define FSDR 0x00000080 +#define MFD 0x0000F000 + +/* UART Controller Chapter 13 */ +#define UART_THR 0xFFC00400L +#define UART_RBR 0xFFC00400L +#define UART_DLL 0xFFC00400L +#define UART_IER 0xFFC00404L +#define UART_DLH 0xFFC00404L +#define UART_IIR 0xFFC00408L +#define UART_LCR 0xFFC0040CL +#define UART_MCR 0xFFC00410L +#define UART_LSR 0xFFC00414L +#define UART_SCR 0xFFC0041CL +#define UART_GCTL 0xFFC00424L + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* General Purpose IO Chapter 14*/ +#define FIO_FLAG_D 0xFFC00700L +#define FIO_FLAG_C 0xFFC00704L +#define FIO_FLAG_S 0xFFC00708L +#define FIO_FLAG_T 0xFFC0070CL +#define FIO_MASKA_D 0xFFC00710L +#define FIO_MASKA_C 0xFFC00714L +#define FIO_MASKA_S 0xFFC00718L +#define FIO_MASKA_T 0xFFC0071CL +#define FIO_MASKB_D 0xFFC00720L +#define FIO_MASKB_C 0xFFC00724L +#define FIO_MASKB_S 0xFFC00728L +#define FIO_MASKB_T 0xFFC0072CL +#define FIO_DIR 0xFFC00730L +#define FIO_POLAR 0xFFC00734L +#define FIO_EDGE 0xFFC00738L +#define FIO_BOTH 0xFFC0073CL +#define FIO_INEN 0xFFC00740L + +/* General Purpose IO Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + + +/* TIMER 0, 1, 2 Chapter 15 */ +#define TIMER0_CONFIG 0xFFC00600L +#define TIMER0_COUNTER 0xFFC00604L +#define TIMER0_PERIOD 0xFFC00608L +#define TIMER0_WIDTH 0xFFC0060CL + +#define TIMER1_CONFIG 0xFFC00610L +#define TIMER1_COUNTER 0xFFC00614L +#define TIMER1_PERIOD 0xFFC00618L +#define TIMER1_WIDTH 0xFFC0061CL + +#define TIMER2_CONFIG 0xFFC00620L +#define TIMER2_COUNTER 0xFFC00624L +#define TIMER2_PERIOD 0xFFC00628L +#define TIMER2_WIDTH 0xFFC0062CL + +#define TIMER_ENABLE 0xFFC00640L +#define TIMER_DISABLE 0xFFC00644L +#define TIMER_STATUS 0xFFC00648L + +/* Real Time Clock Chapter 16 */ +#define RTC_STAT 0xFFC00300L +#define RTC_ICTL 0xFFC00304L +#define RTC_ISTAT 0xFFC00308L +#define RTC_SWCNT 0xFFC0030CL +#define RTC_ALARM 0xFFC00310L +#define RTC_FAST 0xFFC00314L +#define RTC_PREN 0xFFC00314L + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 +#define PREN 0x00000001 + +/* Asynchronous Memory Controller EBUI, Chapter 17*/ +#define EBIU_AMGCTL 0xFFC00A00L +#define EBIU_AMBCTL0 0xFFC00A04L +#define EBIU_AMBCTL1 0xFFC00A08L + +/* SDRAM Controller External Bus Interface Unit */ + +#define EBIU_SDGCTL 0xFFC00A10L +#define EBIU_SDBCTL 0xFFC00A14L +#define EBIU_SDRRC 0xFFC00A18L +#define EBIU_SDSTAT 0xFFC00A1CL + + + + +/* DCPLB_DATA and ICPLB_DATA Registers */ +/*** Bit Positions */ +#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ +/*** Masks */ +#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ +#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ +#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ +#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ +#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ +#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ +/*** ICPLB_DATA only */ +#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ +/*** DCPLB_DATA only */ +#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ +#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ +#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ +#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ + /* 1= allocate cache lines on write-through writes. */ +#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h new file mode 100644 index 0000000000..4ba0b2b295 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h @@ -0,0 +1,88 @@ +/** + * @file + * + * @brief Macros for MMR register common to all Blackfin Processors + * + * This file defines Macros for MMR register common to all Blackfin + * Processors. + */ + +/* + * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. + * modified by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_BFIN_BFIN_H +#define _RTEMS_BFIN_BFIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Scratchpad SRAM */ + +#define SCRATCH 0xFFB00000 +#define SCRATCH_SIZE 0x1000 +#define SCRATCH_TOP 0xFFB00ffc + + +/* System Interrupt Controller Chapter 4*/ +#define SIC_RVECT 0xFFC00108 +#define SIC_IMASK 0xFFC0010C +#define SIC_IAR0 0xFFC00110 +#define SIC_IAR1 0xFFC00114 +#define SIC_IAR2 0xFFC00118 +#define SIC_ISR 0xFFC00120 +#define SIC_IWR 0xFFC00124 + +/* Event Vector Table Chapter 4 */ + +#define EVT0 0xFFE02000 +#define EVT1 0xFFE02004 +#define EVT2 0xFFE02008 +#define EVT3 0xFFE0200C +#define EVT4 0xFFE02010 +#define EVT5 0xFFE02014 +#define EVT6 0xFFE02018 +#define EVT7 0xFFE0201C +#define EVT8 0xFFE02020 +#define EVT9 0xFFE02024 +#define EVT10 0xFFE02028 +#define EVT11 0xFFE0202C +#define EVT12 0xFFE02030 +#define EVT13 0xFFE02034 +#define EVT14 0xFFE02038 +#define EVT15 0xFFE0203C +#define IMASK 0xFFE02104 +#define IPEND 0xFFE02108 +#define ILAT 0xFFE0210C +#define IPRIO 0xFFE02110 + + +#define TCNTL 0xFFE03000 +#define TPERIOD 0xFFE03004 +#define TSCALE 0xFFE03008 +#define TCOUNT 0xFFE0300C + +/* Masks for Timer Control */ +#define TMPWR 0x00000001 +#define TMREN 0x00000002 +#define TAUTORLD 0x00000004 +#define TINT 0x00000008 + +/* Event Bit Positions */ +#define EVT_IVTMR_P 0x00000006 + +#define EVT_IVTMR (1 << EVT_IVTMR_P) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/bfin.h b/cpukit/score/cpu/bfin/include/rtems/score/bfin.h new file mode 100644 index 0000000000..caa3a51830 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/score/bfin.h @@ -0,0 +1,69 @@ +/** + * @file + * + * @brief Blackfin Set up Basic CPU Dependency Settings Based on + * Compiler Settings + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specified to the Blackfin port. + */ + +/* + * + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * modified by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_BFIN_H +#define _RTEMS_SCORE_BFIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * This file contains the information required to build + * RTEMS for a particular member of the Blackfin family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ +#if defined(__BFIN__) +#define CPU_MODEL_NAME "BF533" +#define BF_HAS_FPU 0 +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "BFIN" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h new file mode 100644 index 0000000000..7c90fc6575 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h @@ -0,0 +1,1001 @@ +/** + * @file + * + * @brief Blackfin CPU Department Source + * + * This include file contains information pertaining to the Blackfin + * processor. + */ + +/* + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * adapted to Blackfin by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/** + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * BFIN Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/** + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ISR_PASSES_FRAME_POINTER TRUE + +/** + * @def CPU_HARDWARE_FP + * + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? + * + * This feature conditional is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if ( BLACKFIN_CPU_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPUs in which this option has been used are the + * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and + * gcc both implicitly used the floating point registers to perform + * integer multiplies. Similarly, the PowerPC port of gcc has been + * seen to allocate floating point local variables and touch the FPU + * even when the flow through a subroutine (like vfprintf()) might + * not use floating point formats. + * + * If a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/** + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine @ref _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * @ref _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT + +/** + * @ingroup CPUInterrupt + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* may need to put some structures here. */ + +#ifndef ASM + +/** + * @defgroup CPUContext Processor Dependent Context Management + * + * From the highest level viewpoint, there are 2 types of context to save. + * + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +/**@{**/ + +/** + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ + +/* make sure this stays in sync with the assembly function + __CPU_Context_switch in cpu_asm.S */ +typedef struct { + uint32_t register_r4; + uint32_t register_r5; + uint32_t register_r6; + uint32_t register_r7; + + uint32_t register_p3; + uint32_t register_p4; + uint32_t register_p5; + uint32_t register_fp; + uint32_t register_sp; + + uint32_t register_rets; + + uint32_t imask; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->register_sp + +/** + * This defines the complete set of floating point registers that must + * be saved during any context switch from one thread to another. + */ +typedef struct { + /* FPU registers are listed here */ + /* Blackfin has no Floating Point */ +} Context_Control_fp; + +/** + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ +typedef struct { + /** This field is a hint that a port will have a number of integer + * registers that need to be saved when an interrupt occurs or + * when a context switch occurs at the end of an ISR. + */ + /*uint32_t special_interrupt_register;*/ +} CPU_Interrupt_frame; + +/** @} */ + +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in @ref _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * @note These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +/**@{**/ + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* XXX: if needed, put more variables here */ + +/** + * @ingroup CPUContext + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#endif /* ASM */ + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/** + * @ingroup CPUInterrupt + * This defines the number of entries in the @ref _ISR_Vector_table managed + * by RTEMS. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 + +/** + * @ingroup CPUInterrupt + * This defines the highest interrupt vector number for this port. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/** + * @ingroup CPUInterrupt + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable @a _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** @} */ + +/** + * @ingroup CPUContext + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_MINIMUM_SIZE (1024*8) + +#define CPU_SIZEOF_POINTER 4 + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALIGNMENT 8 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. + * + * @note This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. + * + * @note This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by @ref CPU_ALIGNMENT. If the + * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be + * set to 0. + * + * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_ALIGNMENT 8 + +#ifndef ASM + +/* + * ISR handler macros + */ + +/** + * @addtogroup CPUInterrupt + */ +/**@{**/ + +/** + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Initialize_vectors() + +/** + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in @a _isr_cookie. + * + * @param[out] _isr_cookie will contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Disable( _level ) \ + { \ + __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ + } + + +/** + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * @a _isr_cookie is not modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Enable( _level ) { \ + __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ + } + +/** + * This temporarily restores the interrupt to @a _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Flash( _level ) { \ + __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ + : : "d"(_level) : "R0" ); \ + } + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return level != 0; +} + +/** + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Set_level( _new_level ) \ + { \ + __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ + } + +/** + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * @note This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/** @} */ + +/* Context handler macros */ + +/** + * @ingroup CPUContext + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * @param[in] _the_context is the context structure to be initialized + * @param[in] _stack_base is the lowest physical address of this task's stack + * @param[in] _size is the size of this task's stack + * @param[in] _isr is the interrupt disable level + * @param[in] _entry_point is the thread's entry point. This is + * always @a _Thread_Handler + * @param[in] _is_fp is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * @param[in] tls_area is the thread-local storage (TLS) area + * + * Port Specific Information: + * + * See implementation in cpu.c + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/** + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. For many ports, simply adding a label to the restore path + * of @ref _CPU_Context_switch will work. On other ports, it may be + * possibly to load a few arguments and jump to the restore path. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Initialize_fp( _destination ) \ + memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Fatal_halt( _source, _error ) \ + { \ + __asm__ volatile ( "cli R1; \ + R1 = %0; \ + _halt: \ + idle; \ + jump _halt;"\ + : : "r" (_error) ); \ + } + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/** + * @brief CPU initialize. + * This routine performs CPU dependent initialization. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Initialize(void); + +/** + * @ingroup CPUInterrupt + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the raw ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the RTEMS ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * This routine installs the hardware interrupt stack pointer. + * + * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Install_interrupt_stack( void ); + +/** + * This routine is the CPU dependent IDLE thread body. + * + * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/** + * @addtogroup CPUContext + */ +/**@{**/ + +/** + * This routine switches from the run context to the heir context. + * + * @param[in] run points to the context of the currently executing task + * @param[in] heir points to the context of the heir task + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. + * + * @param[in] new_context points to the context to be restored. + * + * @note May be unnecessary to reload some registers. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/** + * This routine saves the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_restore_fp to restore this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * This routine restores the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area to restore + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_save_fp to save this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/** @} */ + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @ingroup CPUEndian + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +/** + * @ingroup CPUEndian + * This routine swaps a 16 bir quantity. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + */ +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..4f78c9d358 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h @@ -0,0 +1,27 @@ +/** + * @file + * + * @brief Blackfin Assembly File + * + * Defines a couple of Macros used in cpu_asm.S + */ + +/* + * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer + * and Antonio Giovanini + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + + + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/types.h b/cpukit/score/cpu/bfin/include/rtems/score/types.h new file mode 100644 index 0000000000..9865357cdd --- /dev/null +++ b/cpukit/score/cpu/bfin/include/rtems/score/types.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @brief Blackfin CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * Blackfin processor family. + */ + +/* + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +/** This defines the return type for an ISR entry point. */ +typedef void blackfin_isr; + +/** This defines the prototype for an ISR entry point. */ +typedef blackfin_isr ( *blackfin_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/bfin/preinstall.am b/cpukit/score/cpu/bfin/preinstall.am deleted file mode 100644 index 0ede1d7450..0000000000 --- a/cpukit/score/cpu/bfin/preinstall.am +++ /dev/null @@ -1,70 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/bfin - @: > $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/bfin/bfin.h: rtems/bfin/bfin.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bfin.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bfin.h - -$(PROJECT_INCLUDE)/rtems/bfin/bf533.h: rtems/bfin/bf533.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf533.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf533.h - -$(PROJECT_INCLUDE)/rtems/bfin/bf52x.h: rtems/bfin/bf52x.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/bfin.h: rtems/score/bfin.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/bfin.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/bfin.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/bfin/rtems/asm.h b/cpukit/score/cpu/bfin/rtems/asm.h deleted file mode 100644 index 5d133ddbdd..0000000000 --- a/cpukit/score/cpu/bfin/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h b/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h deleted file mode 100644 index 86142a6c62..0000000000 --- a/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h +++ /dev/null @@ -1,430 +0,0 @@ -/** - * @file - * - * @brief Basic MMR for the Blackfin 52x CPU - * - * This file defines basic MMR for the Blackfin 52x CPU. - * The MMR have been taken from the ADSP-BF52x Blackfin Processor - * Hardware Reference from Analog Devices. Mentioned Chapters - * refer to this Documentation. - * - * Based on bf533.h - */ - -/* - * COPYRIGHT (c) 2006. - * Atos Automacao Industrial LTDA. - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * Author: Rohan Kangralkar, ECE Department Northeastern University - * Date: 02/15/2011 - */ - -#ifndef _RTEMS_BFIN_52x_H -#define _RTEMS_BFIN_52x_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Clock and System Control Chapter 8 */ -#define PLL_CTL 0xFFC00000L -#define PLL_DIV 0xFFC00004L -#define VR_CTL 0xFFC00008L -#define PLL_STAT 0xFFC0000CL -#define PLL_LOCKCNT 0xFFC00010L -#define SWRST 0xFFC00100L -#define SYSCR 0xFFC00104L - -/* SPI Controller Chapter 10 */ -#define SPI_CTL 0xFFC00500L -#define SPI_FLG 0xFFC00504L -#define SPI_STAT 0xFFC00508L -#define SPI_TDBR 0xFFC0050CL -#define SPI_RDBR 0xFFC00510L -#define SPI_BAUD 0xFFC00514L -#define SPI_SHADOW 0xFFC00518L - -/* SPORT0 Controller */ -#define SPORT0_TCR1 0xFFC00800L -#define SPORT0_TCR2 0xFFC00804L -#define SPORT0_TCLKDIV 0xFFC00808L -#define SPORT0_TFSDIV 0xFFC0080CL -#define SPORT0_TX 0xFFC00810L -#define SPORT0_RX 0xFFC00818L -#define SPORT0_RCR1 0xFFC00820L -#define SPORT0_RCR2 0xFFC00824L -#define SPORT0_RCLKDIV 0xFFC00828L -#define SPORT0_RFSDIV 0xFFC0082CL -#define SPORT0_STAT 0xFFC00830L -#define SPORT0_CHNL 0xFFC00834L -#define SPORT0_MCMC1 0xFFC00838L -#define SPORT0_MCMC2 0xFFC0083CL -#define SPORT0_MTCS0 0xFFC00840L -#define SPORT0_MTCS1 0xFFC00844L -#define SPORT0_MTCS2 0xFFC00848L -#define SPORT0_MTCS3 0xFFC0084CL -#define SPORT0_MRCS0 0xFFC00850L -#define SPORT0_MRCS1 0xFFC00854L -#define SPORT0_MRCS2 0xFFC00858L -#define SPORT0_MRCS3 0xFFC0085CL - -/* Parallel Peripheral Interface (PPI) Chapter 11 */ - -#define PPI_CONTROL 0xFFC01000L -#define PPI_STATUS 0xFFC01004L -#define PPI_COUNT 0xFFC01008L -#define PPI_DELAY 0xFFC0100CL -#define PPI_FRAME 0xFFC01010L - -/********* PPI MASKS ***********/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 -#define PORT_DIR 0x00000002 -#define XFR_TYPE 0x0000000C -#define PORT_CFG 0x00000030 -#define FLD_SEL 0x00000040 -#define PACK_EN 0x00000080 -#define DMA32 0x00000100 -#define SKIP_EN 0x00000200 -#define SKIP_EO 0x00000400 -#define DLENGTH 0x00003800 -#define DLEN_8 0x0 -#define DLEN(x) (((x-9) & 0x07) << 11) -#define POL 0x0000C000 - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 -#define FT_ERR 0x00000800 -#define OVR 0x00001000 -#define UNDR 0x00002000 -#define ERR_DET 0x00004000 -#define ERR_NCOR 0x00008000 - -/* SPORT1 Controller Chapter 12 */ -#define SPORT1_TCR1 0xFFC00900L -#define SPORT1_TCR2 0xFFC00904L -#define SPORT1_TCLKDIV 0xFFC00908L -#define SPORT1_TFSDIV 0xFFC0090CL -#define SPORT1_TX 0xFFC00910L -#define SPORT1_RX 0xFFC00918L -#define SPORT1_RCR1 0xFFC00920L -#define SPORT1_RCR2 0xFFC00924L -#define SPORT1_RCLKDIV 0xFFC00928L -#define SPORT1_RFSDIV 0xFFC0092CL -#define SPORT1_STAT 0xFFC00930L -#define SPORT1_CHNL 0xFFC00934L -#define SPORT1_MCMC1 0xFFC00938L -#define SPORT1_MCMC2 0xFFC0093CL -#define SPORT1_MTCS0 0xFFC00940L -#define SPORT1_MTCS1 0xFFC00944L -#define SPORT1_MTCS2 0xFFC00948L -#define SPORT1_MTCS3 0xFFC0094CL -#define SPORT1_MRCS0 0xFFC00950L -#define SPORT1_MRCS1 0xFFC00954L -#define SPORT1_MRCS2 0xFFC00958L -#define SPORT1_MRCS3 0xFFC0095CL - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 -#define ITCLK 0x0002 -#define TDTYPE 0x000C -#define TLSBIT 0x0010 -#define ITFS 0x0200 -#define TFSR 0x0400 -#define DITFS 0x0800 -#define LTFS 0x1000 -#define LATFS 0x2000 -#define TCKFE 0x4000 - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F -#define TXSE 0x0100 -#define TSFSE 0x0200 -#define TRFST 0x0400 - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 -#define IRCLK 0x0002 -#define RDTYPE 0x000C -#define RULAW 0x0008 -#define RALAW 0x000C -#define RLSBIT 0x0010 -#define IRFS 0x0200 -#define RFSR 0x0400 -#define LRFS 0x1000 -#define LARFS 0x2000 -#define RCKFE 0x4000 - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F -#define RXSE 0x0100 -#define RSFSE 0x0200 -#define RRFST 0x0400 - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 -#define RUVF 0x0002 -#define ROVF 0x0004 -#define TXF 0x0008 -#define TUVF 0x0010 -#define TOVF 0x0020 -#define TXHRE 0x0040 - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 -#define WOFF 0x000003FF - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 -#define MCDTXPE 0x00000004 -#define MCDRXPE 0x00000008 -#define MCMEN 0x00000010 -#define FSDR 0x00000080 -#define MFD 0x0000F000 - -/* UART Controller Chapter 13 */ -#define UART_THR 0xFFC00400L -#define UART_RBR 0xFFC00400L -#define UART_DLL 0xFFC00400L -#define UART_IER 0xFFC00404L -#define UART_DLH 0xFFC00404L -#define UART_IIR 0xFFC00408L -#define UART_LCR 0xFFC0040CL -#define UART_MCR 0xFFC00410L -#define UART_LSR 0xFFC00414L -#define UART_SCR 0xFFC0041CL -#define UART_GCTL 0xFFC00424L - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* General Purpose IO Chapter 14*/ -#define FIO_FLAG_D 0xFFC00700L -#define FIO_FLAG_C 0xFFC00704L -#define FIO_FLAG_S 0xFFC00708L -#define FIO_FLAG_T 0xFFC0070CL -#define FIO_MASKA_D 0xFFC00710L -#define FIO_MASKA_C 0xFFC00714L -#define FIO_MASKA_S 0xFFC00718L -#define FIO_MASKA_T 0xFFC0071CL -#define FIO_MASKB_D 0xFFC00720L -#define FIO_MASKB_C 0xFFC00724L -#define FIO_MASKB_S 0xFFC00728L -#define FIO_MASKB_T 0xFFC0072CL -#define FIO_DIR 0xFFC00730L -#define FIO_POLAR 0xFFC00734L -#define FIO_EDGE 0xFFC00738L -#define FIO_BOTH 0xFFC0073CL -#define FIO_INEN 0xFFC00740L - - -/* General Purpose IO Chapter 9*/ -#define PORTH_FER 0xFFC03208 -#define PORTH_MUX 0xFFC03218 -#define PORTHIO_DIR 0xFFC01730 -#define PORTHIO_INEN 0xFFC01740 -#define PORTHIO 0xFFC01700 -#define PORTHIO_SET 0xFFC01708 -#define PORTHIO_CLEAR 0xFFC01704 -#define PORTHIO_TOGGLE 0xFFC0170C - - -#define FIO_INEN 0xFFC00740L -#define FIO_POLAR 0xFFC00734L -#define FIO_EDGE 0xFFC00738L -#define FIO_BOTH 0xFFC0073CL - - - -#define FIO_FLAG_C 0xFFC00704L -#define FIO_FLAG_S 0xFFC00708L -#define FIO_FLAG_T 0xFFC0070CL -#define FIO_MASKA_D 0xFFC00710L -#define FIO_MASKA_C 0xFFC00714L -#define FIO_MASKA_S 0xFFC00718L -#define FIO_MASKA_T 0xFFC0071CL -#define FIO_MASKB_D 0xFFC00720L -#define FIO_MASKB_C 0xFFC00724L -#define FIO_MASKB_S 0xFFC00728L -#define FIO_MASKB_T 0xFFC0072CL - - -/* General Purpose IO Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - - -/* TIMER 0, 1, 2 Chapter 15 */ -#define TIMER0_CONFIG 0xFFC00600L -#define TIMER0_COUNTER 0xFFC00604L -#define TIMER0_PERIOD 0xFFC00608L -#define TIMER0_WIDTH 0xFFC0060CL - -#define TIMER1_CONFIG 0xFFC00610L -#define TIMER1_COUNTER 0xFFC00614L -#define TIMER1_PERIOD 0xFFC00618L -#define TIMER1_WIDTH 0xFFC0061CL - -#define TIMER2_CONFIG 0xFFC00620L -#define TIMER2_COUNTER 0xFFC00624L -#define TIMER2_PERIOD 0xFFC00628L -#define TIMER2_WIDTH 0xFFC0062CL - -#define TIMER_ENABLE 0xFFC00640L -#define TIMER_DISABLE 0xFFC00644L -#define TIMER_STATUS 0xFFC00648L - -/* Real Time Clock Chapter 16 */ -#define RTC_STAT 0xFFC00300L -#define RTC_ICTL 0xFFC00304L -#define RTC_ISTAT 0xFFC00308L -#define RTC_SWCNT 0xFFC0030CL -#define RTC_ALARM 0xFFC00310L -#define RTC_FAST 0xFFC00314L -#define RTC_PREN 0xFFC00314L - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 -#define PREN 0x00000001 - -/* Asynchronous Memory Controller EBUI, Chapter 17*/ -#define EBIU_AMGCTL 0xFFC00A00L -#define EBIU_AMBCTL0 0xFFC00A04L -#define EBIU_AMBCTL1 0xFFC00A08L - -/* SDRAM Controller External Bus Interface Unit */ - -#define EBIU_SDGCTL 0xFFC00A10L -#define EBIU_SDBCTL 0xFFC00A14L -#define EBIU_SDRRC 0xFFC00A18L -#define EBIU_SDSTAT 0xFFC00A1CL - - - - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/*** Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ -/*** Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ -/*** ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ -/*** DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ - /* 1= allocate cache lines on write-through writes. */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h deleted file mode 100644 index 682aad4bbb..0000000000 --- a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h +++ /dev/null @@ -1,396 +0,0 @@ -/** - * @file - * - * @brief Basic MMR for the Blackfin 531/532/533 CPU - * - * This file defines basic MMR for the Blackfin 531/532/533 CPU. - * The MMR have been taken from the ADSP-BF533 Blackfin Processor - * Hardware Reference from Analog Devices. Mentioned Chapters - * refer to this Documentation. - * - * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF) - * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined - * in bfin.h which is included. - */ -/* - * COPYRIGHT (c) 2006. - * Atos Automacao Industrial LTDA. - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_BFIN_533_H -#define _RTEMS_BFIN_533_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Clock and System Control Chapter 8 */ -#define PLL_CTL 0xFFC00000L -#define PLL_DIV 0xFFC00004L -#define VR_CTL 0xFFC00008L -#define PLL_STAT 0xFFC0000CL -#define PLL_LOCKCNT 0xFFC00010L -#define SWRST 0xFFC00100L -#define SYSCR 0xFFC00104L - -/* SPI Controller Chapter 10 */ -#define SPI_CTL 0xFFC00500L -#define SPI_FLG 0xFFC00504L -#define SPI_STAT 0xFFC00508L -#define SPI_TDBR 0xFFC0050CL -#define SPI_RDBR 0xFFC00510L -#define SPI_BAUD 0xFFC00514L -#define SPI_SHADOW 0xFFC00518L - -/* SPORT0 Controller */ -#define SPORT0_TCR1 0xFFC00800L -#define SPORT0_TCR2 0xFFC00804L -#define SPORT0_TCLKDIV 0xFFC00808L -#define SPORT0_TFSDIV 0xFFC0080CL -#define SPORT0_TX 0xFFC00810L -#define SPORT0_RX 0xFFC00818L -#define SPORT0_RCR1 0xFFC00820L -#define SPORT0_RCR2 0xFFC00824L -#define SPORT0_RCLKDIV 0xFFC00828L -#define SPORT0_RFSDIV 0xFFC0082CL -#define SPORT0_STAT 0xFFC00830L -#define SPORT0_CHNL 0xFFC00834L -#define SPORT0_MCMC1 0xFFC00838L -#define SPORT0_MCMC2 0xFFC0083CL -#define SPORT0_MTCS0 0xFFC00840L -#define SPORT0_MTCS1 0xFFC00844L -#define SPORT0_MTCS2 0xFFC00848L -#define SPORT0_MTCS3 0xFFC0084CL -#define SPORT0_MRCS0 0xFFC00850L -#define SPORT0_MRCS1 0xFFC00854L -#define SPORT0_MRCS2 0xFFC00858L -#define SPORT0_MRCS3 0xFFC0085CL - -/* Parallel Peripheral Interface (PPI) Chapter 11 */ - -#define PPI_CONTROL 0xFFC01000L -#define PPI_STATUS 0xFFC01004L -#define PPI_COUNT 0xFFC01008L -#define PPI_DELAY 0xFFC0100CL -#define PPI_FRAME 0xFFC01010L - -/********* PPI MASKS ***********/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 -#define PORT_DIR 0x00000002 -#define XFR_TYPE 0x0000000C -#define PORT_CFG 0x00000030 -#define FLD_SEL 0x00000040 -#define PACK_EN 0x00000080 -#define DMA32 0x00000100 -#define SKIP_EN 0x00000200 -#define SKIP_EO 0x00000400 -#define DLENGTH 0x00003800 -#define DLEN_8 0x0 -#define DLEN(x) (((x-9) & 0x07) << 11) -#define POL 0x0000C000 - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 -#define FT_ERR 0x00000800 -#define OVR 0x00001000 -#define UNDR 0x00002000 -#define ERR_DET 0x00004000 -#define ERR_NCOR 0x00008000 - -/* SPORT1 Controller Chapter 12 */ -#define SPORT1_TCR1 0xFFC00900L -#define SPORT1_TCR2 0xFFC00904L -#define SPORT1_TCLKDIV 0xFFC00908L -#define SPORT1_TFSDIV 0xFFC0090CL -#define SPORT1_TX 0xFFC00910L -#define SPORT1_RX 0xFFC00918L -#define SPORT1_RCR1 0xFFC00920L -#define SPORT1_RCR2 0xFFC00924L -#define SPORT1_RCLKDIV 0xFFC00928L -#define SPORT1_RFSDIV 0xFFC0092CL -#define SPORT1_STAT 0xFFC00930L -#define SPORT1_CHNL 0xFFC00934L -#define SPORT1_MCMC1 0xFFC00938L -#define SPORT1_MCMC2 0xFFC0093CL -#define SPORT1_MTCS0 0xFFC00940L -#define SPORT1_MTCS1 0xFFC00944L -#define SPORT1_MTCS2 0xFFC00948L -#define SPORT1_MTCS3 0xFFC0094CL -#define SPORT1_MRCS0 0xFFC00950L -#define SPORT1_MRCS1 0xFFC00954L -#define SPORT1_MRCS2 0xFFC00958L -#define SPORT1_MRCS3 0xFFC0095CL - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 -#define ITCLK 0x0002 -#define TDTYPE 0x000C -#define TLSBIT 0x0010 -#define ITFS 0x0200 -#define TFSR 0x0400 -#define DITFS 0x0800 -#define LTFS 0x1000 -#define LATFS 0x2000 -#define TCKFE 0x4000 - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F -#define TXSE 0x0100 -#define TSFSE 0x0200 -#define TRFST 0x0400 - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 -#define IRCLK 0x0002 -#define RDTYPE 0x000C -#define RULAW 0x0008 -#define RALAW 0x000C -#define RLSBIT 0x0010 -#define IRFS 0x0200 -#define RFSR 0x0400 -#define LRFS 0x1000 -#define LARFS 0x2000 -#define RCKFE 0x4000 - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F -#define RXSE 0x0100 -#define RSFSE 0x0200 -#define RRFST 0x0400 - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 -#define RUVF 0x0002 -#define ROVF 0x0004 -#define TXF 0x0008 -#define TUVF 0x0010 -#define TOVF 0x0020 -#define TXHRE 0x0040 - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 -#define WOFF 0x000003FF - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 -#define MCDTXPE 0x00000004 -#define MCDRXPE 0x00000008 -#define MCMEN 0x00000010 -#define FSDR 0x00000080 -#define MFD 0x0000F000 - -/* UART Controller Chapter 13 */ -#define UART_THR 0xFFC00400L -#define UART_RBR 0xFFC00400L -#define UART_DLL 0xFFC00400L -#define UART_IER 0xFFC00404L -#define UART_DLH 0xFFC00404L -#define UART_IIR 0xFFC00408L -#define UART_LCR 0xFFC0040CL -#define UART_MCR 0xFFC00410L -#define UART_LSR 0xFFC00414L -#define UART_SCR 0xFFC0041CL -#define UART_GCTL 0xFFC00424L - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* General Purpose IO Chapter 14*/ -#define FIO_FLAG_D 0xFFC00700L -#define FIO_FLAG_C 0xFFC00704L -#define FIO_FLAG_S 0xFFC00708L -#define FIO_FLAG_T 0xFFC0070CL -#define FIO_MASKA_D 0xFFC00710L -#define FIO_MASKA_C 0xFFC00714L -#define FIO_MASKA_S 0xFFC00718L -#define FIO_MASKA_T 0xFFC0071CL -#define FIO_MASKB_D 0xFFC00720L -#define FIO_MASKB_C 0xFFC00724L -#define FIO_MASKB_S 0xFFC00728L -#define FIO_MASKB_T 0xFFC0072CL -#define FIO_DIR 0xFFC00730L -#define FIO_POLAR 0xFFC00734L -#define FIO_EDGE 0xFFC00738L -#define FIO_BOTH 0xFFC0073CL -#define FIO_INEN 0xFFC00740L - -/* General Purpose IO Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - - -/* TIMER 0, 1, 2 Chapter 15 */ -#define TIMER0_CONFIG 0xFFC00600L -#define TIMER0_COUNTER 0xFFC00604L -#define TIMER0_PERIOD 0xFFC00608L -#define TIMER0_WIDTH 0xFFC0060CL - -#define TIMER1_CONFIG 0xFFC00610L -#define TIMER1_COUNTER 0xFFC00614L -#define TIMER1_PERIOD 0xFFC00618L -#define TIMER1_WIDTH 0xFFC0061CL - -#define TIMER2_CONFIG 0xFFC00620L -#define TIMER2_COUNTER 0xFFC00624L -#define TIMER2_PERIOD 0xFFC00628L -#define TIMER2_WIDTH 0xFFC0062CL - -#define TIMER_ENABLE 0xFFC00640L -#define TIMER_DISABLE 0xFFC00644L -#define TIMER_STATUS 0xFFC00648L - -/* Real Time Clock Chapter 16 */ -#define RTC_STAT 0xFFC00300L -#define RTC_ICTL 0xFFC00304L -#define RTC_ISTAT 0xFFC00308L -#define RTC_SWCNT 0xFFC0030CL -#define RTC_ALARM 0xFFC00310L -#define RTC_FAST 0xFFC00314L -#define RTC_PREN 0xFFC00314L - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 -#define PREN 0x00000001 - -/* Asynchronous Memory Controller EBUI, Chapter 17*/ -#define EBIU_AMGCTL 0xFFC00A00L -#define EBIU_AMBCTL0 0xFFC00A04L -#define EBIU_AMBCTL1 0xFFC00A08L - -/* SDRAM Controller External Bus Interface Unit */ - -#define EBIU_SDGCTL 0xFFC00A10L -#define EBIU_SDBCTL 0xFFC00A14L -#define EBIU_SDRRC 0xFFC00A18L -#define EBIU_SDSTAT 0xFFC00A1CL - - - - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/*** Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ -/*** Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ -/*** ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ -/*** DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ - /* 1= allocate cache lines on write-through writes. */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h deleted file mode 100644 index 4ba0b2b295..0000000000 --- a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file - * - * @brief Macros for MMR register common to all Blackfin Processors - * - * This file defines Macros for MMR register common to all Blackfin - * Processors. - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_BFIN_BFIN_H -#define _RTEMS_BFIN_BFIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Scratchpad SRAM */ - -#define SCRATCH 0xFFB00000 -#define SCRATCH_SIZE 0x1000 -#define SCRATCH_TOP 0xFFB00ffc - - -/* System Interrupt Controller Chapter 4*/ -#define SIC_RVECT 0xFFC00108 -#define SIC_IMASK 0xFFC0010C -#define SIC_IAR0 0xFFC00110 -#define SIC_IAR1 0xFFC00114 -#define SIC_IAR2 0xFFC00118 -#define SIC_ISR 0xFFC00120 -#define SIC_IWR 0xFFC00124 - -/* Event Vector Table Chapter 4 */ - -#define EVT0 0xFFE02000 -#define EVT1 0xFFE02004 -#define EVT2 0xFFE02008 -#define EVT3 0xFFE0200C -#define EVT4 0xFFE02010 -#define EVT5 0xFFE02014 -#define EVT6 0xFFE02018 -#define EVT7 0xFFE0201C -#define EVT8 0xFFE02020 -#define EVT9 0xFFE02024 -#define EVT10 0xFFE02028 -#define EVT11 0xFFE0202C -#define EVT12 0xFFE02030 -#define EVT13 0xFFE02034 -#define EVT14 0xFFE02038 -#define EVT15 0xFFE0203C -#define IMASK 0xFFE02104 -#define IPEND 0xFFE02108 -#define ILAT 0xFFE0210C -#define IPRIO 0xFFE02110 - - -#define TCNTL 0xFFE03000 -#define TPERIOD 0xFFE03004 -#define TSCALE 0xFFE03008 -#define TCOUNT 0xFFE0300C - -/* Masks for Timer Control */ -#define TMPWR 0x00000001 -#define TMREN 0x00000002 -#define TAUTORLD 0x00000004 -#define TINT 0x00000008 - -/* Event Bit Positions */ -#define EVT_IVTMR_P 0x00000006 - -#define EVT_IVTMR (1 << EVT_IVTMR_P) - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/score/bfin.h b/cpukit/score/cpu/bfin/rtems/score/bfin.h deleted file mode 100644 index caa3a51830..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/bfin.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * - * @brief Blackfin Set up Basic CPU Dependency Settings Based on - * Compiler Settings - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the Blackfin port. - */ - -/* - * - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_BFIN_H -#define _RTEMS_SCORE_BFIN_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* - * This file contains the information required to build - * RTEMS for a particular member of the Blackfin family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ -#if defined(__BFIN__) -#define CPU_MODEL_NAME "BF533" -#define BF_HAS_FPU 0 -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "BFIN" - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h deleted file mode 100644 index 7c90fc6575..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpu.h +++ /dev/null @@ -1,1001 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Department Source - * - * This include file contains information pertaining to the Blackfin - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * adapted to Blackfin by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * BFIN Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER TRUE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( BLACKFIN_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -#ifndef ASM - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ - -/* make sure this stays in sync with the assembly function - __CPU_Context_switch in cpu_asm.S */ -typedef struct { - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - - uint32_t register_p3; - uint32_t register_p4; - uint32_t register_p5; - uint32_t register_fp; - uint32_t register_sp; - - uint32_t register_rets; - - uint32_t imask; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /* FPU registers are listed here */ - /* Blackfin has no Floating Point */ -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - /*uint32_t special_interrupt_register;*/ -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif /* ASM */ - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 - -/** - * @ingroup CPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 8 - -#ifndef ASM - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _level ) \ - { \ - __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ - } - - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _level ) { \ - __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ - } - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _level ) { \ - __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ - : : "d"(_level) : "R0" ); \ - } - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return level != 0; -} - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ - } - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * See implementation in cpu.c - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - __asm__ volatile ( "cli R1; \ - R1 = %0; \ - _halt: \ - idle; \ - jump _halt;"\ - : : "r" (_error) ); \ - } - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h deleted file mode 100644 index 4f78c9d358..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h +++ /dev/null @@ -1,27 +0,0 @@ -/** - * @file - * - * @brief Blackfin Assembly File - * - * Defines a couple of Macros used in cpu_asm.S - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/bfin/rtems/score/cpuatomic.h b/cpukit/score/cpu/bfin/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/bfin/rtems/score/types.h b/cpukit/score/cpu/bfin/rtems/score/types.h deleted file mode 100644 index 9865357cdd..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/types.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Blackfin processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the return type for an ISR entry point. */ -typedef void blackfin_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef blackfin_isr ( *blackfin_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/epiphany/Makefile.am b/cpukit/score/cpu/epiphany/Makefile.am index ed99b436e6..96b0de0054 100644 --- a/cpukit/score/cpu/epiphany/Makefile.am +++ b/cpukit/score/cpu/epiphany/Makefile.am @@ -3,21 +3,6 @@ include $(top_srcdir)/automake/compile.am CLEANFILES = DISTCLEANFILES = -include_rtemsdir = $(includedir)/rtems - -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score - -include_rtems_score_HEADERS = -include_rtems_score_HEADERS += rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/epiphany.h -include_rtems_score_HEADERS += rtems/score/epiphany-utility.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c @@ -29,5 +14,5 @@ libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) all-local: $(PREINSTALL_FILES) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/epiphany/headers.am b/cpukit/score/cpu/epiphany/headers.am new file mode 100644 index 0000000000..125a88dcd9 --- /dev/null +++ b/cpukit/score/cpu/epiphany/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/epiphany-utility.h +include_rtems_score_HEADERS += include/rtems/score/epiphany.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/epiphany/include/rtems/asm.h b/cpukit/score/cpu/epiphany/include/rtems/asm.h new file mode 100644 index 0000000000..87e0cca1cb --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/asm.h @@ -0,0 +1,120 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __EPIPHANY_ASM_H +#define __EPIPHANY_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .extern SYM (sym) +#define TYPE_FUNC(sym) .type SYM (sym), %function + +#endif diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h new file mode 100644 index 0000000000..34ac8ae6c6 --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h @@ -0,0 +1,873 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _EPIPHANY_CPU_H +#define _EPIPHANY_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* pick up machine definitions */ +#include +#ifndef ASM +#include +#include +#include /* for printk */ +#endif + +/* conditional compilation parameters */ + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Currently, for epiphany port, _ISR_Handler is responsible for switching to + * RTEMS dedicated interrupt task. + * + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE + * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + */ + +#define CPU_ISR_PASSES_FRAME_POINTER TRUE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "epiphany_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + * + * The CPU_SOFTWARE_FP is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * epiphany Specific Information: + * + * At this time there are no implementations of Epiphany that are + * expected to implement floating point. + */ + +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + */ + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + * + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 64 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/* + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * epiphany Specific Information: + * + * This version of RTEMS is designed specifically to run with + * big endian architectures. If you want little endian, you'll + * have to make the appropriate adjustments here and write + * efficient routines for byte swapping. The epiphany architecture + * doesn't do this very well. + */ + +#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + */ + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/* + * Processor defined structures required for cpukit/score. + */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * + */ +#ifndef ASM + +typedef struct { + uint32_t r[64]; + + uint32_t status; + uint32_t config; + uint32_t iret; + +#ifdef RTEMS_SMP + /** + * @brief On SMP configurations the thread context must contain a boolean + * indicator to signal if this context is executing on a processor. + * + * This field must be updated during a context switch. The context switch + * to the heir must wait until the heir context indicates that it is no + * longer executing on a processor. The context switch must also check if + * a thread dispatch is necessary to honor updates of the heir thread for + * this processor. This indicator must be updated using an atomic test and + * set operation to ensure that at most one processor uses the heir + * context at the same time. + * + * @code + * void _CPU_Context_switch( + * Context_Control *executing, + * Context_Control *heir + * ) + * { + * save( executing ); + * + * executing->is_executing = false; + * memory_barrier(); + * + * if ( test_and_set( &heir->is_executing ) ) { + * do { + * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); + * + * if ( cpu_self->dispatch_necessary ) { + * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); + * } + * } while ( test_and_set( &heir->is_executing ) ); + * } + * + * restore( heir ); + * } + * @endcode + */ + volatile bool is_executing; +#endif +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r[13] + +typedef struct { + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +typedef Context_Control CPU_Interrupt_frame; + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * epiphany Specific Information: + * + */ + +#define CPU_CONTEXT_FP_SIZE 0 + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * Should be large enough to run all RTEMS tests. This insures + * that a "reasonable" small application should not have any problems. + * + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + */ + +#define CPU_ALIGNMENT 8 + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + * + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + */ + +#define CPU_STACK_ALIGNMENT 8 + +/* ISR handler macros */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + * + */ + +static inline uint32_t epiphany_interrupt_disable( void ) +{ + uint32_t sr; + __asm__ __volatile__ ("movfs %[sr], status \n" : [sr] "=r" (sr):); + __asm__ __volatile__("gid \n"); + return sr; +} + +static inline void epiphany_interrupt_enable(uint32_t level) +{ + __asm__ __volatile__("gie \n"); + __asm__ __volatile__ ("movts status, %[level] \n" :: [level] "r" (level):); +} + +#define _CPU_ISR_Disable( _level ) \ + _level = epiphany_interrupt_disable() + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + * + */ + +#define _CPU_ISR_Enable( _level ) \ + epiphany_interrupt_enable( _level ) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + * + */ + +#define _CPU_ISR_Flash( _level ) \ + do{ \ + if ( (_level & 0x2) != 0 ) \ + _CPU_ISR_Enable( _level ); \ + epiphany_interrupt_disable(); \ + } while(0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & 0x2 ) != 0; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * The get routine usually must be implemented as a subroutine. + * + */ + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + */ + +/** + * @brief Account for GCC red-zone + * + * The following macro is used when initializing task's stack + * to account for GCC red-zone. + */ + +#define EPIPHANY_GCC_RED_ZONE_SIZE 128 + +/** + * @brief Initializes the CPU context. + * + * The following steps are performed: + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * + * @param[in] context points to the context area + * @param[in] stack_area_begin is the low address of the allocated stack area + * @param[in] stack_area_size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to @c true if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + */ +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ) + +#define _CPU_Context_Initialize_fp( _destination ) \ + memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + */ + +#include + +#define _CPU_Fatal_halt(_source, _error ) \ + printk("Fatal Error %d.%" PRIu32 " Halted\n",_source, _error); \ + asm("trap 3" :: "r" (_error)); \ + for(;;) + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#endif /* ASM */ + +/** + * Size of a pointer. + * + * This must be an integer literal that can be used by the assembler. This + * value will be used to calculate offsets of structure members. These + * offsets will be used in assembler code. + */ +#define CPU_SIZEOF_POINTER 4 +#define CPU_EXCEPTION_FRAME_SIZE 260 + +#define CPU_MAXIMUM_PROCESSORS 32 + +#ifndef ASM + +typedef struct { + uint32_t r[62]; + uint32_t status; + uint32_t config; + uint32_t iret; +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + * + */ + +void _CPU_Initialize( + void +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + * + * epiphany Specific Information: + * + * Please see the comments in the .c file for a description of how + * this function works. There are several things to be aware of. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + * + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + * + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to insure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + */ + +static inline unsigned int CPU_swap_u32( + unsigned int value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/epiphany/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..cc091fa909 --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief Epiphany Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/epiphany/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/epiphany/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/epiphany-utility.h b/cpukit/score/cpu/epiphany/include/rtems/score/epiphany-utility.h new file mode 100644 index 0000000000..bf223f93bf --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/epiphany-utility.h @@ -0,0 +1,180 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief This include file contains macros pertaining to the + * Epiphany processor family. + */ + +/* + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _EPIPHANY_UTILITY_H +#define _EPIPHANY_UTILITY_H + +/* eCore IRQs */ +typedef enum +{ + START, + SW_EXCEPTION, + MEM_FAULT, + TIMER0, + TIMER1, + SMP_MESSAGE, + DMA0, + DMA1, + SER, +} EPIPHANY_IRQ_PER_CORE_T; + +/* Per-core IO mapped register addresses + * @see Epiphany architecture reference. + */ +#define EPIPHANY_PER_CORE_REG_CONFIG 0xF0400 +#define EPIPHANY_PER_CORE_REG_STATUS 0xF0404 +#define EPIPHANY_PER_CORE_REG_PC 0xF0408 +#define EPIPHANY_PER_CORE_REG_DEBUGSTATUS 0xF040C +#define EPIPHANY_PER_CORE_REG_LC 0xF0414 +#define EPIPHANY_PER_CORE_REG_LS 0xF0418 +#define EPIPHANY_PER_CORE_REG_LE 0xF041C +#define EPIPHANY_PER_CORE_REG_IRET 0xF0420 +#define EPIPHANY_PER_CORE_REG_IMASK 0xF0424 +#define EPIPHANY_PER_CORE_REG_ILAT 0xF0428 +#define EPIPHANY_PER_CORE_REG_ILATST 0xF042C +#define EPIPHANY_PER_CORE_REG_ILATCL 0xF0430 +#define EPIPHANY_PER_CORE_REG_IPEND 0xF0434 +#define EPIPHANY_PER_CORE_REG_FSTATUS 0xF0440 +#define EPIPHANY_PER_CORE_REG_DEBUGCMD 0xF0448 +#define EPIPHANY_PER_CORE_REG_RESETCORE 0xF070C + +/* Event timer registers */ +#define EPIPHANY_PER_CORE_REG_CTIMER0 0xF0438 +#define EPIPHANY_PER_CORE_REG_CTIMER1 0xF043C + +/* Processor control registers */ +#define EPIPHANY_PER_CORE_REG_MEMSTATUS 0xF0604 +#define EPIPHANY_PER_CORE_REG_MEMPROTECT 0xF0608 + +/* DMA Registers */ +#define EPIPHANY_PER_CORE_REG_DMA0CONFIG 0xF0500 +#define EPIPHANY_PER_CORE_REG_DMA0STRIDE 0xF0504 +#define EPIPHANY_PER_CORE_REG_DMA0COUNT 0xF0508 +#define EPIPHANY_PER_CORE_REG_DMA0SRCADDR 0xF050C +#define EPIPHANY_PER_CORE_REG_DMA0DSTADDR 0xF0510 +#define EPIPHANY_PER_CORE_REG_DMA0AUTO0 0xF0514 +#define EPIPHANY_PER_CORE_REG_DMA0AUTO1 0xF0518 +#define EPIPHANY_PER_CORE_REG_DMA0STATUS 0xF051C +#define EPIPHANY_PER_CORE_REG_DMA1CONFIG 0xF0520 +#define EPIPHANY_PER_CORE_REG_DMA1STRIDE 0xF0524 +#define EPIPHANY_PER_CORE_REG_DMA1COUNT 0xF0528 +#define EPIPHANY_PER_CORE_REG_DMA1SRCADDR 0xF052C +#define EPIPHANY_PER_CORE_REG_DMA1DSTADDR 0xF0530 +#define EPIPHANY_PER_CORE_REG_DMA1AUTO0 0xF0534 +#define EPIPHANY_PER_CORE_REG_DMA1AUTO1 0xF0538 +#define EPIPHANY_PER_CORE_REG_DMA1STATUS 0xF053C + +/* Mesh Node Control Registers */ +#define EPIPHANY_PER_CORE_REG_MESHCONFIG 0xF0700 +#define EPIPHANY_PER_CORE_REG_COREID 0xF0704 +#define EPIPHANY_PER_CORE_REG_MULTICAST 0xF0708 +#define EPIPHANY_PER_CORE_REG_CMESHROUTE 0xF0710 +#define EPIPHANY_PER_CORE_REG_XMESHROUTE 0xF0714 +#define EPIPHANY_PER_CORE_REG_RMESHROUTE 0xF0718 + +/* This macros constructs an address space of epiphany cores + * from their IDs. + */ +#define EPIPHANY_COREID_TO_MSB_ADDR(id) (id) << 20 + +/* Construct a complete/absolute IO mapped address register from + * core ID and register name + */ +#define EPIPHANY_GET_REG_ABSOLUTE_ADDR(coreid, reg) \ + (EPIPHANY_COREID_TO_MSB_ADDR(coreid) | (reg)) + +#define EPIPHANY_REG(reg) (uint32_t *) (reg) + +/* Read register with its absolute address */ +static inline uint32_t read_epiphany_reg(volatile uint32_t reg_addr) +{ + return *(EPIPHANY_REG(reg_addr)); +} + +/* Write register with its abolute address */ +static inline void write_epiphany_reg(volatile uint32_t reg_addr, uint32_t val) +{ + *(EPIPHANY_REG(reg_addr)) = val; +} + +/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses + * linear IDs. The following function converts RTEMS linear IDs to + * Epiphany corresponding ones + */ +static const uint32_t map[16] = +{ + 0x808, 0x809, 0x80A, 0x80B, + 0x848, 0x849, 0x84A, 0x84B, + 0x888, 0x889, 0x88A, 0x88B, + 0x8C8, 0x8C9, 0x8CA, 0x8CB +}; + +static inline uint32_t rtems_coreid_to_epiphany_map(uint32_t rtems_id) +{ + return map[rtems_id]; +} + +/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses + * linear IDs. The following function is used to map Epiphany IDs to + * RTEMS linear IDs. + */ +static inline uint32_t epiphany_coreid_to_rtems_map(uint32_t epiphany_id) +{ + register uint32_t coreid asm ("r17") = epiphany_id; + + /* Mapping from Epiphany IDs to 0-16 IDs macro */ + __asm__ __volatile__(" \ + movfs r17, coreid \ + mov r19, #0x003 \ + mov r20, #0x0F0 \ + and r19, r17, r19 \ + and r20, r17, r20 \ + lsr r20, r20, #4 \ + add r17, r19, r20 \ + "); + + /* coreid or r17 now holds the rtems core id */ + return coreid; +} + +static inline uint32_t _Epiphany_Get_current_processor() +{ + uint32_t coreid; + + asm volatile ("movfs %0, coreid" : "=r" (coreid): ); + + return epiphany_coreid_to_rtems_map(coreid); +} +#endif /* _EPIPHANY_UTILITY_H */ diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/epiphany.h b/cpukit/score/cpu/epiphany/include/rtems/score/epiphany.h new file mode 100644 index 0000000000..60d975581f --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/epiphany.h @@ -0,0 +1,64 @@ +/** + * @file rtems/score/epiphany.h + */ + +/* + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_EPIPHANY_H +#define _RTEMS_SCORE_EPIPHANY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the Epiphany family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + + /* + * Define the name of the CPU family and specific model. + */ + +#define CPU_NAME "EPIPHANY" +#define CPU_MODEL_NAME "EPIPHANY" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_EPIPHANY_H */ diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/types.h b/cpukit/score/cpu/epiphany/include/rtems/score/types.h new file mode 100644 index 0000000000..24c8955fd3 --- /dev/null +++ b/cpukit/score/cpu/epiphany/include/rtems/score/types.h @@ -0,0 +1,67 @@ +/** + * @file + * + * @brief Epiphany Architecture Types API + */ + +/* + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + #ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void epiphany_isr; +typedef void ( *epiphany_isr_entry )( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/epiphany/preinstall.am b/cpukit/score/cpu/epiphany/preinstall.am deleted file mode 100644 index e12a51695e..0000000000 --- a/cpukit/score/cpu/epiphany/preinstall.am +++ /dev/null @@ -1,57 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/epiphany.h: rtems/score/epiphany.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/epiphany.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/epiphany.h - -$(PROJECT_INCLUDE)/rtems/score/epiphany-utility.h: rtems/score/epiphany-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/epiphany-utility.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/epiphany-utility.h - diff --git a/cpukit/score/cpu/epiphany/rtems/asm.h b/cpukit/score/cpu/epiphany/rtems/asm.h deleted file mode 100644 index 87e0cca1cb..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef __EPIPHANY_ASM_H -#define __EPIPHANY_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .extern SYM (sym) -#define TYPE_FUNC(sym) .type SYM (sym), %function - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h b/cpukit/score/cpu/epiphany/rtems/score/cpu.h deleted file mode 100644 index 34ac8ae6c6..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h +++ /dev/null @@ -1,873 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _EPIPHANY_CPU_H -#define _EPIPHANY_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include /* pick up machine definitions */ -#include -#ifndef ASM -#include -#include -#include /* for printk */ -#endif - -/* conditional compilation parameters */ - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Currently, for epiphany port, _ISR_Handler is responsible for switching to - * RTEMS dedicated interrupt task. - * - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "epiphany_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * epiphany Specific Information: - * - * At this time there are no implementations of Epiphany that are - * expected to implement floating point. - */ - -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - */ - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 64 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * epiphany Specific Information: - * - * This version of RTEMS is designed specifically to run with - * big endian architectures. If you want little endian, you'll - * have to make the appropriate adjustments here and write - * efficient routines for byte swapping. The epiphany architecture - * doesn't do this very well. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * - */ -#ifndef ASM - -typedef struct { - uint32_t r[64]; - - uint32_t status; - uint32_t config; - uint32_t iret; - -#ifdef RTEMS_SMP - /** - * @brief On SMP configurations the thread context must contain a boolean - * indicator to signal if this context is executing on a processor. - * - * This field must be updated during a context switch. The context switch - * to the heir must wait until the heir context indicates that it is no - * longer executing on a processor. The context switch must also check if - * a thread dispatch is necessary to honor updates of the heir thread for - * this processor. This indicator must be updated using an atomic test and - * set operation to ensure that at most one processor uses the heir - * context at the same time. - * - * @code - * void _CPU_Context_switch( - * Context_Control *executing, - * Context_Control *heir - * ) - * { - * save( executing ); - * - * executing->is_executing = false; - * memory_barrier(); - * - * if ( test_and_set( &heir->is_executing ) ) { - * do { - * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); - * - * if ( cpu_self->dispatch_necessary ) { - * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); - * } - * } while ( test_and_set( &heir->is_executing ) ); - * } - * - * restore( heir ); - * } - * @endcode - */ - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r[13] - -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * epiphany Specific Information: - * - */ - -#define CPU_CONTEXT_FP_SIZE 0 - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - */ - -#define CPU_ALIGNMENT 8 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - */ - -#define CPU_STACK_ALIGNMENT 8 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline uint32_t epiphany_interrupt_disable( void ) -{ - uint32_t sr; - __asm__ __volatile__ ("movfs %[sr], status \n" : [sr] "=r" (sr):); - __asm__ __volatile__("gid \n"); - return sr; -} - -static inline void epiphany_interrupt_enable(uint32_t level) -{ - __asm__ __volatile__("gie \n"); - __asm__ __volatile__ ("movts status, %[level] \n" :: [level] "r" (level):); -} - -#define _CPU_ISR_Disable( _level ) \ - _level = epiphany_interrupt_disable() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - */ - -#define _CPU_ISR_Enable( _level ) \ - epiphany_interrupt_enable( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - */ - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - if ( (_level & 0x2) != 0 ) \ - _CPU_ISR_Enable( _level ); \ - epiphany_interrupt_disable(); \ - } while(0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & 0x2 ) != 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - */ - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - */ - -/** - * @brief Account for GCC red-zone - * - * The following macro is used when initializing task's stack - * to account for GCC red-zone. - */ - -#define EPIPHANY_GCC_RED_ZONE_SIZE 128 - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - */ - -#include - -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%" PRIu32 " Halted\n",_source, _error); \ - asm("trap 3" :: "r" (_error)); \ - for(;;) - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#endif /* ASM */ - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 -#define CPU_EXCEPTION_FRAME_SIZE 260 - -#define CPU_MAXIMUM_PROCESSORS 32 - -#ifndef ASM - -typedef struct { - uint32_t r[62]; - uint32_t status; - uint32_t config; - uint32_t iret; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * epiphany Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h b/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h deleted file mode 100644 index cc091fa909..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief Epiphany Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpuatomic.h b/cpukit/score/cpu/epiphany/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h b/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/epiphany-utility.h b/cpukit/score/cpu/epiphany/rtems/score/epiphany-utility.h deleted file mode 100644 index bf223f93bf..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/epiphany-utility.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * @file - * - * @ingroup ScoreCPU - * - * @brief This include file contains macros pertaining to the - * Epiphany processor family. - */ - -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _EPIPHANY_UTILITY_H -#define _EPIPHANY_UTILITY_H - -/* eCore IRQs */ -typedef enum -{ - START, - SW_EXCEPTION, - MEM_FAULT, - TIMER0, - TIMER1, - SMP_MESSAGE, - DMA0, - DMA1, - SER, -} EPIPHANY_IRQ_PER_CORE_T; - -/* Per-core IO mapped register addresses - * @see Epiphany architecture reference. - */ -#define EPIPHANY_PER_CORE_REG_CONFIG 0xF0400 -#define EPIPHANY_PER_CORE_REG_STATUS 0xF0404 -#define EPIPHANY_PER_CORE_REG_PC 0xF0408 -#define EPIPHANY_PER_CORE_REG_DEBUGSTATUS 0xF040C -#define EPIPHANY_PER_CORE_REG_LC 0xF0414 -#define EPIPHANY_PER_CORE_REG_LS 0xF0418 -#define EPIPHANY_PER_CORE_REG_LE 0xF041C -#define EPIPHANY_PER_CORE_REG_IRET 0xF0420 -#define EPIPHANY_PER_CORE_REG_IMASK 0xF0424 -#define EPIPHANY_PER_CORE_REG_ILAT 0xF0428 -#define EPIPHANY_PER_CORE_REG_ILATST 0xF042C -#define EPIPHANY_PER_CORE_REG_ILATCL 0xF0430 -#define EPIPHANY_PER_CORE_REG_IPEND 0xF0434 -#define EPIPHANY_PER_CORE_REG_FSTATUS 0xF0440 -#define EPIPHANY_PER_CORE_REG_DEBUGCMD 0xF0448 -#define EPIPHANY_PER_CORE_REG_RESETCORE 0xF070C - -/* Event timer registers */ -#define EPIPHANY_PER_CORE_REG_CTIMER0 0xF0438 -#define EPIPHANY_PER_CORE_REG_CTIMER1 0xF043C - -/* Processor control registers */ -#define EPIPHANY_PER_CORE_REG_MEMSTATUS 0xF0604 -#define EPIPHANY_PER_CORE_REG_MEMPROTECT 0xF0608 - -/* DMA Registers */ -#define EPIPHANY_PER_CORE_REG_DMA0CONFIG 0xF0500 -#define EPIPHANY_PER_CORE_REG_DMA0STRIDE 0xF0504 -#define EPIPHANY_PER_CORE_REG_DMA0COUNT 0xF0508 -#define EPIPHANY_PER_CORE_REG_DMA0SRCADDR 0xF050C -#define EPIPHANY_PER_CORE_REG_DMA0DSTADDR 0xF0510 -#define EPIPHANY_PER_CORE_REG_DMA0AUTO0 0xF0514 -#define EPIPHANY_PER_CORE_REG_DMA0AUTO1 0xF0518 -#define EPIPHANY_PER_CORE_REG_DMA0STATUS 0xF051C -#define EPIPHANY_PER_CORE_REG_DMA1CONFIG 0xF0520 -#define EPIPHANY_PER_CORE_REG_DMA1STRIDE 0xF0524 -#define EPIPHANY_PER_CORE_REG_DMA1COUNT 0xF0528 -#define EPIPHANY_PER_CORE_REG_DMA1SRCADDR 0xF052C -#define EPIPHANY_PER_CORE_REG_DMA1DSTADDR 0xF0530 -#define EPIPHANY_PER_CORE_REG_DMA1AUTO0 0xF0534 -#define EPIPHANY_PER_CORE_REG_DMA1AUTO1 0xF0538 -#define EPIPHANY_PER_CORE_REG_DMA1STATUS 0xF053C - -/* Mesh Node Control Registers */ -#define EPIPHANY_PER_CORE_REG_MESHCONFIG 0xF0700 -#define EPIPHANY_PER_CORE_REG_COREID 0xF0704 -#define EPIPHANY_PER_CORE_REG_MULTICAST 0xF0708 -#define EPIPHANY_PER_CORE_REG_CMESHROUTE 0xF0710 -#define EPIPHANY_PER_CORE_REG_XMESHROUTE 0xF0714 -#define EPIPHANY_PER_CORE_REG_RMESHROUTE 0xF0718 - -/* This macros constructs an address space of epiphany cores - * from their IDs. - */ -#define EPIPHANY_COREID_TO_MSB_ADDR(id) (id) << 20 - -/* Construct a complete/absolute IO mapped address register from - * core ID and register name - */ -#define EPIPHANY_GET_REG_ABSOLUTE_ADDR(coreid, reg) \ - (EPIPHANY_COREID_TO_MSB_ADDR(coreid) | (reg)) - -#define EPIPHANY_REG(reg) (uint32_t *) (reg) - -/* Read register with its absolute address */ -static inline uint32_t read_epiphany_reg(volatile uint32_t reg_addr) -{ - return *(EPIPHANY_REG(reg_addr)); -} - -/* Write register with its abolute address */ -static inline void write_epiphany_reg(volatile uint32_t reg_addr, uint32_t val) -{ - *(EPIPHANY_REG(reg_addr)) = val; -} - -/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses - * linear IDs. The following function converts RTEMS linear IDs to - * Epiphany corresponding ones - */ -static const uint32_t map[16] = -{ - 0x808, 0x809, 0x80A, 0x80B, - 0x848, 0x849, 0x84A, 0x84B, - 0x888, 0x889, 0x88A, 0x88B, - 0x8C8, 0x8C9, 0x8CA, 0x8CB -}; - -static inline uint32_t rtems_coreid_to_epiphany_map(uint32_t rtems_id) -{ - return map[rtems_id]; -} - -/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses - * linear IDs. The following function is used to map Epiphany IDs to - * RTEMS linear IDs. - */ -static inline uint32_t epiphany_coreid_to_rtems_map(uint32_t epiphany_id) -{ - register uint32_t coreid asm ("r17") = epiphany_id; - - /* Mapping from Epiphany IDs to 0-16 IDs macro */ - __asm__ __volatile__(" \ - movfs r17, coreid \ - mov r19, #0x003 \ - mov r20, #0x0F0 \ - and r19, r17, r19 \ - and r20, r17, r20 \ - lsr r20, r20, #4 \ - add r17, r19, r20 \ - "); - - /* coreid or r17 now holds the rtems core id */ - return coreid; -} - -static inline uint32_t _Epiphany_Get_current_processor() -{ - uint32_t coreid; - - asm volatile ("movfs %0, coreid" : "=r" (coreid): ); - - return epiphany_coreid_to_rtems_map(coreid); -} -#endif /* _EPIPHANY_UTILITY_H */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/epiphany.h b/cpukit/score/cpu/epiphany/rtems/score/epiphany.h deleted file mode 100644 index 60d975581f..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/epiphany.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * @file rtems/score/epiphany.h - */ - -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_EPIPHANY_H -#define _RTEMS_SCORE_EPIPHANY_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the Epiphany family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - - /* - * Define the name of the CPU family and specific model. - */ - -#define CPU_NAME "EPIPHANY" -#define CPU_MODEL_NAME "EPIPHANY" - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_EPIPHANY_H */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/types.h b/cpukit/score/cpu/epiphany/rtems/score/types.h deleted file mode 100644 index 24c8955fd3..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/types.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - * @file - * - * @brief Epiphany Architecture Types API - */ - -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - #ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void epiphany_isr; -typedef void ( *epiphany_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/h8300/headers.am b/cpukit/score/cpu/h8300/headers.am new file mode 100644 index 0000000000..6f4357916f --- /dev/null +++ b/cpukit/score/cpu/h8300/headers.am @@ -0,0 +1,5 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h diff --git a/cpukit/score/cpu/h8300/include/machine/elf_machdep.h b/cpukit/score/cpu/h8300/include/machine/elf_machdep.h new file mode 100644 index 0000000000..3d049157eb --- /dev/null +++ b/cpukit/score/cpu/h8300/include/machine/elf_machdep.h @@ -0,0 +1,59 @@ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB + +#define ELF32_MACHDEP_ID_CASES \ + case EM_H8_300: \ + case EM_H8_300H: \ + case EM_H8S: \ + case EM_H8_500: \ + break; + +#define ELF32_MACHDEP_ID EM_H8_300 +#define ARCH_ELFSIZE 32 + +#define R_H8_NONE 0 +#define R_H8_DIR32 1 +#define R_H8_DIR32_28 2 +#define R_H8_DIR32_24 3 +#define R_H8_DIR32_16 4 +#define R_H8_DIR32U 6 +#define R_H8_DIR32U_28 7 +#define R_H8_DIR32U_24 8 +#define R_H8_DIR32U_20 9 +#define R_H8_DIR32U_16 10 +#define R_H8_DIR24 11 +#define R_H8_DIR24_20 12 +#define R_H8_DIR24_16 13 +#define R_H8_DIR24U 14 +#define R_H8_DIR24U_20 15 +#define R_H8_DIR24U_16 16 +#define R_H8_DIR16 17 +#define R_H8_DIR16U 18 +#define R_H8_DIR16S_32 19 +#define R_H8_DIR16S_28 20 +#define R_H8_DIR16S_24 21 +#define R_H8_DIR16S_20 22 +#define R_H8_DIR16S 23 +#define R_H8_DIR8 24 +#define R_H8_DIR8U 25 +#define R_H8_DIR8Z_32 26 +#define R_H8_DIR8Z_28 27 +#define R_H8_DIR8Z_24 28 +#define R_H8_DIR8Z_20 29 +#define R_H8_DIR8Z_16 30 +#define R_H8_PCREL16 31 +#define R_H8_PCREL8 32 +#define R_H8_BPOS 33 +#define R_H8_PCREL32 34 +#define R_H8_GOT32O 35 +#define R_H8_GOT16O 36 +#define R_H8_DIR16A8 59 +#define R_H8_DIR16R8 60 +#define R_H8_DIR24A8 61 +#define R_H8_DIR24R8 62 +#define R_H8_DIR32A16 63 +#define R_H8_ABS32 65 +#define R_H8_ABS32A16 127 + + +#define R_TYPE(name) __CONCAT(R_H8_,name) diff --git a/cpukit/score/cpu/i386/Makefile.am b/cpukit/score/cpu/i386/Makefile.am index 7fb2a081b6..fe7fa5582c 100644 --- a/cpukit/score/cpu/i386/Makefile.am +++ b/cpukit/score/cpu/i386/Makefile.am @@ -1,22 +1,9 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS= rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/i386.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/interrupts.h -include_rtems_score_HEADERS += rtems/score/registers.h -include_rtems_score_HEADERS += rtems/score/idtr.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c cpu_asm.S libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/i386/headers.am b/cpukit/score/cpu/i386/headers.am new file mode 100644 index 0000000000..ea07edcbd4 --- /dev/null +++ b/cpukit/score/cpu/i386/headers.am @@ -0,0 +1,20 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/i386.h +include_rtems_score_HEADERS += include/rtems/score/idtr.h +include_rtems_score_HEADERS += include/rtems/score/interrupts.h +include_rtems_score_HEADERS += include/rtems/score/registers.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/i386/include/machine/elf_machdep.h b/cpukit/score/cpu/i386/include/machine/elf_machdep.h new file mode 100644 index 0000000000..442c561a9c --- /dev/null +++ b/cpukit/score/cpu/i386/include/machine/elf_machdep.h @@ -0,0 +1,63 @@ +/* $NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $ */ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#define ELF32_MACHDEP_ID_CASES \ + case EM_386: \ + case EM_486: \ + break; + +#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ +#define ELF64_MACHDEP_ID_CASES \ + /* no 64-bit ELF machine types supported */ + +#define ELF32_MACHDEP_ID EM_386 + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +/* i386 relocations */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 + +/* TLS relocations */ +#define R_386_TLS_TPOFF 14 +#define R_386_TLS_IE 15 +#define R_386_TLS_GOTIE 16 +#define R_386_TLS_LE 17 +#define R_386_TLS_GD 18 +#define R_386_TLS_LDM 19 + +/* The following relocations are GNU extensions. */ +#define R_386_16 20 +#define R_386_PC16 21 +#define R_386_8 22 +#define R_386_PC8 23 + +/* More TLS relocations */ +#define R_386_TLS_GD_32 24 +#define R_386_TLS_GD_PUSH 25 +#define R_386_TLS_GD_CALL 26 +#define R_386_TLS_GD_POP 27 +#define R_386_TLS_LDM_32 28 +#define R_386_TLS_LDM_PUSH 29 +#define R_386_TLS_LDM_CALL 30 +#define R_386_TLS_LDM_POP 31 +#define R_386_TLS_LDO_32 32 +#define R_386_TLS_IE_32 33 +#define R_386_TLS_LE_32 34 +#define R_386_TLS_DTPMOD32 35 +#define R_386_TLS_DTPOFF32 36 +#define R_386_TLS_TPOFF32 37 +#define R_386_TLS_GOTDESC 39 +#define R_386_TLS_DESC_CALL 40 +#define R_386_TLS_DESC 41 + +#define R_TYPE(name) __CONCAT(R_386_,name) diff --git a/cpukit/score/cpu/i386/include/rtems/asm.h b/cpukit/score/cpu/i386/include/rtems/asm.h new file mode 100644 index 0000000000..50b0fd71a0 --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/asm.h @@ -0,0 +1,140 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +/* + * Looks like there is a bug in gcc 2.6.2 where this is not + * defined correctly when configured as i386-coff and + * i386-aout. + */ + +#undef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ % + +/* +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif +*/ + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) + +#define eax REG (eax) +#define ebx REG (ebx) +#define ecx REG (ecx) +#define edx REG (edx) +#define esi REG (esi) +#define edi REG (edi) +#define esp REG (esp) +#define ebp REG (ebp) +#define cr0 REG (cr0) +#define cr4 REG (cr4) + +#define ax REG (ax) +#define bx REG (bx) +#define cx REG (cx) +#define dx REG (dx) +#define si REG (si) +#define di REG (di) +#define sp REG (sp) +#define bp REG (bp) + +#define ah REG (ah) +#define bh REG (bh) +#define ch REG (ch) +#define dh REG (dh) + +#define al REG (al) +#define bl REG (bl) +#define cl REG (cl) +#define dl REG (dl) + +#define cs REG (cs) +#define ds REG (ds) +#define es REG (es) +#define fs REG (fs) +#define gs REG (gs) +#define ss REG (ss) + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA .data +#define END_DATA +#define BEGIN_BSS .bss +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h b/cpukit/score/cpu/i386/include/rtems/score/cpu.h new file mode 100644 index 0000000000..f78149c24b --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h @@ -0,0 +1,700 @@ +/** + * @file + * + * @brief Intel I386 CPU Dependent Source + * + * This include file contains information pertaining to the Intel + * i386 processor. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifndef ASM +#include /* for memcpy */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * PowerPC Specific Information: + * + * The PowerPC and x86 were the first to use the PIC interrupt model. + * They do not use the simple vectored interrupt model. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE + +/* + * i386 has an RTEMS allocated and managed interrupt stack. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/* + * Some family members have no FP, some have an FPU such as the i387 + * for the i386, others have it built in (i486DX, Pentium). + */ + +#ifdef __SSE__ +#define CPU_HARDWARE_FP TRUE +#define CPU_SOFTWARE_FP FALSE + +#define CPU_ALL_TASKS_ARE_FP TRUE +#define CPU_IDLE_TASK_IS_FP TRUE +#define CPU_USE_DEFERRED_FP_SWITCH FALSE +#else /* __SSE__ */ + +#if ( I386_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE /* i387 for i386 */ +#else +#define CPU_HARDWARE_FP FALSE +#endif +#define CPU_SOFTWARE_FP FALSE + +#define CPU_ALL_TASKS_ARE_FP FALSE +#define CPU_IDLE_TASK_IS_FP FALSE +#if defined(RTEMS_SMP) + #define CPU_USE_DEFERRED_FP_SWITCH FALSE +#else + #define CPU_USE_DEFERRED_FP_SWITCH TRUE +#endif +#endif /* __SSE__ */ + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */ +#define CPU_CACHE_LINE_BYTES 64 + +#define CPU_STRUCTURE_ALIGNMENT + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +#define CPU_MAXIMUM_PROCESSORS 32 + +#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 +#define I386_CONTEXT_CONTROL_ESP_OFFSET 4 +#define I386_CONTEXT_CONTROL_EBP_OFFSET 8 +#define I386_CONTEXT_CONTROL_EBX_OFFSET 12 +#define I386_CONTEXT_CONTROL_ESI_OFFSET 16 +#define I386_CONTEXT_CONTROL_EDI_OFFSET 20 +#define I386_CONTEXT_CONTROL_GS_0_OFFSET 24 +#define I386_CONTEXT_CONTROL_GS_1_OFFSET 28 + +#ifdef RTEMS_SMP + #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32 +#endif + +/* structures */ + +#ifndef ASM + +/* + * Basic integer context for the i386 family. + */ + +typedef struct { + uint32_t eflags; /* extended flags register */ + void *esp; /* extended stack pointer register */ + void *ebp; /* extended base pointer register */ + uint32_t ebx; /* extended bx register */ + uint32_t esi; /* extended source index register */ + uint32_t edi; /* extended destination index flags register */ + segment_descriptors gs; /* gs segment descriptor */ +#ifdef RTEMS_SMP + volatile bool is_executing; +#endif +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->esp + +#ifdef RTEMS_SMP + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + { + return context->is_executing; + } + + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + context->is_executing = is_executing; + } +#endif + +/* + * FP context save area for the i387 numeric coprocessors. + */ +#ifdef __SSE__ +/* All FPU and SSE registers are volatile; hence, as long + * as we are within normally executing C code (including + * a task switch) there is no need for saving/restoring + * any of those registers. + * We must save/restore the full FPU/SSE context across + * interrupts and exceptions, however: + * - after ISR execution a _Thread_Dispatch() may happen + * and it is therefore necessary to save the FPU/SSE + * registers to be restored when control is returned + * to the interrupted task. + * - gcc may implicitly use FPU/SSE instructions in + * an ISR. + * + * Even though there is no explicit mentioning of the FPU + * control word in the SYSV ABI (i386) being non-volatile + * we maintain MXCSR and the FPU control-word for each task. + */ +typedef struct { + uint32_t mxcsr; + uint16_t fpucw; +} Context_Control_fp; + +#else + +typedef struct { + uint8_t fp_save_area[108]; /* context size area for I80387 */ + /* 28 bytes for environment */ +} Context_Control_fp; + +#endif + + +/* + * The following structure defines the set of information saved + * on the current stack by RTEMS upon receipt of execptions. + * + * idtIndex is either the interrupt number or the trap/exception number. + * faultCode is the code pushed by the processor on some exceptions. + * + * Since the first registers are directly pushed by the CPU they + * may not respect 16-byte stack alignment, which is, however, + * mandatory for the SSE register area. + * Therefore, these registers are stored at an aligned address + * and a pointer is stored in the CPU_Exception_frame. + * If the executive was compiled without SSE support then + * this pointer is NULL. + */ + +struct Context_Control_sse; + +typedef struct { + struct Context_Control_sse *fp_ctxt; + uint32_t edi; + uint32_t esi; + uint32_t ebp; + uint32_t esp0; + uint32_t ebx; + uint32_t edx; + uint32_t ecx; + uint32_t eax; + uint32_t idtIndex; + uint32_t faultCode; + uint32_t eip; + uint32_t cs; + uint32_t eflags; +} CPU_Exception_frame; + +#ifdef __SSE__ +typedef struct Context_Control_sse { + uint16_t fcw; + uint16_t fsw; + uint8_t ftw; + uint8_t res_1; + uint16_t fop; + uint32_t fpu_ip; + uint16_t cs; + uint16_t res_2; + uint32_t fpu_dp; + uint16_t ds; + uint16_t res_3; + uint32_t mxcsr; + uint32_t mxcsr_mask; + struct { + uint8_t fpreg[10]; + uint8_t res_4[ 6]; + } fp_mmregs[8]; + uint8_t xmmregs[8][16]; + uint8_t res_5[224]; +} Context_Control_sse +__attribute__((aligned(16))) +; +#endif + +typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); +extern cpuExcHandlerType _currentExcHandler; +extern void rtems_exception_init_mngt(void); + +/* + * This port does not pass any frame info to the + * interrupt handler. + */ + +typedef void CPU_Interrupt_frame; + +typedef enum { + I386_EXCEPTION_DIVIDE_BY_ZERO = 0, + I386_EXCEPTION_DEBUG = 1, + I386_EXCEPTION_NMI = 2, + I386_EXCEPTION_BREAKPOINT = 3, + I386_EXCEPTION_OVERFLOW = 4, + I386_EXCEPTION_BOUND = 5, + I386_EXCEPTION_ILLEGAL_INSTR = 6, + I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, + I386_EXCEPTION_DOUBLE_FAULT = 8, + I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, + I386_EXCEPTION_INVALID_TSS = 10, + I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, + I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, + I386_EXCEPTION_GENERAL_PROT_ERR = 13, + I386_EXCEPTION_PAGE_FAULT = 14, + I386_EXCEPTION_INTEL_RES15 = 15, + I386_EXCEPTION_FLOAT_ERROR = 16, + I386_EXCEPTION_ALIGN_CHECK = 17, + I386_EXCEPTION_MACHINE_CHECK = 18, + I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ + +} Intel_symbolic_exception_name; + + +/* + * context size area for floating point + * + * NOTE: This is out of place on the i386 to avoid a forward reference. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* variables */ + +extern Context_Control_fp _CPU_Null_fp_context; + +#endif /* ASM */ + +/* constants */ + +/* + * This defines the number of levels and the mask used to pick those + * bits out of a thread mode. + */ + +#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ + +/* + * extra stack required by the MPCI receive server thread + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * Minimum size of a thread's stack. + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +#define CPU_SIZEOF_POINTER 4 + +/* + * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. + */ + +#define CPU_ALIGNMENT 4 +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * On i386 thread stacks require no further alignment after allocation + * from the Workspace. However, since gcc maintains 16-byte alignment + * we try to respect that. If you find an option to let gcc squeeze + * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still + * doesn't waste much space since this only determines the *initial* + * alignment. + */ + +#define CPU_STACK_ALIGNMENT 16 + +/* macros */ + +#ifndef ASM +/* + * ISR handler macros + * + * These macros perform the following functions: + * + initialize the RTEMS vector table + * + disable all maskable CPU interrupts + * + restore previous interrupt level (enable) + * + temporarily restore interrupts (flash) + * + set a particular level + */ + +#if !defined(RTEMS_PARAVIRT) +#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) + +#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) + +#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) + +#define _CPU_ISR_Set_level( _new_level ) \ + { \ + if ( _new_level ) __asm__ volatile ( "cli" ); \ + else __asm__ volatile ( "sti" ); \ + } +#else +#define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts() +#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) +#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) +#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) +#endif + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & EFLAGS_INTR_ENABLE ) != 0; +} + +uint32_t _CPU_ISR_Get_level( void ); + +/* Make sure interrupt stack has space for ISR + * 'vector' arg at the top and that it is aligned + * properly. + */ + +#define _CPU_Interrupt_stack_setup( _lo, _hi ) \ + do { \ + _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ + } while (0) + +#endif /* ASM */ + +/* end of ISR handler macros */ + +/* + * Context handler macros + * + * These macros perform the following functions: + * + initialize a context area + * + restart the current thread + * + calculate the initial pointer into a FP context area + * + initialize an FP context area + */ + +#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 +#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 + +#ifndef ASM + +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#if defined(RTEMS_SMP) + uint32_t _CPU_SMP_Initialize( void ); + + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + /* Nothing to do */ + #define _CPU_SMP_Prepare_start_multitasking() do { } while ( 0 ) + + uint32_t _CPU_SMP_Get_current_processor( void ); + + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + static inline void _CPU_SMP_Processor_event_receive( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } +#endif + +#define _CPU_Context_Initialize_fp( _fp_area ) \ + { \ + memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ + } + +/* end of Context handler macros */ + +/* + * Fatal Error manager macros + * + * These macros perform the following functions: + * + disable interrupts and halt the CPU + */ + +extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) + RTEMS_NO_RETURN; + +#endif /* ASM */ + +/* end of Fatal Error manager macros */ + +/* + * Bitfield handler macros + * + * These macros perform the following functions: + * + scan for the highest numbered (MSB) set in a 16 bit bitfield + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE FALSE + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + register uint16_t __value_in_register = ( _value ); \ + uint16_t __output = 0; \ + __asm__ volatile ( "bsfw %0,%1 " \ + : "=r" ( __value_in_register ), "=r" ( __output ) \ + : "0" ( __value_in_register ), "1" ( __output ) \ + ); \ + ( _output ) = __output; \ + } + +/* end of Bitfield handler macros */ + +/* + * Priority handler macros + * + * These macros perform the following functions: + * + return a mask with the bit for this major/minor portion of + * of thread priority set. + * + translate the bit number returned by "Bitfield_find_first_bit" + * into an index into the thread ready chain bit maps + */ + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +/* functions */ + +#ifndef ASM +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Thread_Idle_body + * + * Use the halt instruction of low power mode of a particular i386 model. + */ + +#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner and avoid stack conflicts. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +#ifdef __SSE__ +#define _CPU_Context_save_fp(fp_context_pp) \ + do { \ + __asm__ __volatile__( \ + "fstcw %0" \ + :"=m"((*(fp_context_pp))->fpucw) \ + ); \ + __asm__ __volatile__( \ + "stmxcsr %0" \ + :"=m"((*(fp_context_pp))->mxcsr) \ + ); \ + } while (0) +#else +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); +#endif + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ +#ifdef __SSE__ +#define _CPU_Context_restore_fp(fp_context_pp) \ + do { \ + __asm__ __volatile__( \ + "fldcw %0" \ + ::"m"((*(fp_context_pp))->fpucw) \ + :"fpcr" \ + ); \ + __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ + } while (0) +#else +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); +#endif + +#ifdef __SSE__ +#define _CPU_Context_Initialization_at_thread_begin() \ + do { \ + __asm__ __volatile__( \ + "finit" \ + : \ + : \ + :"st","st(1)","st(2)","st(3)", \ + "st(4)","st(5)","st(6)","st(7)", \ + "fpsr","fpcr" \ + ); \ + if ( _Thread_Executing->fp_context ) { \ + _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ + } \ + } while (0) +#endif + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/i386/include/rtems/score/i386.h b/cpukit/score/cpu/i386/include/rtems/score/i386.h new file mode 100644 index 0000000000..2555d13b8b --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/i386.h @@ -0,0 +1,670 @@ +/** + * @file + * + * @brief Intel I386 CPU Dependent Source + * + * This include file contains information pertaining to the Intel + * i386 processor. + */ + +/* + * COPYRIGHT (c) 1989-2016. + * On-Line Applications Research Corporation (OAR). + * + * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_I386_H +#define _RTEMS_SCORE_I386_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* + * This section contains the information required to build + * RTEMS for a particular member of the Intel i386 + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + * + * Currently recognized: + * i386_fp (i386 DX or SX w/i387) + * i486dx + * pentium + * pentiumpro + * + * CPU Model Feature Flags: + * + * I386_HAS_BSWAP: Defined to "1" if the instruction for endian swapping + * (bswap) should be used. This instruction appears to + * be present in all i486's and above. + * + * I386_HAS_FPU: Defined to "1" if the CPU has an FPU. + * As of at least gcc 4.7, i386 soft-float was obsoleted. + * Thus this is always set to "1". + */ +#define I386_HAS_FPU 1 + +#if defined(__pentiumpro__) + + #define CPU_MODEL_NAME "Pentium Pro" + +#elif defined(__i586__) + + #if defined(__pentium__) + #define CPU_MODEL_NAME "Pentium" + #elif defined(__k6__) + #define CPU_MODEL_NAME "K6" + #else + #define CPU_MODEL_NAME "i586" + #endif + +#elif defined(__i486__) + + #define CPU_MODEL_NAME "i486dx" + +#elif defined(__i386__) + + #define I386_HAS_BSWAP 0 + #define CPU_MODEL_NAME "i386 with i387" + +#else + #error "Unknown CPU Model" +#endif + +/* + * Set default values for CPU model feature flags + * + * NOTE: These settings are chosen to reflect most of the family members. + */ +#ifndef I386_HAS_BSWAP +#define I386_HAS_BSWAP 1 +#endif + +/* + * Define the name of the CPU family. + */ +#define CPU_NAME "Intel i386" + +#ifndef ASM + +/* + * The following routine swaps the endian format of an unsigned int. + * It must be static so it can be referenced indirectly. + */ + +static inline uint32_t i386_swap_u32( + uint32_t value +) +{ + uint32_t lout; + +#if (I386_HAS_BSWAP == 0) + __asm__ volatile( "rorw $8,%%ax;" + "rorl $16,%0;" + "rorw $8,%%ax" : "=a" (lout) : "0" (value) ); +#else + __asm__ volatile( "bswap %0" : "=r" (lout) : "0" (value)); +#endif + return( lout ); +} +#define CPU_swap_u32( _value ) i386_swap_u32( _value ) + +static inline uint16_t i386_swap_u16( + uint16_t value +) +{ + unsigned short sout; + + __asm__ volatile( "rorw $8,%0" : "=r" (sout) : "0" (value)); + return (sout); +} +#define CPU_swap_u16( _value ) i386_swap_u16( _value ) + +/* + * Added for pagination management + */ +static inline unsigned int i386_get_cr0(void) +{ + register unsigned int segment = 0; + + __asm__ volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static inline void i386_set_cr0(unsigned int segment) +{ + __asm__ volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) ); +} + +static inline unsigned int i386_get_cr2(void) +{ + register unsigned int segment = 0; + + __asm__ volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static inline unsigned int i386_get_cr3(void) +{ + register unsigned int segment = 0; + + __asm__ volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static inline void i386_set_cr3(unsigned int segment) +{ + __asm__ volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); +} + +/* routines */ + +/* + * i386_Logical_to_physical + * + * Converts logical address to physical address. + */ +void *i386_Logical_to_physical( + unsigned short segment, + void *address +); + +/* + * i386_Physical_to_logical + * + * Converts physical address to logical address. + */ +void *i386_Physical_to_logical( + unsigned short segment, + void *address +); + +/** + * @brief Converts real mode pointer {segment, offset} to physical address. + * + * i386_Real_to_physical + * + * @param[in] segment used with \p offset to compute physical address + * @param[in] offset used with \p segment to compute physical address + * @retval physical address + */ +RTEMS_INLINE_ROUTINE void *i386_Real_to_physical( + uint16_t segment, + uint16_t offset) +{ + return (void *)(((uint32_t)segment<<4)+offset); +} + +/** + * @brief Retrieves real mode pointer elements {segmnet, offset} from + * physical address. + * + * i386_Physical_to_real + * Function returns the highest segment (base) address possible. + * Example: input address - 0x4B3A2 + * output segment - 0x4B3A + * offset - 0x2 + * input address - 0x10F12E + * output segment - 0xFFFF + * offset - 0xF13E + * + * @param[in] address address to be converted, must be less than 0x10FFEF + * @param[out] segment segment computed from \p address + * @param[out] offset offset computed from \p address + * @retval 0 address not convertible + * @retval 1 segment and offset extracted + */ +int i386_Physical_to_real( + void *address, + uint16_t *segment, + uint16_t *offset +); + +/* + * Segment Access Routines + * + * NOTE: Unfortunately, these are still static inlines even when the + * "macro" implementation of the generic code is used. + */ + +static __inline__ unsigned short i386_get_cs(void) +{ + register unsigned short segment = 0; + + __asm__ volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static __inline__ unsigned short i386_get_ds(void) +{ + register unsigned short segment = 0; + + __asm__ volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static __inline__ unsigned short i386_get_es(void) +{ + register unsigned short segment = 0; + + __asm__ volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static __inline__ unsigned short i386_get_ss(void) +{ + register unsigned short segment = 0; + + __asm__ volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static __inline__ unsigned short i386_get_fs(void) +{ + register unsigned short segment = 0; + + __asm__ volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static __inline__ unsigned short i386_get_gs(void) +{ + register unsigned short segment = 0; + + __asm__ volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +/* + * IO Port Access Routines + */ + +#define i386_outport_byte( _port, _value ) \ +do { register unsigned short __port = _port; \ + register unsigned char __value = _value; \ + \ + __asm__ volatile ( "outb %0,%1" : : "a" (__value), "d" (__port) ); \ + } while (0) + +#define i386_outport_word( _port, _value ) \ +do { register unsigned short __port = _port; \ + register unsigned short __value = _value; \ + \ + __asm__ volatile ( "outw %0,%1" : : "a" (__value), "d" (__port) ); \ + } while (0) + +#define i386_outport_long( _port, _value ) \ +do { register unsigned short __port = _port; \ + register unsigned int __value = _value; \ + \ + __asm__ volatile ( "outl %0,%1" : : "a" (__value), "d" (__port) ); \ + } while (0) + +#define i386_inport_byte( _port, _value ) \ +do { register unsigned short __port = _port; \ + register unsigned char __value = 0; \ + \ + __asm__ volatile ( "inb %1,%0" : "=a" (__value) \ + : "d" (__port) \ + ); \ + _value = __value; \ + } while (0) + +#define i386_inport_word( _port, _value ) \ +do { register unsigned short __port = _port; \ + register unsigned short __value = 0; \ + \ + __asm__ volatile ( "inw %1,%0" : "=a" (__value) \ + : "d" (__port) \ + ); \ + _value = __value; \ + } while (0) + +#define i386_inport_long( _port, _value ) \ +do { register unsigned short __port = _port; \ + register unsigned int __value = 0; \ + \ + __asm__ volatile ( "inl %1,%0" : "=a" (__value) \ + : "d" (__port) \ + ); \ + _value = __value; \ + } while (0) + +/* + * Type definition for raw interrupts. + */ + +typedef unsigned char rtems_vector_offset; + +typedef struct __rtems_raw_irq_connect_data__{ + /* + * IDT vector offset (IRQ line + PC386_IRQ_VECTOR_BASE) + */ + rtems_vector_offset idtIndex; + /* + * IDT raw handler. See comment on handler properties below in function prototype. + */ + rtems_raw_irq_hdl hdl; + /* + * function for enabling raw interrupts. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage interrupts and thus the + * "on" routine must enable the irq both at device and PIC level. + * + */ + rtems_raw_irq_enable on; + /* + * function for disabling raw interrupts. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage interrupts and thus the + * "on" routine must disable the irq both at device and PIC level. + * + */ + rtems_raw_irq_disable off; + /* + * function enabling to know what interrupt may currently occur + */ + rtems_raw_irq_is_enabled isOn; +}rtems_raw_irq_connect_data; + +typedef struct { + /* + * size of all the table fields (*Tbl) described below. + */ + unsigned int idtSize; + /* + * Default handler used when disconnecting interrupts. + */ + rtems_raw_irq_connect_data defaultRawEntry; + /* + * Table containing initials/current value. + */ + rtems_raw_irq_connect_data* rawIrqHdlTbl; +}rtems_raw_irq_global_settings; + +#include + +/* + * C callable function enabling to get handler currently connected to a vector + * + */ +rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset); + +/* + * C callable function enabling to set up one raw idt entry + */ +extern int i386_set_idt_entry (const rtems_raw_irq_connect_data*); + +/* + * C callable function enabling to get one current raw idt entry + */ +extern int i386_get_current_idt_entry (rtems_raw_irq_connect_data*); + +/* + * C callable function enabling to remove one current raw idt entry + */ +extern int i386_delete_idt_entry (const rtems_raw_irq_connect_data*); + +/* + * C callable function enabling to init idt. + * + * CAUTION : this function assumes that the IDTR register + * has been already set. + */ +extern int i386_init_idt (rtems_raw_irq_global_settings* config); + +/* + * C callable function enabling to get actual idt configuration + */ +extern int i386_get_idt_config (rtems_raw_irq_global_settings** config); + + +/* + * See page 11.12 Figure 11-8. + * + */ +/** + * @brief describes one entry of Global/Local Descriptor Table + */ +typedef struct { + unsigned int limit_15_0 : 16; + unsigned int base_address_15_0 : 16; + unsigned int base_address_23_16 : 8; + unsigned int type : 4; + unsigned int descriptor_type : 1; + unsigned int privilege : 2; + unsigned int present : 1; + unsigned int limit_19_16 : 4; + unsigned int available : 1; + unsigned int fixed_value_bits : 1; + unsigned int operation_size : 1; + unsigned int granularity : 1; + unsigned int base_address_31_24 : 8; +} RTEMS_PACKED segment_descriptors; + +/* + * C callable function enabling to get easilly usable info from + * the actual value of GDT register. + */ +extern void i386_get_info_from_GDTR (segment_descriptors** table, + uint16_t* limit); +/* + * C callable function enabling to change the value of GDT register. Must be called + * with interrupts masked at processor level!!!. + */ +extern void i386_set_GDTR (segment_descriptors*, + uint16_t limit); + +/** + * @brief Allows to set a GDT entry. + * + * Puts global descriptor \p sd to the global descriptor table on index + * \p segment_selector_index + * + * @param[in] segment_selector_index index to GDT entry + * @param[in] sd structure to be coppied to given \p segment_selector in GDT + * @retval 0 FAILED out of GDT range or index is 0, which is not valid + * index in GDT + * @retval 1 SUCCESS + */ +extern uint32_t i386_raw_gdt_entry (uint16_t segment_selector_index, + segment_descriptors* sd); + +/** + * @brief fills \p sd with provided \p base in appropriate fields of \p sd + * + * @param[in] base 32-bit address to be set as descriptor's base + * @param[out] sd descriptor being filled with \p base + */ +extern void i386_fill_segment_desc_base (uint32_t base, + segment_descriptors* sd); + +/** + * @brief fills \p sd with provided \p limit in appropriate fields of \p sd + * + * sets granularity bit if necessary + * + * @param[in] limit 32-bit value representing number of limit bytes + * @param[out] sd descriptor being filled with \p limit + */ +extern void i386_fill_segment_desc_limit (uint32_t limit, + segment_descriptors* sd); + +/* + * C callable function enabling to set up one raw interrupt handler + */ +extern uint32_t i386_set_gdt_entry (uint16_t segment_selector, + uint32_t base, + uint32_t limit); + +/** + * @brief Returns next empty descriptor in GDT. + * + * Number of descriptors that can be returned depends on \a GDT_SIZE + * + * @retval 0 FAILED GDT is full + * @retval <1;65535> segment_selector number as index to GDT + */ +extern uint16_t i386_next_empty_gdt_entry (void); + +/** + * @brief Copies GDT entry at index \p segment_selector to structure + * pointed to by \p struct_to_fill + * + * @param[in] segment_selector index to GDT table specifying descriptor to copy + * @param[out] struct_to_fill pointer to memory where will be descriptor coppied + * @retval 0 FAILED segment_selector out of GDT range + * @retval <1;65535> retrieved segment_selector + */ +extern uint16_t i386_cpy_gdt_entry (uint16_t segment_selector, + segment_descriptors* struct_to_fill); + +/** + * @brief Returns pointer to GDT table at index given by \p segment_selector + * + * @param[in] sgmnt_selector index to GDT table for specifying descriptor to get + * @retval NULL FAILED segment_selector out of GDT range + * @retval pointer to GDT table at \p segment_selector + */ +extern segment_descriptors* i386_get_gdt_entry (uint16_t sgmnt_selector); + +/** + * @brief Extracts base address from GDT entry pointed to by \p gdt_entry + * + * @param[in] gdt_entry pointer to entry from which base should be retrieved + * @retval base address from GDT entry +*/ +RTEMS_INLINE_ROUTINE void* i386_base_gdt_entry (segment_descriptors* gdt_entry) +{ + return (void*)(gdt_entry->base_address_15_0 | + (gdt_entry->base_address_23_16<<16) | + (gdt_entry->base_address_31_24<<24)); +} + +/** + * @brief Extracts limit in bytes from GDT entry pointed to by \p gdt_entry + * + * @param[in] gdt_entry pointer to entry from which limit should be retrieved + * @retval limit value in bytes from GDT entry + */ +extern uint32_t i386_limit_gdt_entry (segment_descriptors* gdt_entry); + +/* + * See page 11.18 Figure 11-12. + * + */ + +typedef struct { + unsigned int offset : 12; + unsigned int page : 10; + unsigned int directory : 10; +}la_bits; + +typedef union { + la_bits bits; + unsigned int address; +}linear_address; + + +/* + * See page 11.20 Figure 11-14. + * + */ + +typedef struct { + unsigned int present : 1; + unsigned int writable : 1; + unsigned int user : 1; + unsigned int write_through : 1; + unsigned int cache_disable : 1; + unsigned int accessed : 1; + unsigned int reserved1 : 1; + unsigned int page_size : 1; + unsigned int reserved2 : 1; + unsigned int available : 3; + unsigned int page_frame_address : 20; +}page_dir_bits; + +typedef union { + page_dir_bits bits; + unsigned int dir_entry; +}page_dir_entry; + +typedef struct { + unsigned int present : 1; + unsigned int writable : 1; + unsigned int user : 1; + unsigned int write_through : 1; + unsigned int cache_disable : 1; + unsigned int accessed : 1; + unsigned int dirty : 1; + unsigned int reserved2 : 2; + unsigned int available : 3; + unsigned int page_frame_address : 20; +}page_table_bits; + +typedef union { + page_table_bits bits; + unsigned int table_entry; +} page_table_entry; + +/* + * definitions related to page table entry + */ +#define PG_SIZE 0x1000 +#define MASK_OFFSET 0xFFF +#define MAX_ENTRY (PG_SIZE/sizeof(page_dir_entry)) +#define FOUR_MB 0x400000 +#define MASK_FLAGS 0x1A + +#define PTE_PRESENT 0x01 +#define PTE_WRITABLE 0x02 +#define PTE_USER 0x04 +#define PTE_WRITE_THROUGH 0x08 +#define PTE_CACHE_DISABLE 0x10 + +typedef struct { + page_dir_entry pageDirEntry[MAX_ENTRY]; +} page_directory; + +typedef struct { + page_table_entry pageTableEntry[MAX_ENTRY]; +} page_table; + +/* Simpler names for the i80x86 I/O instructions */ +#define outport_byte( _port, _value ) i386_outport_byte( _port, _value ) +#define outport_word( _port, _value ) i386_outport_word( _port, _value ) +#define outport_long( _port, _value ) i386_outport_long( _port, _value ) +#define inport_byte( _port, _value ) i386_inport_byte( _port, _value ) +#define inport_word( _port, _value ) i386_inport_word( _port, _value ) +#define inport_long( _port, _value ) i386_inport_long( _port, _value ) + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/i386/include/rtems/score/idtr.h b/cpukit/score/cpu/i386/include/rtems/score/idtr.h new file mode 100644 index 0000000000..a79af40792 --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/idtr.h @@ -0,0 +1,66 @@ +/** + * @file + * + * @brief Intel I386 Data Structures + * + * This file contains definitions for data structure related + * to Intel system programming. More information can be found + * on Intel site and more precisely in the following book : + * + * Pentium Processor familly + * Developper's Manual + * + * Volume 3 : Architecture and Programming Manual + * + * Formerly contained in and extracted from libcpu/i386/cpu.h. + */ + +/* + * COPYRIGHT (C) 1998 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Applications must not include this file directly. + */ + +#ifndef _RTEMS_SCORE_IDTR_H +#define _RTEMS_SCORE_IDTR_H + +/* + * See page 14.9 Figure 14-2. + * + */ +typedef struct +{ + unsigned int low_offsets_bits:16; + unsigned int segment_selector:16; + unsigned int fixed_value_bits:8; + unsigned int gate_type:5; + unsigned int privilege:2; + unsigned int present:1; + unsigned int high_offsets_bits:16; +} interrupt_gate_descriptor; + +/* + * C callable function enabling to create a interrupt_gate_descriptor + */ +extern void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl); + +/* + * C callable function enabling to get easily usable info from + * the actual value of IDT register. + */ +extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table, + unsigned* limit); + +/* + * C callable function enabling to change the value of IDT register. Must be called + * with interrupts masked at processor level!!!. + */ +extern void i386_set_IDTR (interrupt_gate_descriptor* table, + unsigned limit); + +#endif diff --git a/cpukit/score/cpu/i386/include/rtems/score/interrupts.h b/cpukit/score/cpu/i386/include/rtems/score/interrupts.h new file mode 100644 index 0000000000..3a7971c1ff --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/interrupts.h @@ -0,0 +1,85 @@ +/** + * @file + * + * @brief Intel I386 Interrupt Macros + * + * Formerly contained in and extracted from libcpu/i386/cpu.h + */ + +/* + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Applications must not include this file directly. + */ + +#ifndef _RTEMS_SCORE_INTERRUPTS_H +#define _RTEMS_SCORE_INTERRUPTS_H + +#ifndef ASM + +struct __rtems_raw_irq_connect_data__; + +typedef void (*rtems_raw_irq_hdl) (void); +typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*); +typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*); +typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*); + +/** + * @name Interrupt Level Macros + * + */ +/**@{**/ +#if !defined(RTEMS_PARAVIRT) +#define i386_disable_interrupts( _level ) \ + { \ + __asm__ volatile ( "pushf ; \ + cli ; \ + pop %0" \ + : "=rm" ((_level)) \ + ); \ + } + +#define i386_enable_interrupts( _level ) \ + { \ + __asm__ volatile ( "push %0 ; \ + popf" \ + : : "rm" ((_level)) : "cc" \ + ); \ + } + +#define i386_flash_interrupts( _level ) \ + { \ + __asm__ volatile ( "push %0 ; \ + popf ; \ + cli" \ + : : "rm" ((_level)) : "cc" \ + ); \ + } + +#define i386_get_interrupt_level( _level ) \ + do { \ + register uint32_t _eflags; \ + \ + __asm__ volatile ( "pushf ; \ + pop %0" \ + : "=rm" ((_eflags)) \ + ); \ + \ + _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \ + } while (0) +#else +uint32_t i386_disable_interrupts( void ); +void i386_enable_interrupts(uint32_t level); +void i386_flash_interrupts(uint32_t level); +void i386_set_interrupt_level(uint32_t new_level); +uint32_t i386_get_interrupt_level( void ); +#endif /* PARAVIRT */ + +/** @} */ + +#endif +#endif diff --git a/cpukit/score/cpu/i386/include/rtems/score/registers.h b/cpukit/score/cpu/i386/include/rtems/score/registers.h new file mode 100644 index 0000000000..254fef701b --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/registers.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @brief Intel CPU Constants and Definitions + * + * This file contains definition and constants related to Intel Cpu + */ + +/* + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_REGISTERS_H +#define _RTEMS_SCORE_REGISTERS_H + +/* + * definition related to EFLAGS + */ +#define EFLAGS_CARRY 0x1 +#define EFLAGS_PARITY 0x4 + +#define EFLAGS_AUX_CARRY 0x10 +#define EFLAGS_ZERO 0x40 +#define EFLAGS_SIGN 0x80 + +#define EFLAGS_TRAP 0x100 +#define EFLAGS_INTR_ENABLE 0x200 +#define EFLAGS_DIRECTION 0x400 +#define EFLAGS_OVERFLOW 0x800 + +#define EFLAGS_IOPL_MASK 0x3000 +#define EFLAGS_NESTED_TASK 0x8000 + +#define EFLAGS_RESUME 0x10000 +#define EFLAGS_VIRTUAL_MODE 0x20000 +#define EFLAGS_ALIGN_CHECK 0x40000 +#define EFLAGS_VIRTUAL_INTR 0x80000 + +#define EFLAGS_VIRTUAL_INTR_PEND 0x100000 +#define EFLAGS_ID 0x200000 + +/* + * definitions related to CR0 + */ +#define CR0_PROTECTION_ENABLE 0x1 +#define CR0_MONITOR_COPROC 0x2 +#define CR0_COPROC_SOFT_EMUL 0x4 +#define CR0_FLOATING_INSTR_EXCEPTION 0x8 + +#define CR0_EXTENSION_TYPE 0x10 +#define CR0_NUMERIC_ERROR 0x20 + +#define CR0_WRITE_PROTECT 0x10000 +#define CR0_ALIGMENT_MASK 0x40000 + +#define CR0_NO_WRITE_THROUGH 0x20000000 +#define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 +#define CR0_PAGING 0x80000000 + +/* + * definitions related to CR3 + */ + +#define CR3_PAGE_CACHE_DISABLE 0x10 +#define CR3_PAGE_WRITE_THROUGH 0x8 +#define CR3_PAGE_DIRECTORY_MASK 0xFFFFF000 + +#endif diff --git a/cpukit/score/cpu/i386/include/rtems/score/types.h b/cpukit/score/cpu/i386/include/rtems/score/types.h new file mode 100644 index 0000000000..00555d41b5 --- /dev/null +++ b/cpukit/score/cpu/i386/include/rtems/score/types.h @@ -0,0 +1,46 @@ +/** + * @file + * + * @brief Intel I386 CPU Type Definitions + * + * This include file contains type definitions pertaining to the Intel + * i386 processor family. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void i386_isr; +typedef i386_isr ( *i386_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/i386/preinstall.am b/cpukit/score/cpu/i386/preinstall.am deleted file mode 100644 index 6eda753836..0000000000 --- a/cpukit/score/cpu/i386/preinstall.am +++ /dev/null @@ -1,61 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/i386.h: rtems/score/i386.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/i386.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/i386.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/interrupts.h: rtems/score/interrupts.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/interrupts.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/interrupts.h - -$(PROJECT_INCLUDE)/rtems/score/registers.h: rtems/score/registers.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/registers.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/registers.h - -$(PROJECT_INCLUDE)/rtems/score/idtr.h: rtems/score/idtr.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/idtr.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/idtr.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/i386/rtems/asm.h b/cpukit/score/cpu/i386/rtems/asm.h deleted file mode 100644 index 50b0fd71a0..0000000000 --- a/cpukit/score/cpu/i386/rtems/asm.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -/* - * Looks like there is a bug in gcc 2.6.2 where this is not - * defined correctly when configured as i386-coff and - * i386-aout. - */ - -#undef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ % - -/* -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif -*/ - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) - -#define eax REG (eax) -#define ebx REG (ebx) -#define ecx REG (ecx) -#define edx REG (edx) -#define esi REG (esi) -#define edi REG (edi) -#define esp REG (esp) -#define ebp REG (ebp) -#define cr0 REG (cr0) -#define cr4 REG (cr4) - -#define ax REG (ax) -#define bx REG (bx) -#define cx REG (cx) -#define dx REG (dx) -#define si REG (si) -#define di REG (di) -#define sp REG (sp) -#define bp REG (bp) - -#define ah REG (ah) -#define bh REG (bh) -#define ch REG (ch) -#define dh REG (dh) - -#define al REG (al) -#define bl REG (bl) -#define cl REG (cl) -#define dl REG (dl) - -#define cs REG (cs) -#define ds REG (ds) -#define es REG (es) -#define fs REG (fs) -#define gs REG (gs) -#define ss REG (ss) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h deleted file mode 100644 index f78149c24b..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/cpu.h +++ /dev/null @@ -1,700 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Dependent Source - * - * This include file contains information pertaining to the Intel - * i386 processor. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifndef ASM -#include /* for memcpy */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * i386 has an RTEMS allocated and managed interrupt stack. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Some family members have no FP, some have an FPU such as the i387 - * for the i386, others have it built in (i486DX, Pentium). - */ - -#ifdef __SSE__ -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP TRUE -#define CPU_IDLE_TASK_IS_FP TRUE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else /* __SSE__ */ - -#if ( I386_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE /* i387 for i386 */ -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#if defined(RTEMS_SMP) - #define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else - #define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif -#endif /* __SSE__ */ - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */ -#define CPU_CACHE_LINE_BYTES 64 - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -#define CPU_MAXIMUM_PROCESSORS 32 - -#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 -#define I386_CONTEXT_CONTROL_ESP_OFFSET 4 -#define I386_CONTEXT_CONTROL_EBP_OFFSET 8 -#define I386_CONTEXT_CONTROL_EBX_OFFSET 12 -#define I386_CONTEXT_CONTROL_ESI_OFFSET 16 -#define I386_CONTEXT_CONTROL_EDI_OFFSET 20 -#define I386_CONTEXT_CONTROL_GS_0_OFFSET 24 -#define I386_CONTEXT_CONTROL_GS_1_OFFSET 28 - -#ifdef RTEMS_SMP - #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32 -#endif - -/* structures */ - -#ifndef ASM - -/* - * Basic integer context for the i386 family. - */ - -typedef struct { - uint32_t eflags; /* extended flags register */ - void *esp; /* extended stack pointer register */ - void *ebp; /* extended base pointer register */ - uint32_t ebx; /* extended bx register */ - uint32_t esi; /* extended source index register */ - uint32_t edi; /* extended destination index flags register */ - segment_descriptors gs; /* gs segment descriptor */ -#ifdef RTEMS_SMP - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->esp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -/* - * FP context save area for the i387 numeric coprocessors. - */ -#ifdef __SSE__ -/* All FPU and SSE registers are volatile; hence, as long - * as we are within normally executing C code (including - * a task switch) there is no need for saving/restoring - * any of those registers. - * We must save/restore the full FPU/SSE context across - * interrupts and exceptions, however: - * - after ISR execution a _Thread_Dispatch() may happen - * and it is therefore necessary to save the FPU/SSE - * registers to be restored when control is returned - * to the interrupted task. - * - gcc may implicitly use FPU/SSE instructions in - * an ISR. - * - * Even though there is no explicit mentioning of the FPU - * control word in the SYSV ABI (i386) being non-volatile - * we maintain MXCSR and the FPU control-word for each task. - */ -typedef struct { - uint32_t mxcsr; - uint16_t fpucw; -} Context_Control_fp; - -#else - -typedef struct { - uint8_t fp_save_area[108]; /* context size area for I80387 */ - /* 28 bytes for environment */ -} Context_Control_fp; - -#endif - - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of execptions. - * - * idtIndex is either the interrupt number or the trap/exception number. - * faultCode is the code pushed by the processor on some exceptions. - * - * Since the first registers are directly pushed by the CPU they - * may not respect 16-byte stack alignment, which is, however, - * mandatory for the SSE register area. - * Therefore, these registers are stored at an aligned address - * and a pointer is stored in the CPU_Exception_frame. - * If the executive was compiled without SSE support then - * this pointer is NULL. - */ - -struct Context_Control_sse; - -typedef struct { - struct Context_Control_sse *fp_ctxt; - uint32_t edi; - uint32_t esi; - uint32_t ebp; - uint32_t esp0; - uint32_t ebx; - uint32_t edx; - uint32_t ecx; - uint32_t eax; - uint32_t idtIndex; - uint32_t faultCode; - uint32_t eip; - uint32_t cs; - uint32_t eflags; -} CPU_Exception_frame; - -#ifdef __SSE__ -typedef struct Context_Control_sse { - uint16_t fcw; - uint16_t fsw; - uint8_t ftw; - uint8_t res_1; - uint16_t fop; - uint32_t fpu_ip; - uint16_t cs; - uint16_t res_2; - uint32_t fpu_dp; - uint16_t ds; - uint16_t res_3; - uint32_t mxcsr; - uint32_t mxcsr_mask; - struct { - uint8_t fpreg[10]; - uint8_t res_4[ 6]; - } fp_mmregs[8]; - uint8_t xmmregs[8][16]; - uint8_t res_5[224]; -} Context_Control_sse -__attribute__((aligned(16))) -; -#endif - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(void); - -/* - * This port does not pass any frame info to the - * interrupt handler. - */ - -typedef void CPU_Interrupt_frame; - -typedef enum { - I386_EXCEPTION_DIVIDE_BY_ZERO = 0, - I386_EXCEPTION_DEBUG = 1, - I386_EXCEPTION_NMI = 2, - I386_EXCEPTION_BREAKPOINT = 3, - I386_EXCEPTION_OVERFLOW = 4, - I386_EXCEPTION_BOUND = 5, - I386_EXCEPTION_ILLEGAL_INSTR = 6, - I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, - I386_EXCEPTION_DOUBLE_FAULT = 8, - I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, - I386_EXCEPTION_INVALID_TSS = 10, - I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, - I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, - I386_EXCEPTION_GENERAL_PROT_ERR = 13, - I386_EXCEPTION_PAGE_FAULT = 14, - I386_EXCEPTION_INTEL_RES15 = 15, - I386_EXCEPTION_FLOAT_ERROR = 16, - I386_EXCEPTION_ALIGN_CHECK = 17, - I386_EXCEPTION_MACHINE_CHECK = 18, - I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ - -} Intel_symbolic_exception_name; - - -/* - * context size area for floating point - * - * NOTE: This is out of place on the i386 to avoid a forward reference. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* variables */ - -extern Context_Control_fp _CPU_Null_fp_context; - -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On i386 thread stacks require no further alignment after allocation - * from the Workspace. However, since gcc maintains 16-byte alignment - * we try to respect that. If you find an option to let gcc squeeze - * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still - * doesn't waste much space since this only determines the *initial* - * alignment. - */ - -#define CPU_STACK_ALIGNMENT 16 - -/* macros */ - -#ifndef ASM -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#if !defined(RTEMS_PARAVIRT) -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) __asm__ volatile ( "cli" ); \ - else __asm__ volatile ( "sti" ); \ - } -#else -#define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts() -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) -#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) -#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) -#endif - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & EFLAGS_INTR_ENABLE ) != 0; -} - -uint32_t _CPU_ISR_Get_level( void ); - -/* Make sure interrupt stack has space for ISR - * 'vector' arg at the top and that it is aligned - * properly. - */ - -#define _CPU_Interrupt_stack_setup( _lo, _hi ) \ - do { \ - _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ - } while (0) - -#endif /* ASM */ - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 -#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 - -#ifndef ASM - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#if defined(RTEMS_SMP) - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - /* Nothing to do */ - #define _CPU_SMP_Prepare_start_multitasking() do { } while ( 0 ) - - uint32_t _CPU_SMP_Get_current_processor( void ); - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ - } - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) - RTEMS_NO_RETURN; - -#endif /* ASM */ - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register uint16_t __value_in_register = ( _value ); \ - uint16_t __output = 0; \ - __asm__ volatile ( "bsfw %0,%1 " \ - : "=r" ( __value_in_register ), "=r" ( __output ) \ - : "0" ( __value_in_register ), "1" ( __output ) \ - ); \ - ( _output ) = __output; \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* functions */ - -#ifndef ASM -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * Use the halt instruction of low power mode of a particular i386 model. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -#ifdef __SSE__ -#define _CPU_Context_save_fp(fp_context_pp) \ - do { \ - __asm__ __volatile__( \ - "fstcw %0" \ - :"=m"((*(fp_context_pp))->fpucw) \ - ); \ - __asm__ __volatile__( \ - "stmxcsr %0" \ - :"=m"((*(fp_context_pp))->mxcsr) \ - ); \ - } while (0) -#else -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ -#ifdef __SSE__ -#define _CPU_Context_restore_fp(fp_context_pp) \ - do { \ - __asm__ __volatile__( \ - "fldcw %0" \ - ::"m"((*(fp_context_pp))->fpucw) \ - :"fpcr" \ - ); \ - __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ - } while (0) -#else -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -#ifdef __SSE__ -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ __volatile__( \ - "finit" \ - : \ - : \ - :"st","st(1)","st(2)","st(3)", \ - "st(4)","st(5)","st(6)","st(7)", \ - "fpsr","fpcr" \ - ); \ - if ( _Thread_Executing->fp_context ) { \ - _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ - } \ - } while (0) -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/cpuatomic.h b/cpukit/score/cpu/i386/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/i386/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/i386/rtems/score/i386.h b/cpukit/score/cpu/i386/rtems/score/i386.h deleted file mode 100644 index 2555d13b8b..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/i386.h +++ /dev/null @@ -1,670 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Dependent Source - * - * This include file contains information pertaining to the Intel - * i386 processor. - */ - -/* - * COPYRIGHT (c) 1989-2016. - * On-Line Applications Research Corporation (OAR). - * - * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_I386_H -#define _RTEMS_SCORE_I386_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Intel i386 - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized: - * i386_fp (i386 DX or SX w/i387) - * i486dx - * pentium - * pentiumpro - * - * CPU Model Feature Flags: - * - * I386_HAS_BSWAP: Defined to "1" if the instruction for endian swapping - * (bswap) should be used. This instruction appears to - * be present in all i486's and above. - * - * I386_HAS_FPU: Defined to "1" if the CPU has an FPU. - * As of at least gcc 4.7, i386 soft-float was obsoleted. - * Thus this is always set to "1". - */ -#define I386_HAS_FPU 1 - -#if defined(__pentiumpro__) - - #define CPU_MODEL_NAME "Pentium Pro" - -#elif defined(__i586__) - - #if defined(__pentium__) - #define CPU_MODEL_NAME "Pentium" - #elif defined(__k6__) - #define CPU_MODEL_NAME "K6" - #else - #define CPU_MODEL_NAME "i586" - #endif - -#elif defined(__i486__) - - #define CPU_MODEL_NAME "i486dx" - -#elif defined(__i386__) - - #define I386_HAS_BSWAP 0 - #define CPU_MODEL_NAME "i386 with i387" - -#else - #error "Unknown CPU Model" -#endif - -/* - * Set default values for CPU model feature flags - * - * NOTE: These settings are chosen to reflect most of the family members. - */ -#ifndef I386_HAS_BSWAP -#define I386_HAS_BSWAP 1 -#endif - -/* - * Define the name of the CPU family. - */ -#define CPU_NAME "Intel i386" - -#ifndef ASM - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static so it can be referenced indirectly. - */ - -static inline uint32_t i386_swap_u32( - uint32_t value -) -{ - uint32_t lout; - -#if (I386_HAS_BSWAP == 0) - __asm__ volatile( "rorw $8,%%ax;" - "rorl $16,%0;" - "rorw $8,%%ax" : "=a" (lout) : "0" (value) ); -#else - __asm__ volatile( "bswap %0" : "=r" (lout) : "0" (value)); -#endif - return( lout ); -} -#define CPU_swap_u32( _value ) i386_swap_u32( _value ) - -static inline uint16_t i386_swap_u16( - uint16_t value -) -{ - unsigned short sout; - - __asm__ volatile( "rorw $8,%0" : "=r" (sout) : "0" (value)); - return (sout); -} -#define CPU_swap_u16( _value ) i386_swap_u16( _value ) - -/* - * Added for pagination management - */ -static inline unsigned int i386_get_cr0(void) -{ - register unsigned int segment = 0; - - __asm__ volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr0(unsigned int segment) -{ - __asm__ volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) ); -} - -static inline unsigned int i386_get_cr2(void) -{ - register unsigned int segment = 0; - - __asm__ volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline unsigned int i386_get_cr3(void) -{ - register unsigned int segment = 0; - - __asm__ volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr3(unsigned int segment) -{ - __asm__ volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); -} - -/* routines */ - -/* - * i386_Logical_to_physical - * - * Converts logical address to physical address. - */ -void *i386_Logical_to_physical( - unsigned short segment, - void *address -); - -/* - * i386_Physical_to_logical - * - * Converts physical address to logical address. - */ -void *i386_Physical_to_logical( - unsigned short segment, - void *address -); - -/** - * @brief Converts real mode pointer {segment, offset} to physical address. - * - * i386_Real_to_physical - * - * @param[in] segment used with \p offset to compute physical address - * @param[in] offset used with \p segment to compute physical address - * @retval physical address - */ -RTEMS_INLINE_ROUTINE void *i386_Real_to_physical( - uint16_t segment, - uint16_t offset) -{ - return (void *)(((uint32_t)segment<<4)+offset); -} - -/** - * @brief Retrieves real mode pointer elements {segmnet, offset} from - * physical address. - * - * i386_Physical_to_real - * Function returns the highest segment (base) address possible. - * Example: input address - 0x4B3A2 - * output segment - 0x4B3A - * offset - 0x2 - * input address - 0x10F12E - * output segment - 0xFFFF - * offset - 0xF13E - * - * @param[in] address address to be converted, must be less than 0x10FFEF - * @param[out] segment segment computed from \p address - * @param[out] offset offset computed from \p address - * @retval 0 address not convertible - * @retval 1 segment and offset extracted - */ -int i386_Physical_to_real( - void *address, - uint16_t *segment, - uint16_t *offset -); - -/* - * Segment Access Routines - * - * NOTE: Unfortunately, these are still static inlines even when the - * "macro" implementation of the generic code is used. - */ - -static __inline__ unsigned short i386_get_cs(void) -{ - register unsigned short segment = 0; - - __asm__ volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static __inline__ unsigned short i386_get_ds(void) -{ - register unsigned short segment = 0; - - __asm__ volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static __inline__ unsigned short i386_get_es(void) -{ - register unsigned short segment = 0; - - __asm__ volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static __inline__ unsigned short i386_get_ss(void) -{ - register unsigned short segment = 0; - - __asm__ volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static __inline__ unsigned short i386_get_fs(void) -{ - register unsigned short segment = 0; - - __asm__ volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static __inline__ unsigned short i386_get_gs(void) -{ - register unsigned short segment = 0; - - __asm__ volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -/* - * IO Port Access Routines - */ - -#define i386_outport_byte( _port, _value ) \ -do { register unsigned short __port = _port; \ - register unsigned char __value = _value; \ - \ - __asm__ volatile ( "outb %0,%1" : : "a" (__value), "d" (__port) ); \ - } while (0) - -#define i386_outport_word( _port, _value ) \ -do { register unsigned short __port = _port; \ - register unsigned short __value = _value; \ - \ - __asm__ volatile ( "outw %0,%1" : : "a" (__value), "d" (__port) ); \ - } while (0) - -#define i386_outport_long( _port, _value ) \ -do { register unsigned short __port = _port; \ - register unsigned int __value = _value; \ - \ - __asm__ volatile ( "outl %0,%1" : : "a" (__value), "d" (__port) ); \ - } while (0) - -#define i386_inport_byte( _port, _value ) \ -do { register unsigned short __port = _port; \ - register unsigned char __value = 0; \ - \ - __asm__ volatile ( "inb %1,%0" : "=a" (__value) \ - : "d" (__port) \ - ); \ - _value = __value; \ - } while (0) - -#define i386_inport_word( _port, _value ) \ -do { register unsigned short __port = _port; \ - register unsigned short __value = 0; \ - \ - __asm__ volatile ( "inw %1,%0" : "=a" (__value) \ - : "d" (__port) \ - ); \ - _value = __value; \ - } while (0) - -#define i386_inport_long( _port, _value ) \ -do { register unsigned short __port = _port; \ - register unsigned int __value = 0; \ - \ - __asm__ volatile ( "inl %1,%0" : "=a" (__value) \ - : "d" (__port) \ - ); \ - _value = __value; \ - } while (0) - -/* - * Type definition for raw interrupts. - */ - -typedef unsigned char rtems_vector_offset; - -typedef struct __rtems_raw_irq_connect_data__{ - /* - * IDT vector offset (IRQ line + PC386_IRQ_VECTOR_BASE) - */ - rtems_vector_offset idtIndex; - /* - * IDT raw handler. See comment on handler properties below in function prototype. - */ - rtems_raw_irq_hdl hdl; - /* - * function for enabling raw interrupts. In order to be consistent - * with the fact that the raw connexion can defined in the - * libcpu library, this library should have no knowledge of - * board specific hardware to manage interrupts and thus the - * "on" routine must enable the irq both at device and PIC level. - * - */ - rtems_raw_irq_enable on; - /* - * function for disabling raw interrupts. In order to be consistent - * with the fact that the raw connexion can defined in the - * libcpu library, this library should have no knowledge of - * board specific hardware to manage interrupts and thus the - * "on" routine must disable the irq both at device and PIC level. - * - */ - rtems_raw_irq_disable off; - /* - * function enabling to know what interrupt may currently occur - */ - rtems_raw_irq_is_enabled isOn; -}rtems_raw_irq_connect_data; - -typedef struct { - /* - * size of all the table fields (*Tbl) described below. - */ - unsigned int idtSize; - /* - * Default handler used when disconnecting interrupts. - */ - rtems_raw_irq_connect_data defaultRawEntry; - /* - * Table containing initials/current value. - */ - rtems_raw_irq_connect_data* rawIrqHdlTbl; -}rtems_raw_irq_global_settings; - -#include - -/* - * C callable function enabling to get handler currently connected to a vector - * - */ -rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset); - -/* - * C callable function enabling to set up one raw idt entry - */ -extern int i386_set_idt_entry (const rtems_raw_irq_connect_data*); - -/* - * C callable function enabling to get one current raw idt entry - */ -extern int i386_get_current_idt_entry (rtems_raw_irq_connect_data*); - -/* - * C callable function enabling to remove one current raw idt entry - */ -extern int i386_delete_idt_entry (const rtems_raw_irq_connect_data*); - -/* - * C callable function enabling to init idt. - * - * CAUTION : this function assumes that the IDTR register - * has been already set. - */ -extern int i386_init_idt (rtems_raw_irq_global_settings* config); - -/* - * C callable function enabling to get actual idt configuration - */ -extern int i386_get_idt_config (rtems_raw_irq_global_settings** config); - - -/* - * See page 11.12 Figure 11-8. - * - */ -/** - * @brief describes one entry of Global/Local Descriptor Table - */ -typedef struct { - unsigned int limit_15_0 : 16; - unsigned int base_address_15_0 : 16; - unsigned int base_address_23_16 : 8; - unsigned int type : 4; - unsigned int descriptor_type : 1; - unsigned int privilege : 2; - unsigned int present : 1; - unsigned int limit_19_16 : 4; - unsigned int available : 1; - unsigned int fixed_value_bits : 1; - unsigned int operation_size : 1; - unsigned int granularity : 1; - unsigned int base_address_31_24 : 8; -} RTEMS_PACKED segment_descriptors; - -/* - * C callable function enabling to get easilly usable info from - * the actual value of GDT register. - */ -extern void i386_get_info_from_GDTR (segment_descriptors** table, - uint16_t* limit); -/* - * C callable function enabling to change the value of GDT register. Must be called - * with interrupts masked at processor level!!!. - */ -extern void i386_set_GDTR (segment_descriptors*, - uint16_t limit); - -/** - * @brief Allows to set a GDT entry. - * - * Puts global descriptor \p sd to the global descriptor table on index - * \p segment_selector_index - * - * @param[in] segment_selector_index index to GDT entry - * @param[in] sd structure to be coppied to given \p segment_selector in GDT - * @retval 0 FAILED out of GDT range or index is 0, which is not valid - * index in GDT - * @retval 1 SUCCESS - */ -extern uint32_t i386_raw_gdt_entry (uint16_t segment_selector_index, - segment_descriptors* sd); - -/** - * @brief fills \p sd with provided \p base in appropriate fields of \p sd - * - * @param[in] base 32-bit address to be set as descriptor's base - * @param[out] sd descriptor being filled with \p base - */ -extern void i386_fill_segment_desc_base (uint32_t base, - segment_descriptors* sd); - -/** - * @brief fills \p sd with provided \p limit in appropriate fields of \p sd - * - * sets granularity bit if necessary - * - * @param[in] limit 32-bit value representing number of limit bytes - * @param[out] sd descriptor being filled with \p limit - */ -extern void i386_fill_segment_desc_limit (uint32_t limit, - segment_descriptors* sd); - -/* - * C callable function enabling to set up one raw interrupt handler - */ -extern uint32_t i386_set_gdt_entry (uint16_t segment_selector, - uint32_t base, - uint32_t limit); - -/** - * @brief Returns next empty descriptor in GDT. - * - * Number of descriptors that can be returned depends on \a GDT_SIZE - * - * @retval 0 FAILED GDT is full - * @retval <1;65535> segment_selector number as index to GDT - */ -extern uint16_t i386_next_empty_gdt_entry (void); - -/** - * @brief Copies GDT entry at index \p segment_selector to structure - * pointed to by \p struct_to_fill - * - * @param[in] segment_selector index to GDT table specifying descriptor to copy - * @param[out] struct_to_fill pointer to memory where will be descriptor coppied - * @retval 0 FAILED segment_selector out of GDT range - * @retval <1;65535> retrieved segment_selector - */ -extern uint16_t i386_cpy_gdt_entry (uint16_t segment_selector, - segment_descriptors* struct_to_fill); - -/** - * @brief Returns pointer to GDT table at index given by \p segment_selector - * - * @param[in] sgmnt_selector index to GDT table for specifying descriptor to get - * @retval NULL FAILED segment_selector out of GDT range - * @retval pointer to GDT table at \p segment_selector - */ -extern segment_descriptors* i386_get_gdt_entry (uint16_t sgmnt_selector); - -/** - * @brief Extracts base address from GDT entry pointed to by \p gdt_entry - * - * @param[in] gdt_entry pointer to entry from which base should be retrieved - * @retval base address from GDT entry -*/ -RTEMS_INLINE_ROUTINE void* i386_base_gdt_entry (segment_descriptors* gdt_entry) -{ - return (void*)(gdt_entry->base_address_15_0 | - (gdt_entry->base_address_23_16<<16) | - (gdt_entry->base_address_31_24<<24)); -} - -/** - * @brief Extracts limit in bytes from GDT entry pointed to by \p gdt_entry - * - * @param[in] gdt_entry pointer to entry from which limit should be retrieved - * @retval limit value in bytes from GDT entry - */ -extern uint32_t i386_limit_gdt_entry (segment_descriptors* gdt_entry); - -/* - * See page 11.18 Figure 11-12. - * - */ - -typedef struct { - unsigned int offset : 12; - unsigned int page : 10; - unsigned int directory : 10; -}la_bits; - -typedef union { - la_bits bits; - unsigned int address; -}linear_address; - - -/* - * See page 11.20 Figure 11-14. - * - */ - -typedef struct { - unsigned int present : 1; - unsigned int writable : 1; - unsigned int user : 1; - unsigned int write_through : 1; - unsigned int cache_disable : 1; - unsigned int accessed : 1; - unsigned int reserved1 : 1; - unsigned int page_size : 1; - unsigned int reserved2 : 1; - unsigned int available : 3; - unsigned int page_frame_address : 20; -}page_dir_bits; - -typedef union { - page_dir_bits bits; - unsigned int dir_entry; -}page_dir_entry; - -typedef struct { - unsigned int present : 1; - unsigned int writable : 1; - unsigned int user : 1; - unsigned int write_through : 1; - unsigned int cache_disable : 1; - unsigned int accessed : 1; - unsigned int dirty : 1; - unsigned int reserved2 : 2; - unsigned int available : 3; - unsigned int page_frame_address : 20; -}page_table_bits; - -typedef union { - page_table_bits bits; - unsigned int table_entry; -} page_table_entry; - -/* - * definitions related to page table entry - */ -#define PG_SIZE 0x1000 -#define MASK_OFFSET 0xFFF -#define MAX_ENTRY (PG_SIZE/sizeof(page_dir_entry)) -#define FOUR_MB 0x400000 -#define MASK_FLAGS 0x1A - -#define PTE_PRESENT 0x01 -#define PTE_WRITABLE 0x02 -#define PTE_USER 0x04 -#define PTE_WRITE_THROUGH 0x08 -#define PTE_CACHE_DISABLE 0x10 - -typedef struct { - page_dir_entry pageDirEntry[MAX_ENTRY]; -} page_directory; - -typedef struct { - page_table_entry pageTableEntry[MAX_ENTRY]; -} page_table; - -/* Simpler names for the i80x86 I/O instructions */ -#define outport_byte( _port, _value ) i386_outport_byte( _port, _value ) -#define outport_word( _port, _value ) i386_outport_word( _port, _value ) -#define outport_long( _port, _value ) i386_outport_long( _port, _value ) -#define inport_byte( _port, _value ) i386_inport_byte( _port, _value ) -#define inport_word( _port, _value ) i386_inport_word( _port, _value ) -#define inport_long( _port, _value ) i386_inport_long( _port, _value ) - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/idtr.h b/cpukit/score/cpu/i386/rtems/score/idtr.h deleted file mode 100644 index a79af40792..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/idtr.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * @file - * - * @brief Intel I386 Data Structures - * - * This file contains definitions for data structure related - * to Intel system programming. More information can be found - * on Intel site and more precisely in the following book : - * - * Pentium Processor familly - * Developper's Manual - * - * Volume 3 : Architecture and Programming Manual - * - * Formerly contained in and extracted from libcpu/i386/cpu.h. - */ - -/* - * COPYRIGHT (C) 1998 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Applications must not include this file directly. - */ - -#ifndef _RTEMS_SCORE_IDTR_H -#define _RTEMS_SCORE_IDTR_H - -/* - * See page 14.9 Figure 14-2. - * - */ -typedef struct -{ - unsigned int low_offsets_bits:16; - unsigned int segment_selector:16; - unsigned int fixed_value_bits:8; - unsigned int gate_type:5; - unsigned int privilege:2; - unsigned int present:1; - unsigned int high_offsets_bits:16; -} interrupt_gate_descriptor; - -/* - * C callable function enabling to create a interrupt_gate_descriptor - */ -extern void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl); - -/* - * C callable function enabling to get easily usable info from - * the actual value of IDT register. - */ -extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table, - unsigned* limit); - -/* - * C callable function enabling to change the value of IDT register. Must be called - * with interrupts masked at processor level!!!. - */ -extern void i386_set_IDTR (interrupt_gate_descriptor* table, - unsigned limit); - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/interrupts.h b/cpukit/score/cpu/i386/rtems/score/interrupts.h deleted file mode 100644 index 3a7971c1ff..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/interrupts.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file - * - * @brief Intel I386 Interrupt Macros - * - * Formerly contained in and extracted from libcpu/i386/cpu.h - */ - -/* - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Applications must not include this file directly. - */ - -#ifndef _RTEMS_SCORE_INTERRUPTS_H -#define _RTEMS_SCORE_INTERRUPTS_H - -#ifndef ASM - -struct __rtems_raw_irq_connect_data__; - -typedef void (*rtems_raw_irq_hdl) (void); -typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*); -typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*); -typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*); - -/** - * @name Interrupt Level Macros - * - */ -/**@{**/ -#if !defined(RTEMS_PARAVIRT) -#define i386_disable_interrupts( _level ) \ - { \ - __asm__ volatile ( "pushf ; \ - cli ; \ - pop %0" \ - : "=rm" ((_level)) \ - ); \ - } - -#define i386_enable_interrupts( _level ) \ - { \ - __asm__ volatile ( "push %0 ; \ - popf" \ - : : "rm" ((_level)) : "cc" \ - ); \ - } - -#define i386_flash_interrupts( _level ) \ - { \ - __asm__ volatile ( "push %0 ; \ - popf ; \ - cli" \ - : : "rm" ((_level)) : "cc" \ - ); \ - } - -#define i386_get_interrupt_level( _level ) \ - do { \ - register uint32_t _eflags; \ - \ - __asm__ volatile ( "pushf ; \ - pop %0" \ - : "=rm" ((_eflags)) \ - ); \ - \ - _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \ - } while (0) -#else -uint32_t i386_disable_interrupts( void ); -void i386_enable_interrupts(uint32_t level); -void i386_flash_interrupts(uint32_t level); -void i386_set_interrupt_level(uint32_t new_level); -uint32_t i386_get_interrupt_level( void ); -#endif /* PARAVIRT */ - -/** @} */ - -#endif -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/registers.h b/cpukit/score/cpu/i386/rtems/score/registers.h deleted file mode 100644 index 254fef701b..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/registers.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief Intel CPU Constants and Definitions - * - * This file contains definition and constants related to Intel Cpu - */ - -/* - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_REGISTERS_H -#define _RTEMS_SCORE_REGISTERS_H - -/* - * definition related to EFLAGS - */ -#define EFLAGS_CARRY 0x1 -#define EFLAGS_PARITY 0x4 - -#define EFLAGS_AUX_CARRY 0x10 -#define EFLAGS_ZERO 0x40 -#define EFLAGS_SIGN 0x80 - -#define EFLAGS_TRAP 0x100 -#define EFLAGS_INTR_ENABLE 0x200 -#define EFLAGS_DIRECTION 0x400 -#define EFLAGS_OVERFLOW 0x800 - -#define EFLAGS_IOPL_MASK 0x3000 -#define EFLAGS_NESTED_TASK 0x8000 - -#define EFLAGS_RESUME 0x10000 -#define EFLAGS_VIRTUAL_MODE 0x20000 -#define EFLAGS_ALIGN_CHECK 0x40000 -#define EFLAGS_VIRTUAL_INTR 0x80000 - -#define EFLAGS_VIRTUAL_INTR_PEND 0x100000 -#define EFLAGS_ID 0x200000 - -/* - * definitions related to CR0 - */ -#define CR0_PROTECTION_ENABLE 0x1 -#define CR0_MONITOR_COPROC 0x2 -#define CR0_COPROC_SOFT_EMUL 0x4 -#define CR0_FLOATING_INSTR_EXCEPTION 0x8 - -#define CR0_EXTENSION_TYPE 0x10 -#define CR0_NUMERIC_ERROR 0x20 - -#define CR0_WRITE_PROTECT 0x10000 -#define CR0_ALIGMENT_MASK 0x40000 - -#define CR0_NO_WRITE_THROUGH 0x20000000 -#define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 -#define CR0_PAGING 0x80000000 - -/* - * definitions related to CR3 - */ - -#define CR3_PAGE_CACHE_DISABLE 0x10 -#define CR3_PAGE_WRITE_THROUGH 0x8 -#define CR3_PAGE_DIRECTORY_MASK 0xFFFFF000 - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/types.h b/cpukit/score/cpu/i386/rtems/score/types.h deleted file mode 100644 index 00555d41b5..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * i386 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void i386_isr; -typedef i386_isr ( *i386_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/lm32/Makefile.am b/cpukit/score/cpu/lm32/Makefile.am index 72cb69abcc..75bcba5793 100644 --- a/cpukit/score/cpu/lm32/Makefile.am +++ b/cpukit/score/cpu/lm32/Makefile.am @@ -1,21 +1,10 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/lm32.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c cpu_asm.S irq.c libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += lm32-exception-frame-print.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/lm32/headers.am b/cpukit/score/cpu/lm32/headers.am new file mode 100644 index 0000000000..68128ca00b --- /dev/null +++ b/cpukit/score/cpu/lm32/headers.am @@ -0,0 +1,18 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/lm32.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/lm32/include/machine/elf_machdep.h b/cpukit/score/cpu/lm32/include/machine/elf_machdep.h new file mode 100644 index 0000000000..29c75b89db --- /dev/null +++ b/cpukit/score/cpu/lm32/include/machine/elf_machdep.h @@ -0,0 +1,34 @@ +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB + +#define ELF32_MACHDEP_ID_CASES \ + case EM_LATTICEMICO32: \ + break; + +#define ELF32_MACHDEP_ID EM_LATTICEMICO32 + +#define EF_MACH32_MACH 0x00000001 + +//#define EF_BLACKFIN + +#define ARCH_ELFSIZE 32 + +#define R_LM32_NONE 0 +#define R_LM32_8 1 +#define R_LM32_16 2 +#define R_LM32_32 3 +#define R_LM32_HI16 4 +#define R_LM32_LO16 5 +#define R_LM32_GPREL16 6 +#define R_LM32_CALL 7 +#define R_LM32_BRANCH 8 +#define R_LM32_GNU_VTINHERIT 9 +#define R_LM32_GNU_VTENTRY 10 +#define R_LM32_16_GOT 11 +#define R_LM32_GOTOFF_HI16 12 +#define R_LM32_GOTOFF_LO16 13 +#define R_LM32_COPY 14 +#define R_LM32_GLOT_DAT 15 +#define R_LM32_JMP_SLOT 16 +#define R_LM32_RELATIVE 17 + +#define R_TYPE(name) __CONCAT(R_LM32_,name) diff --git a/cpukit/score/cpu/lm32/include/rtems/asm.h b/cpukit/score/cpu/lm32/include/rtems/asm.h new file mode 100644 index 0000000000..15046df81c --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/asm.h @@ -0,0 +1,127 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-2006. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all register names. + */ +#define __REGISTER_PREFIX__ +#endif + +#include + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** This macro is used to denote the beginning of a data declaration section. */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** + * This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * NOTE: This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * NOTE: This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h new file mode 100644 index 0000000000..9d229948aa --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h @@ -0,0 +1,1035 @@ +/** + * @file + * + * @brief LM32 CPU Department Source + * + * This include file contains information pertaining to the LM32 + * processor. + */ + +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/** + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/** + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/** + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ISR_PASSES_FRAME_POINTER TRUE + +/** + * @def CPU_HARDWARE_FP + * + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? + * + * This feature conditional is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPUs in which this option has been used are the + * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and + * gcc both implicitly used the floating point registers to perform + * integer multiplies. Similarly, the PowerPC port of gcc has been + * seen to allocate floating point local variables and touch the FPU + * even when the flow through a subroutine (like vfprintf()) might + * not use floating point formats. + * + * If a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/** + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine @ref _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * @ref _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_GROWS_UP FALSE + +/* L2 cache lines are 32 bytes in Milkymist SoC */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/** + * @ingroup CPUInterrupt + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* may need to put some structures here. */ + +/** + * @defgroup CPUContext Processor Dependent Context Management + * + * From the highest level viewpoint, there are 2 types of context to save. + * + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +/**@{**/ + +/** + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ +typedef struct { + uint32_t r11; + uint32_t r12; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t gp; + uint32_t fp; + uint32_t sp; + uint32_t ra; + uint32_t ie; + uint32_t epc; +} Context_Control; + +/** + * + * This macro returns the stack pointer associated with @a _context. + * + * @param[in] _context is the thread context area to access + * + * @return This method returns the stack pointer. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->sp + +/** + * This defines the complete set of floating point registers that must + * be saved during any context switch from one thread to another. + */ +typedef struct { +} Context_Control_fp; + +/** + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ +typedef struct { + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t ra; + uint32_t ba; + uint32_t ea; +} CPU_Interrupt_frame; + +/** + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * @ref _CPU_Initialize and copied into the task's FP context area during + * @ref _CPU_Context_Initialize. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if 0 +extern Context_Control_fp _CPU_Null_fp_context; +#endif + +/** @} */ + +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in @ref _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * NOTE: These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +/**@{**/ + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* XXX: if needed, put more variables here */ + +/** + * @ingroup CPUContext + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/** + * This defines the number of entries in the @ref _ISR_Vector_table managed + * by RTEMS. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +/** + * This defines the highest interrupt vector number for this port. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/** + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable @a _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** @} */ + +/** + * @ingroup CPUContext + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +#define CPU_SIZEOF_POINTER 4 + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * Port Specific Information: + * The LM32 architecture manual simply states: "All memory accesses must be + * aligned to the size of the access", and there is no hardware support + * whatsoever for 64-bit numbers. + * (lm32_archman.pdf, July 2009, p. 15) + */ +#define CPU_ALIGNMENT 4 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by @ref CPU_ALIGNMENT. + * + * + * Port Specific Information: + * + * Stack is software-managed + */ +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +/* + * ISR handler macros + */ + +/** + * @addtogroup CPUInterrupt + */ +/**@{**/ + +/** + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Initialize_vectors() + +/** + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in @a _isr_cookie. + * + * @param[out] _isr_cookie will contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Disable( _isr_cookie ) \ + lm32_disable_interrupts( _isr_cookie ); + +/** + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * @a _isr_cookie is not modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Enable( _isr_cookie ) \ + lm32_enable_interrupts( _isr_cookie ); + +/** + * This temporarily restores the interrupt to @a _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Flash( _isr_cookie ) \ + lm32_flash_interrupts( _isr_cookie ); + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & 0x0001 ) != 0; +} + +/** + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Set_level( new_level ) \ + { \ + _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \ + } + +/** + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * NOTE: This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/** @} */ + +/* Context handler macros */ + +/** + * @ingroup CPUContext + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * @param[in] _the_context is the context structure to be initialized + * @param[in] _stack_base is the lowest physical address of this task's stack + * @param[in] _size is the size of this task's stack + * @param[in] _isr is the interrupt disable level + * @param[in] _entry_point is the thread's entry point. This is + * always @a _Thread_Handler + * @param[in] _is_fp is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +extern char _gp[]; + +#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ + _isr, _entry_point, _is_fp, _tls_area ) \ + do { \ + uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ + \ + (void) _is_fp; /* avoid warning for being unused */ \ + (void) _isr; /* avoid warning for being unused */ \ + (_the_context)->gp = (uint32_t)_gp; \ + (_the_context)->fp = (uint32_t)_stack; \ + (_the_context)->sp = (uint32_t)_stack; \ + (_the_context)->ra = (uint32_t)(_entry_point); \ + } while ( 0 ) + +/** + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. For many ports, simply adding a label to the restore path + * of @ref _CPU_Context_switch will work. On other ports, it may be + * possibly to load a few arguments and jump to the restore path. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/** + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * @a _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other floating point context save/restore models include: + * -# not doing anything, and + * -# putting a "null FP status word" in the correct place in the FP context. + * + * @param[in] _destination is the floating point context area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Initialize_fp( _destination ) +#if 0 + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } +#endif + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Fatal_halt( _source, _error ) \ + { \ + } + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/** + * This routine performs CPU dependent initialization. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Initialize(void); + +/** + * @addtogroup CPUInterrupt + */ +/**@{**/ + +/** + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the raw ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the RTEMS ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Install_interrupt_stack( void ); + +/** @} */ + +/** + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/** + * @ingroup CPUContext + * This routine switches from the run context to the heir context. + * + * @param[in] run points to the context of the currently executing task + * @param[in] heir points to the context of the heir task + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * @addtogroup CPUContext + */ +/**@{**/ + +/** + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. + * + * @param[in] new_context points to the context to be restored. + * + * NOTE: May be unnecessary to reload some registers. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/** + * This routine saves the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_restore_fp to restore this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * This routine restores the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area to restore + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_save_fp to save this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/** @} */ + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @ingroup CPUEndian + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +} + +/** + * @ingroup CPUEndian + * This routine swaps a 16 bir quantity. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + */ +static inline uint16_t CPU_swap_u16(uint16_t v) +{ + return v << 8 | v >> 8; +} + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/lm32/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..3909c1d608 --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief LM32 CPU Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/lm32/include/rtems/score/lm32.h b/cpukit/score/cpu/lm32/include/rtems/score/lm32.h new file mode 100644 index 0000000000..e8fecdf2f6 --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/score/lm32.h @@ -0,0 +1,112 @@ +/** + * @file + * + * @brief LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specified to the NO CPU port. + */ +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Jukka Pietarinen , 2008, + * Micro-Research Finland Oy + */ + +#ifndef _RTEMS_SCORE_LM32_H +#define _RTEMS_SCORE_LM32_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the NO CPU family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +#if defined(rtems_multilib) +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#define CPU_MODEL_NAME "rtems_multilib" +#define LM32_HAS_FPU 0 + +#elif defined(__lm32__) + +#define CPU_MODEL_NAME "lm32" +#define LM32_HAS_FPU 0 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "LM32" + +#ifdef __cplusplus +} +#endif + +#define lm32_read_interrupts( _ip) \ + __asm__ volatile ("rcsr %0, ip":"=r"(_ip)); + +#define lm32_disable_interrupts( _level ) \ + do { register uint32_t ie; \ + __asm__ volatile ("rcsr %0,ie":"=r"(ie)); \ + (_level) = ie; \ + ie &= (~0x0001); \ + __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \ + } while (0) + +#define lm32_enable_interrupts( _level ) \ + __asm__ volatile ("wcsr ie,%0"::"r"(_level)); + +#define lm32_flash_interrupts( _level ) \ + do { register uint32_t ie; \ + __asm__ volatile ("wcsr ie,%0"::"r"(_level)); \ + ie = (_level) & (~0x0001); \ + __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \ + } while (0) + +#define lm32_interrupt_unmask( _mask ) \ + do { register uint32_t im; \ + __asm__ volatile ("rcsr %0,im":"=r"(im)); \ + im |= _mask; \ + __asm__ volatile ("wcsr im,%0"::"r"(im)); \ + } while (0) + +#define lm32_interrupt_mask( _mask ) \ + do { register uint32_t im; \ + __asm__ volatile ("rcsr %0,im":"=r"(im)); \ + im &= ~(_mask); \ + __asm__ volatile ("wcsr im,%0"::"r"(im)); \ + } while (0) + +#define lm32_interrupt_ack( _mask ) \ + do { register uint32_t ip = _mask; \ + __asm__ volatile ("wcsr ip,%0"::"r"(ip)); \ + } while (0) + +#endif /* _RTEMS_SCORE_LM32_H */ diff --git a/cpukit/score/cpu/lm32/include/rtems/score/types.h b/cpukit/score/cpu/lm32/include/rtems/score/types.h new file mode 100644 index 0000000000..c3d8666de4 --- /dev/null +++ b/cpukit/score/cpu/lm32/include/rtems/score/types.h @@ -0,0 +1,46 @@ +/** + * @file + * + * @brief LM32 CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * Lattice lm32 processor family. + */ + +/* + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Jukka Pietarinen , 2008, + * Micro-Research Finland Oy + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/lm32/preinstall.am b/cpukit/score/cpu/lm32/preinstall.am deleted file mode 100644 index 282353f3f7..0000000000 --- a/cpukit/score/cpu/lm32/preinstall.am +++ /dev/null @@ -1,53 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/lm32.h: rtems/score/lm32.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/lm32.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/lm32.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/lm32/rtems/asm.h b/cpukit/score/cpu/lm32/rtems/asm.h deleted file mode 100644 index 15046df81c..0000000000 --- a/cpukit/score/cpu/lm32/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h deleted file mode 100644 index 9d229948aa..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpu.h +++ /dev/null @@ -1,1035 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Department Source - * - * This include file contains information pertaining to the LM32 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER TRUE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/* L2 cache lines are 32 bytes in Milkymist SoC */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t ie; - uint32_t epc; -} Context_Control; - -/** - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t ra; - uint32_t ba; - uint32_t ea; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if 0 -extern Context_Control_fp _CPU_Null_fp_context; -#endif - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * The LM32 architecture manual simply states: "All memory accesses must be - * aligned to the size of the access", and there is no hardware support - * whatsoever for 64-bit numbers. - * (lm32_archman.pdf, July 2009, p. 15) - */ -#define CPU_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. - * - * - * Port Specific Information: - * - * Stack is software-managed - */ -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - lm32_disable_interrupts( _isr_cookie ); - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - lm32_enable_interrupts( _isr_cookie ); - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - lm32_flash_interrupts( _isr_cookie ); - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & 0x0001 ) != 0; -} - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \ - } - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -extern char _gp[]; - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - do { \ - uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - (void) _isr; /* avoid warning for being unused */ \ - (_the_context)->gp = (uint32_t)_gp; \ - (_the_context)->fp = (uint32_t)_stack; \ - (_the_context)->sp = (uint32_t)_stack; \ - (_the_context)->ra = (uint32_t)(_entry_point); \ - } while ( 0 ) - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) -#if 0 - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** @} */ - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -static inline uint16_t CPU_swap_u16(uint16_t v) -{ - return v << 8 | v >> 8; -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h b/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h deleted file mode 100644 index 3909c1d608..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/lm32/rtems/score/cpuatomic.h b/cpukit/score/cpu/lm32/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/lm32/rtems/score/cpuimpl.h b/cpukit/score/cpu/lm32/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/lm32/rtems/score/lm32.h b/cpukit/score/cpu/lm32/rtems/score/lm32.h deleted file mode 100644 index e8fecdf2f6..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/lm32.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - * @file - * - * @brief LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the NO CPU port. - */ -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Jukka Pietarinen , 2008, - * Micro-Research Finland Oy - */ - -#ifndef _RTEMS_SCORE_LM32_H -#define _RTEMS_SCORE_LM32_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define LM32_HAS_FPU 0 - -#elif defined(__lm32__) - -#define CPU_MODEL_NAME "lm32" -#define LM32_HAS_FPU 0 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "LM32" - -#ifdef __cplusplus -} -#endif - -#define lm32_read_interrupts( _ip) \ - __asm__ volatile ("rcsr %0, ip":"=r"(_ip)); - -#define lm32_disable_interrupts( _level ) \ - do { register uint32_t ie; \ - __asm__ volatile ("rcsr %0,ie":"=r"(ie)); \ - (_level) = ie; \ - ie &= (~0x0001); \ - __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \ - } while (0) - -#define lm32_enable_interrupts( _level ) \ - __asm__ volatile ("wcsr ie,%0"::"r"(_level)); - -#define lm32_flash_interrupts( _level ) \ - do { register uint32_t ie; \ - __asm__ volatile ("wcsr ie,%0"::"r"(_level)); \ - ie = (_level) & (~0x0001); \ - __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \ - } while (0) - -#define lm32_interrupt_unmask( _mask ) \ - do { register uint32_t im; \ - __asm__ volatile ("rcsr %0,im":"=r"(im)); \ - im |= _mask; \ - __asm__ volatile ("wcsr im,%0"::"r"(im)); \ - } while (0) - -#define lm32_interrupt_mask( _mask ) \ - do { register uint32_t im; \ - __asm__ volatile ("rcsr %0,im":"=r"(im)); \ - im &= ~(_mask); \ - __asm__ volatile ("wcsr im,%0"::"r"(im)); \ - } while (0) - -#define lm32_interrupt_ack( _mask ) \ - do { register uint32_t ip = _mask; \ - __asm__ volatile ("wcsr ip,%0"::"r"(ip)); \ - } while (0) - -#endif /* _RTEMS_SCORE_LM32_H */ diff --git a/cpukit/score/cpu/lm32/rtems/score/types.h b/cpukit/score/cpu/lm32/rtems/score/types.h deleted file mode 100644 index c3d8666de4..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Lattice lm32 processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Jukka Pietarinen , 2008, - * Micro-Research Finland Oy - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m32c/Makefile.am b/cpukit/score/cpu/m32c/Makefile.am index 993cf4b4d3..22bec7fce0 100644 --- a/cpukit/score/cpu/m32c/Makefile.am +++ b/cpukit/score/cpu/m32c/Makefile.am @@ -1,18 +1,5 @@ include $(top_srcdir)/automake/compile.am -include_HEADERS = varvects.h - -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/m32c.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c cpu_asm.c context_switch.S context_init.c \ varvects.S @@ -20,5 +7,5 @@ libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += m32c-exception-frame-print.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/m32c/headers.am b/cpukit/score/cpu/m32c/headers.am new file mode 100644 index 0000000000..f67d070b88 --- /dev/null +++ b/cpukit/score/cpu/m32c/headers.am @@ -0,0 +1,17 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += include/varvects.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/m32c.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/m32c/include/rtems/asm.h b/cpukit/score/cpu/m32c/include/rtems/asm.h new file mode 100644 index 0000000000..f3f244d066 --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/asm.h @@ -0,0 +1,124 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-2006. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +/** + * @see __USER_LABEL_PREFIX__ + * + * This symbol is prefixed to all register names. + */ +#define __REGISTER_PREFIX__ +#endif + +#include + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** + * This macro is used to denote the beginning of a data declaration section. + */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * NOTE: This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * @see PUBLIC(sym) .globl SYM (sym) + */ +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/m32c/include/rtems/score/cpu.h b/cpukit/score/cpu/m32c/include/rtems/score/cpu.h new file mode 100644 index 0000000000..af1c3412ea --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/score/cpu.h @@ -0,0 +1,985 @@ +/** + * @file + * + * @brief M32C CPU Dependent Source + */ + +/* + * This include file contains information pertaining to the XXX + * processor. + * + * @note This file is part of a porting template that is intended + * to be used as the starting point when porting RTEMS to a new + * CPU family. The following needs to be done when using this as + * the starting point for a new port: + * + * + Anywhere there is an XXX, it should be replaced + * with information about the CPU family being ported to. + * + * + At the end of each comment section, there is a heading which + * says "Port Specific Information:". When porting to RTEMS, + * add CPU family specific information in this section + */ + +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +#define RTEMS_USE_16_BIT_OBJECT + +/** + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +/** + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE + +/** + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/** + * @def CPU_HARDWARE_FP + * + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "M32C_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? + * + * This feature conditional is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if ( M32C_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif +#define CPU_SOFTWARE_FP FALSE + +#define CPU_CONTEXT_FP_SIZE 0 + +/** + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPUs in which this option has been used are the + * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and + * gcc both implicitly used the floating point registers to perform + * integer multiplies. Similarly, the PowerPC port of gcc has been + * seen to allocate floating point local variables and touch the FPU + * even when the flow through a subroutine (like vfprintf()) might + * not use floating point formats. + * + * If a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALL_TASKS_ARE_FP TRUE + +/** + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine @ref _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * @ref _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_GROWS_UP TRUE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 2 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/** + * @ingroup CPUInterrupt + * + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* may need to put some structures here. */ + +/** + * @defgroup CPUContext Processor Dependent Context Management + * + * From the highest level viewpoint, there are 2 types of context to save. + * + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +/**@{**/ + +/** + * @ingroup Management + * + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ +typedef struct { + /** This will contain the stack pointer. */ + uint32_t sp; + /** This will contain the frame base pointer. */ + uint32_t fb; +} Context_Control; + +/** + * @ingroup Management + * + * This macro returns the stack pointer associated with @a _context. + * + * @param[in] _context is the thread context area to access + * + * @return This method returns the stack pointer. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->sp + +/** + * @ingroup Management + * + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ +typedef struct { + /** + * This field is a hint that a port will have a number of integer + * registers that need to be saved when an interrupt occurs or + * when a context switch occurs at the end of an ISR. + */ + uint32_t special_interrupt_register; +} CPU_Interrupt_frame; + +/** @} */ + +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in @ref _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * NOTE: These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + * + */ +/**@{**/ + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* XXX: if needed, put more variables here */ + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/** + * This defines the number of entries in the @ref _ISR_Vector_table managed + * by RTEMS. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +/** This defines the highest interrupt vector number for this port. */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/** + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable @a _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** @} */ + +/** + * @ingroup CPUContext + * + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_MINIMUM_SIZE (2048L) + +#ifdef __m32cm_cpu__ + #define CPU_SIZEOF_POINTER 4 +#else + #define CPU_SIZEOF_POINTER 2 +#endif + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALIGNMENT 2 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HEAP_ALIGNMENT 4 + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by @ref CPU_ALIGNMENT. If the + * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be + * set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_ALIGNMENT 0 + +/* + * ISR handler macros + */ + +/** + * @ingroup CPUInterrupt + * + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Initialize_vectors() + +/** + * @ingroup CPUInterrupt + * + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in @a _isr_cookie. + * + * @param[out] _isr_cookie will contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + int _flg; \ + m32c_get_flg( _flg ); \ + _isr_cookie = _flg; \ + __asm__ volatile( "fclr I" ); \ + } while(0) + +/** + * @ingroup CPUInterrupt + * + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * @a _isr_cookie is not modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Enable(_isr_cookie) \ + do { \ + int _flg = (int) (_isr_cookie); \ + m32c_set_flg( _flg ); \ + } while(0) + +/** + * @ingroup CPUInterrupt + * + * This temporarily restores the interrupt to @a _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Flash( _isr_cookie ) \ + do { \ + int _flg = (int) (_isr_cookie); \ + m32c_set_flg( _flg ); \ + __asm__ volatile( "fclr I" ); \ + } while(0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & 0x40 ) != 0; +} + +/** + * @ingroup CPUInterrupt + * + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + *This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Set_level( _new_level ) \ + do { \ + if (_new_level) __asm__ volatile( "fclr I" ); \ + else __asm__ volatile( "fset I" ); \ + } while(0) + +/** + * @ingroup CPUInterrupt + * + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * NOTE: This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/** + * @ingroup CPUContext + * + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * @param[in] _the_context is the context structure to be initialized + * @param[in] _stack_base is the lowest physical address of this task's stack + * @param[in] _size is the size of this task's stack + * @param[in] _isr is the interrupt disable level + * @param[in] _entry_point is the thread's entry point. This is + * always @a _Thread_Handler + * @param[in] _is_fp is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * @param[in] tls_area is the thread-local storage (TLS) area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + size_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/** + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. For many ports, simply adding a label to the restore path + * of @ref _CPU_Context_switch will work. On other ports, it may be + * possibly to load a few arguments and jump to the restore path. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_Restart_self( + Context_Control *the_context +) RTEMS_NO_RETURN; + +/** + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * @a _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other floating point context save/restore models include: + * -# not doing anything, and + * -# putting a "null FP status word" in the correct place in the FP context. + * + * @param[in] _destination is the floating point context area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Fatal_halt( _source, _error ) \ + { \ + } + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/** + * This routine performs CPU dependent initialization. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Initialize(void); + +/** + * @ingroup CPUInterrupt + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the raw ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the RTEMS ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Install_interrupt_stack( void ); + +/** + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/** + * @ingroup CPUContext + * + * This routine switches from the run context to the heir context. + * + * @param[in] run points to the context of the currently executing task + * @param[in] heir points to the context of the heir task + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * @ingroup CPUContext + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. + * + * @param[in] new_context points to the context to be restored. + * + * NOTE: May be unnecessary to reload some registers. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @ingroup CPUEndian + * + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +} + +/** + * @ingroup CPUEndian + * + * This routine swaps a 16 bir quantity. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + */ +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/m32c/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32c/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..451c022d75 --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/score/cpu_asm.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @brief M32C CPU Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +#include + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/m32c/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/m32c/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/m32c/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/m32c/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/m32c/include/rtems/score/m32c.h b/cpukit/score/cpu/m32c/include/rtems/score/m32c.h new file mode 100644 index 0000000000..e1936fdcfb --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/score/m32c.h @@ -0,0 +1,76 @@ +/** + * @file + * + * @brief M32C Set up Basic CPU Dependency Settings Based on Compiler Settings + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specified to the NO CPU port. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_NO_CPU_H +#define _RTEMS_SCORE_NO_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the NO CPU family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +#if defined(rtems_multilib) +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#define CPU_MODEL_NAME "rtems_multilib" +#define NOCPU_HAS_FPU 1 + +#elif defined(__m32c__) + +#define CPU_MODEL_NAME "m32c" +#define M32C_HAS_FPU 0 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "m32c" + +#define m32c_get_flg( _flg ) \ + __asm__ volatile( "stc flg, %0" : "=r" (_flg)) + +#define m32c_set_flg( _flg ) \ + __asm__ volatile( "ldc %1, flg" : "=r" (_flg) : "r" (_flg) ) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_NO_CPU_H */ diff --git a/cpukit/score/cpu/m32c/include/rtems/score/types.h b/cpukit/score/cpu/m32c/include/rtems/score/types.h new file mode 100644 index 0000000000..99d8297143 --- /dev/null +++ b/cpukit/score/cpu/m32c/include/rtems/score/types.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @brief M32C CPU Type Definitions + * + * This include file contains type definitions pertaining to the Intel + * m32c processor family. + */ + +/* + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef unsigned long CPU_Uint32ptr; + +/** This defines the return type for an ISR entry point. */ +typedef void m32c_isr; + +/** This defines the prototype for an ISR entry point. */ +typedef m32c_isr ( *m32c_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/m32c/include/varvects.h b/cpukit/score/cpu/m32c/include/varvects.h new file mode 100644 index 0000000000..7168482b54 --- /dev/null +++ b/cpukit/score/cpu/m32c/include/varvects.h @@ -0,0 +1,58 @@ +/** + * @file + * + * @brief M32C Built-in Variable Vector Table Interface + * + * This file defines the interface to the built-in variable vector + * table in R8C/M16C/M32C chips. + */ + +/* + * Copyright (c) 2008 Red Hat Incorporated. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * The name of Red Hat Incorporated may not be used to endorse + * or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _VARVECTS_H_ +#define _VARVECTS_H_ + +typedef void (*_m32c_interrupt_func)(void) __attribute__((mode(SI))); +extern _m32c_interrupt_func _var_vects[]; + +#if defined(__r8c_cpu__) || defined (__m16c_cpu__) + +#define _set_var_vect(f,n) \ + { __asm__ ("mov.w #%%lo16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4)); \ + __asm__ ("mov.w #%%hi16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4+2)); } + +#else + +#define _set_var_vect(f,n) \ + _var_vects[n] = f + +#endif +#endif diff --git a/cpukit/score/cpu/m32c/preinstall.am b/cpukit/score/cpu/m32c/preinstall.am deleted file mode 100644 index 3e12ca477d..0000000000 --- a/cpukit/score/cpu/m32c/preinstall.am +++ /dev/null @@ -1,62 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/varvects.h: varvects.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/varvects.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/varvects.h - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/m32c.h: rtems/score/m32c.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/m32c.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/m32c.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/m32c/rtems/asm.h b/cpukit/score/cpu/m32c/rtems/asm.h deleted file mode 100644 index f3f244d066..0000000000 --- a/cpukit/score/cpu/m32c/rtems/asm.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * @see __USER_LABEL_PREFIX__ - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** - * This macro is used to denote the beginning of a data declaration section. - */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @see PUBLIC(sym) .globl SYM (sym) - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h b/cpukit/score/cpu/m32c/rtems/score/cpu.h deleted file mode 100644 index af1c3412ea..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpu.h +++ /dev/null @@ -1,985 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Dependent Source - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -#define RTEMS_USE_16_BIT_OBJECT - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "M32C_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( M32C_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_CONTEXT_FP_SIZE 0 - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 2 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/** - * @ingroup CPUInterrupt - * - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * @ingroup Management - * - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - /** This will contain the stack pointer. */ - uint32_t sp; - /** This will contain the frame base pointer. */ - uint32_t fb; -} Context_Control; - -/** - * @ingroup Management - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * @ingroup Management - * - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** - * This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - * - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** This defines the highest interrupt vector number for this port. */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (2048L) - -#ifdef __m32cm_cpu__ - #define CPU_SIZEOF_POINTER 4 -#else - #define CPU_SIZEOF_POINTER 2 -#endif - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 2 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - int _flg; \ - m32c_get_flg( _flg ); \ - _isr_cookie = _flg; \ - __asm__ volatile( "fclr I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable(_isr_cookie) \ - do { \ - int _flg = (int) (_isr_cookie); \ - m32c_set_flg( _flg ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - int _flg = (int) (_isr_cookie); \ - m32c_set_flg( _flg ); \ - __asm__ volatile( "fclr I" ); \ - } while(0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & 0x40 ) != 0; -} - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - *This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - do { \ - if (_new_level) __asm__ volatile( "fclr I" ); \ - else __asm__ volatile( "fset I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h deleted file mode 100644 index 451c022d75..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/m32c/rtems/score/cpuatomic.h b/cpukit/score/cpu/m32c/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/m32c/rtems/score/cpuimpl.h b/cpukit/score/cpu/m32c/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/m32c/rtems/score/m32c.h b/cpukit/score/cpu/m32c/rtems/score/m32c.h deleted file mode 100644 index e1936fdcfb..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/m32c.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * @file - * - * @brief M32C Set up Basic CPU Dependency Settings Based on Compiler Settings - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the NO CPU port. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_NO_CPU_H -#define _RTEMS_SCORE_NO_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define NOCPU_HAS_FPU 1 - -#elif defined(__m32c__) - -#define CPU_MODEL_NAME "m32c" -#define M32C_HAS_FPU 0 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "m32c" - -#define m32c_get_flg( _flg ) \ - __asm__ volatile( "stc flg, %0" : "=r" (_flg)) - -#define m32c_set_flg( _flg ) \ - __asm__ volatile( "ldc %1, flg" : "=r" (_flg) : "r" (_flg) ) - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_NO_CPU_H */ diff --git a/cpukit/score/cpu/m32c/rtems/score/types.h b/cpukit/score/cpu/m32c/rtems/score/types.h deleted file mode 100644 index 99d8297143..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/types.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * m32c processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -/** This defines the return type for an ISR entry point. */ -typedef void m32c_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef m32c_isr ( *m32c_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m32c/varvects.h b/cpukit/score/cpu/m32c/varvects.h deleted file mode 100644 index 7168482b54..0000000000 --- a/cpukit/score/cpu/m32c/varvects.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file - * - * @brief M32C Built-in Variable Vector Table Interface - * - * This file defines the interface to the built-in variable vector - * table in R8C/M16C/M32C chips. - */ - -/* - * Copyright (c) 2008 Red Hat Incorporated. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * The name of Red Hat Incorporated may not be used to endorse - * or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _VARVECTS_H_ -#define _VARVECTS_H_ - -typedef void (*_m32c_interrupt_func)(void) __attribute__((mode(SI))); -extern _m32c_interrupt_func _var_vects[]; - -#if defined(__r8c_cpu__) || defined (__m16c_cpu__) - -#define _set_var_vect(f,n) \ - { __asm__ ("mov.w #%%lo16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4)); \ - __asm__ ("mov.w #%%hi16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4+2)); } - -#else - -#define _set_var_vect(f,n) \ - _var_vects[n] = f - -#endif -#endif diff --git a/cpukit/score/cpu/m68k/Makefile.am b/cpukit/score/cpu/m68k/Makefile.am index 04eebcba85..68fd3a253a 100644 --- a/cpukit/score/cpu/m68k/Makefile.am +++ b/cpukit/score/cpu/m68k/Makefile.am @@ -3,26 +3,10 @@ include $(top_srcdir)/automake/compile.am noinst_LIBRARIES = libscorecpu.a libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_m68kdir = $(includedir)/rtems/m68k -include_rtems_m68k_HEADERS = rtems/m68k/m68302.h -include_rtems_m68k_HEADERS += rtems/m68k/m68360.h -include_rtems_m68k_HEADERS += rtems/m68k/qsm.h -include_rtems_m68k_HEADERS += rtems/m68k/sim.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/m68k.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - libscorecpu_a_SOURCES = cpu.c cpu_asm.S libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += m68k-exception-frame-print.c libscorecpu_a_SOURCES += __m68k_read_tp.c -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/m68k/headers.am b/cpukit/score/cpu/m68k/headers.am new file mode 100644 index 0000000000..e02fad3906 --- /dev/null +++ b/cpukit/score/cpu/m68k/headers.am @@ -0,0 +1,24 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_m68kdir = $(includedir)/rtems/m68k +include_rtems_m68k_HEADERS = +include_rtems_m68k_HEADERS += include/rtems/m68k/m68302.h +include_rtems_m68k_HEADERS += include/rtems/m68k/m68360.h +include_rtems_m68k_HEADERS += include/rtems/m68k/qsm.h +include_rtems_m68k_HEADERS += include/rtems/m68k/sim.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/m68k.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/m68k/include/machine/elf_machdep.h b/cpukit/score/cpu/m68k/include/machine/elf_machdep.h new file mode 100644 index 0000000000..9a987c69b5 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/machine/elf_machdep.h @@ -0,0 +1,47 @@ +/* $NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $ */ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF32_MACHDEP_ID_CASES \ + case EM_68K: \ + break; + +#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ +#define ELF64_MACHDEP_ID_CASES \ + /* no 64-bit ELF machine types supported */ + +#define ELF32_MACHDEP_ID EM_68K + +/* + * Machine-dependent ELF flags. These are defined by the GNU tools. + */ +#define EF_CPU32 0x00810000 +#define EF_M68000 0x01000000 + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +/* m68k relocation types */ +#define R_68K_NONE 0 +#define R_68K_32 1 +#define R_68K_16 2 +#define R_68K_8 3 +#define R_68K_PC32 4 +#define R_68K_PC16 5 +#define R_68K_PC8 6 +#define R_68K_GOT32 7 +#define R_68K_GOT16 8 +#define R_68K_GOT8 9 +#define R_68K_GOT32O 10 +#define R_68K_GOT16O 11 +#define R_68K_GOT8O 12 +#define R_68K_PLT32 13 +#define R_68K_PLT16 14 +#define R_68K_PLT8 15 +#define R_68K_PLT32O 16 +#define R_68K_PLT16O 17 +#define R_68K_PLT8O 18 +#define R_68K_COPY 19 +#define R_68K_GLOB_DAT 20 +#define R_68K_JMP_SLOT 21 +#define R_68K_RELATIVE 22 + +#define R_TYPE(name) __CONCAT(R_68K_,name) diff --git a/cpukit/score/cpu/m68k/include/rtems/asm.h b/cpukit/score/cpu/m68k/include/rtems/asm.h new file mode 100644 index 0000000000..cbd2a7f8b2 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/asm.h @@ -0,0 +1,152 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) + +#define d0 REG (d0) +#define d1 REG (d1) +#define d2 REG (d2) +#define d3 REG (d3) +#define d4 REG (d4) +#define d5 REG (d5) +#define d6 REG (d6) +#define d7 REG (d7) +#define a0 REG (a0) +#define a1 REG (a1) +#define a2 REG (a2) +#define a3 REG (a3) +#define a4 REG (a4) +#define a5 REG (a5) +#define a6 REG (a6) +#define a7 REG (a7) +#define sp REG (sp) + +#define msp REG (msp) +#define usp REG (usp) +#define isp REG (isp) +#define sr REG (sr) +#define vbr REG (vbr) +#define dfc REG (dfc) +#define sfc REG (sfc) + +/* mcf52xx special regs */ +#define cacr REG (cacr) +#define acr0 REG (acr0) +#define acr1 REG (acr1) +#define rambar0 REG (rambar0) +#define mbar REG (mbar) + +/* additional v4e special regs */ +#define rambar1 REG (rambar1) +#define macsr REG (macsr) +#define acc0 REG (acc0) +#define acc1 REG (acc1) +#define acc2 REG (acc2) +#define acc3 REG (acc3) +#define accext01 REG (accext01) +#define accext23 REG (accext23) +#define mask REG (mask) + + +#define fp0 REG (fp0) +#define fp1 REG (fp1) +#define fp2 REG (fp2) +#define fp3 REG (fp3) +#define fp4 REG (fp4) +#define fp5 REG (fp5) +#define fp6 REG (fp6) +#define fp7 REG (fp7) + +#define fpc REG (fpc) +#define fpi REG (fpi) +#define fps REG (fps) +#define fpsr REG (fpsr) + + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA .data +#define END_DATA +#define BEGIN_BSS .bss +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/m68k/include/rtems/m68k/m68302.h b/cpukit/score/cpu/m68k/include/rtems/m68k/m68302.h new file mode 100644 index 0000000000..acf55f50c5 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/m68k/m68302.h @@ -0,0 +1,659 @@ +/** + * @file + * + * @brief Definitions for Motorola MC68302 Processor + * + * Section references in this file refer to revision 2 of Motorola's + * "MC68302 Integrated Multiprotocol Processor User's Manual". + * (Motorola document MC68302UM/AD REV 2.) + * + * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k + * on 17 February, 1993. + */ + +/* + * COPYRIGHT 1995 David W. Glessner. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. Redistribution of source code and documentation must retain + * the above copyright notice, this list of conditions and the + * following disclaimer. + * 2. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * This software is provided "AS IS" without warranty of any kind, + * either expressed or implied, including, but not limited to, the + * implied warranties of merchantability, title and fitness for a + * particular purpose. + * + *------------------------------------------------------------------ + */ + +#ifndef _RTEMS_M68K_M68302_H +#define _RTEMS_M68K_M68302_H + +/* + * BAR - Base Address Register + * Section 2.7 + */ +#define M302_BAR (*((volatile uint16_t *) 0xf2)) + +/* + * SCR - System Control Register + * Section 3.8.1 + */ +#define M302_SCR (*((volatile uint32_t *) 0xf4)) +/* + * SCR bits + */ +#define RBIT_SCR_IPA 0x08000000 +#define RBIT_SCR_HWT 0x04000000 +#define RBIT_SCR_WPV 0x02000000 +#define RBIT_SCR_ADC 0x01000000 + +#define RBIT_SCR_ERRE 0x00400000 +#define RBIT_SCR_VGE 0x00200000 +#define RBIT_SCR_WPVE 0x00100000 +#define RBIT_SCR_RMCST 0x00080000 +#define RBIT_SCR_EMWS 0x00040000 +#define RBIT_SCR_ADCE 0x00020000 +#define RBIT_SCR_BCLM 0x00010000 + +#define RBIT_SCR_FRZW 0x00008000 +#define RBIT_SCR_FRZ2 0x00004000 +#define RBIT_SCR_FRZ1 0x00002000 +#define RBIT_SCR_SAM 0x00001000 +#define RBIT_SCR_HWDEN 0x00000800 +#define RBIT_SCR_HWDCN2 0x00000400 +#define RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */ +#define RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */ + +#define RBIT_SCR_LPREC 0x00000080 +#define RBIT_SCR_LPP16 0x00000040 +#define RBIT_SCR_LPEN 0x00000020 +#define RBIT_SCR_LPCLKDIV 0x0000001f + + +/* + * 68000 interrupt and trap vector numbers + */ +#define M68K_IVEC_BUS_ERROR 2 +#define M68K_IVEC_ADDRESS_ERROR 3 +#define M68K_IVEC_ILLEGAL_OPCODE 4 +#define M68K_IVEC_ZERO_DIVIDE 5 +#define M68K_IVEC_CHK 6 +#define M68K_IVEC_TRAPV 7 +#define M68K_IVEC_PRIVILEGE 8 +#define M68K_IVEC_TRACE 9 +#define M68K_IVEC_LINE_A 10 +#define M68K_IVEC_LINE_F 11 +/* Unassigned, Reserved 12-14 */ +#define M68K_IVEC_UNINITIALIZED_INT 15 +/* Unassigned, Reserved 16-23 */ +#define M68K_IVEC_SPURIOUS_INT 24 + +#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 +#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 +#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 +#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 +#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 +#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 +#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 + +#define M68K_IVEC_TRAP0 32 +#define M68K_IVEC_TRAP1 33 +#define M68K_IVEC_TRAP2 34 +#define M68K_IVEC_TRAP3 35 +#define M68K_IVEC_TRAP4 36 +#define M68K_IVEC_TRAP5 37 +#define M68K_IVEC_TRAP6 38 +#define M68K_IVEC_TRAP7 39 +#define M68K_IVEC_TRAP8 40 +#define M68K_IVEC_TRAP9 41 +#define M68K_IVEC_TRAP10 42 +#define M68K_IVEC_TRAP11 43 +#define M68K_IVEC_TRAP12 44 +#define M68K_IVEC_TRAP13 45 +#define M68K_IVEC_TRAP14 46 +#define M68K_IVEC_TRAP15 47 +/* + * Unassigned, Reserved 48-59 + * + * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). + */ + +/* + * MC68302 Interrupt Vectors + * Section 3.2 + */ +enum m68302_ivec_e { + M302_IVEC_ERR =0, + M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ + M302_IVEC_SMC2 =2, + M302_IVEC_SMC1 =3, + M302_IVEC_TIMER3 =4, + M302_IVEC_SCP =5, + M302_IVEC_TIMER2 =6, + M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ + M302_IVEC_SCC3 =8, + M302_IVEC_TIMER1 =9, + M302_IVEC_SCC2 =10, + M302_IVEC_IDMA =11, + M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ + M302_IVEC_SCC1 =13, + M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ + M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ + M302_IVEC_IRQ1 =17, /* External Device */ + M302_IVEC_IRQ6 =22, /* External Device */ + M302_IVEC_IRQ7 =23 /* External Device */ +}; + + +/* + * GIMR - Global Interrupt Mode Register + * Section 3.2.5.1 + */ +#define RBIT_GIMR_MOD (1<<15) +#define RBIT_GIMR_IV7 (1<<14) +#define RBIT_GIMR_IV6 (1<<13) +#define RBIT_GIMR_IV1 (1<<12) +#define RBIT_GIMR_ET7 (1<<10) +#define RBIT_GIMR_ET6 (1<<9) +#define RBIT_GIMR_ET1 (1<<8) +#define RBIT_GIMR_VECTOR (7<<5) + +/* + * IPR - Interrupt Pending Register (Section 3.2.5.2) + * IMR - Interrupt Mask Register (Section 3.2.5.3) + * ISR - Interrupt In-Service Register (Section 3.2.5.4) + */ +#define RBIT_IPR_PB11 (1<<15) +#define RBIT_IPR_PB10 (1<<14) +#define RBIT_IPR_SCC1 (1<<13) +#define RBIT_IPR_SDMA (1<<12) +#define RBIT_IPR_IDMA (1<<11) +#define RBIT_IPR_SCC2 (1<<10) +#define RBIT_IPR_TIMER1 (1<<9) +#define RBIT_IPR_SCC3 (1<<8) +#define RBIT_IPR_PB9 (1<<7) +#define RBIT_IPR_TIMER2 (1<<6) +#define RBIT_IPR_SCP (1<<5) +#define RBIT_IPR_TIMER3 (1<<4) +#define RBIT_IPR_SMC1 (1<<3) +#define RBIT_IPR_SMC2 (1<<2) +#define RBIT_IPR_PB8 (1<<1) +#define RBIT_IPR_ERR (1<<0) + +#define RBIT_ISR_PB11 (1<<15) +#define RBIT_ISR_PB10 (1<<14) +#define RBIT_ISR_SCC1 (1<<13) +#define RBIT_ISR_SDMA (1<<12) +#define RBIT_ISR_IDMA (1<<11) +#define RBIT_ISR_SCC2 (1<<10) +#define RBIT_ISR_TIMER1 (1<<9) +#define RBIT_ISR_SCC3 (1<<8) +#define RBIT_ISR_PB9 (1<<7) +#define RBIT_ISR_TIMER2 (1<<6) +#define RBIT_ISR_SCP (1<<5) +#define RBIT_ISR_TIMER3 (1<<4) +#define RBIT_ISR_SMC1 (1<<3) +#define RBIT_ISR_SMC2 (1<<2) +#define RBIT_ISR_PB8 (1<<1) + +#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ +#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ +#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ +#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ +#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ +#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ +#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ +#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ +#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ +#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ +#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ +#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ +#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ +#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ +#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ + + +/* + * DRAM Refresh + * Section 3.9 + * + * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 + * structures in the parameter RAM. + * + * Access to the DRAM registers can be accomplished by + * the following approach: + * + * volatile m302_DRAM_refresh_t *dram; + * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; + * + * Then simply use pointer references (e.g. dram->count = 3). + */ +typedef struct { + uint16_t dram_high; /* DRAM high address and FC */ + uint16_t dram_low; /* DRAM low address */ + uint16_t increment; /* increment step (bytes/row) */ + uint16_t count; /* RAM refresh cycle count (#rows) */ + uint16_t t_ptr_h; /* temporary refresh high addr & FC */ + uint16_t t_ptr_l; /* temporary refresh low address */ + uint16_t t_count; /* temporary refresh cycles count */ + uint16_t res; /* reserved */ +} m302_DRAM_refresh_t; + + +/* + * TMR - Timer Mode Register (for timers 1 and 2) + * Section 3.5.2.1 + */ +#define RBIT_TMR_ICLK_STOP (0<<1) +#define RBIT_TMR_ICLK_MASTER (1<<1) +#define RBIT_TMR_ICLK_MASTER16 (2<<1) +#define RBIT_TMR_ICLK_TIN (3<<1) + +#define RBIT_TMR_OM (1<<5) +#define RBIT_TMR_ORI (1<<4) +#define RBIT_TMR_FRR (1<<3) +#define RBIT_TMR_RST (1<<0) + + +/* + * TER - Timer Event Register (for timers 1 and 2) + * Section 3.5.2.5 + */ +#define RBIT_TER_REF (1<<1) /* Output Reference Event */ +#define RBIT_TER_CAP (1<<0) /* Capture Event */ + + +/* + * SCC Buffer Descriptors and Buffer Descriptors Table + * Section 4.5.5 + */ +typedef struct m302_SCC_bd { + uint16_t status; /* status and control */ + uint16_t length; /* data length */ + volatile uint8_t *buffer; /* data buffer pointer */ +} m302_SCC_bd_t; + +typedef struct { + m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ + m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ +} m302_SCC_bd_table_t; + + +/* + * SCC Parameter RAM (offset 0x080 from an SCC Base) + * Section 4.5.6 + * + * Each SCC parameter RAM area begins at offset 0x80 from each SCC base + * area (0x400, 0x500, or 0x600 from the dual-port RAM base). + * + * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific + * portion of the SCC parameter RAM. + */ +typedef struct { + uint8_t rfcr; /* Rx Function Code */ + uint8_t tfcr; /* Tx Function Code */ + uint16_t mrblr; /* Maximum Rx Buffer Length */ + uint16_t _rstate; /* Rx Internal State */ + uint8_t res2; + uint8_t rbd; /* Rx Internal Buffer Number */ + uint32_t _rdptr; /* Rx Internal Data Pointer */ + uint16_t _rcount; /* Rx Internal Byte Count */ + uint16_t _rtmp; /* Rx Temp */ + uint16_t _tstate; /* Tx Internal State */ + uint8_t res7; + uint8_t tbd; /* Tx Internal Buffer Number */ + uint32_t _tdptr; /* Tx Internal Data Pointer */ + uint16_t _tcount; /* Tx Internal Byte Count */ + uint16_t _ttmp; /* Tx Temp */ +} m302_SCC_parameters_t; + +/* + * UART-Specific SCC Parameter RAM + * Section 4.5.11.3 + */ +typedef struct { + uint16_t max_idl; /* Maximum IDLE Characters (rx) */ + uint16_t idlc; /* Temporary rx IDLE counter */ + uint16_t brkcr; /* Break Count Register (tx) */ + uint16_t parec; /* Receive Parity Error Counter */ + uint16_t frmec; /* Receive Framing Error Counter */ + uint16_t nosec; /* Receive Noise Counter */ + uint16_t brkec; /* Receive Break Condition Counter */ + uint16_t uaddr1; /* UART ADDRESS Character 1 */ + uint16_t uaddr2; /* UART ADDRESS Character 2 */ + uint16_t rccr; /* Receive Control Character Register */ + uint16_t character[8]; /* Control Characters 1 through 8*/ +} m302_SCC_UartSpecific_t; +/* + * This definition allows for the checking of receive buffers + * for errors. + */ + +#define RCV_ERR 0x003F + +/* + * UART receive buffer descriptor bit definitions. + * Section 4.5.11.14 + */ +#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ +#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ +#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ +#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ +#define RBIT_UART_BR (1<<5) /* break sequence was received */ +#define RBIT_UART_FR (1<<4) /* framing error was received */ +#define RBIT_UART_PR (1<<3) /* parity error was received */ +#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ +#define RBIT_UART_CD (1<<0) /* carrier detect lost */ +#define RBIT_UART_STATUS 0x003B /* all status bits */ + +/* + * UART transmit buffer descriptor bit definitions. + * Section 4.5.11.15 + */ +#define RBIT_UART_CR (1<<11) /* clear-to-send report + * this results in two idle bits + * between back-to-back frames + */ +#define RBIT_UART_A (1<<10) /* buffer contains address characters + * only valid in multidrop mode (UM0=1) + */ +#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ +#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ + +/* + * UART event register + * Section 4.5.11.16 + */ +#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ +#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ +#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ +#define M302_UART_EV_BRK (1<<4) /* break character was received */ +#define M302_UART_EV_CCR (1<<3) /* control character received */ +#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ +#define M302_UART_EV_RX (1<<0) /* buffer has been received */ + + +/* + * HDLC-Specific SCC Parameter RAM + * Section 4.5.12.3 + * + * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC + * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC + */ +typedef struct { + uint16_t rcrc_l; /* Temp Receive CRC Low */ + uint16_t rcrc_h; /* Temp Receive CRC High */ + uint16_t c_mask_l; /* CRC Mask Low */ + uint16_t c_mask_h; /* CRC Mask High */ + uint16_t tcrc_l; /* Temp Transmit CRC Low */ + uint16_t tcrc_h; /* Temp Transmit CRC High */ + + uint16_t disfc; /* Discard Frame Counter */ + uint16_t crcec; /* CRC Error Counter */ + uint16_t abtsc; /* Abort Sequence Counter */ + uint16_t nmarc; /* Nonmatching Address Received Cntr */ + uint16_t retrc; /* Frame Retransmission Counter */ + + uint16_t mflr; /* Maximum Frame Length Register */ + uint16_t max_cnt; /* Maximum_Length Counter */ + + uint16_t hmask; /* User Defined Frame Address Mask */ + uint16_t haddr1; /* User Defined Frame Address */ + uint16_t haddr2; /* " */ + uint16_t haddr3; /* " */ + uint16_t haddr4; /* " */ +} m302_SCC_HdlcSpecific_t; +/* + * HDLC receiver buffer descriptor bit definitions + * Section 4.5.12.10 + */ +#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ +#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ +#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ +#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ +#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ +#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ +#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ +#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ + +/* + * HDLC transmit buffer descriptor bit definitions + * Section 4.5.12.11 + */ +#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ +#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ +#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ +#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ +#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ +#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ +#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ + +/* + * HDLC event register bit definitions + * Section 4.5.12.12 + */ +#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ +#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ +#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ +#define RBIT_HDLC_TXE 0x10 /* transmit error */ +#define RBIT_HDLC_RXF 0x08 /* received frame */ +#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to + * lack of buffers + */ +#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ +#define RBIT_HDLC_RXB 0x01 /* received buffer */ + + + +typedef struct { + m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ + m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ + union { /* +09C Protocol-Specific Parm RAM */ + m302_SCC_UartSpecific_t uart; + m302_SCC_HdlcSpecific_t hdlc; + } prot; + uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */ +} m302_SCC_t; + + +/* + * Common SCC Registers + */ +typedef struct { + uint16_t res1; + uint16_t scon; /* SCC Configuration Register 4.5.2 */ + uint16_t scm; /* SCC Mode Register 4.5.3 */ + uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */ + uint8_t scce; /* SCC Event Register 4.5.8.1 */ + uint8_t res2; + uint8_t sccm; /* SCC Mask Register 4.5.8.2 */ + uint8_t res3; + uint8_t sccs; /* SCC Status Register 4.5.8.3 */ + uint8_t res4; + uint16_t res5; +} m302_SCC_Registers_t; + +/* + * SCON - SCC Configuration Register + * Section 4.5.2 + */ +#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) + * When set, the TXD driver is an + * open-drain output */ +#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ +#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ +#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ + +/* + * SCM - SCC Mode Register bit definitions + * Section 4.5.3 + * The parameter-specific mode bits occupy bits 15 through 6. + */ +#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ +#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ + + +/* + * Internal MC68302 Registers + * starts at offset 0x800 from dual-port RAM base + * Section 2.8 + */ +typedef struct { + /* offset +800 */ + uint16_t res0; + uint16_t cmr; /* IDMA Channel Mode Register */ + uint32_t sapr; /* IDMA Source Address Pointer */ + uint32_t dapr; /* IDMA Destination Address Pointer */ + uint16_t bcr; /* IDMA Byte Count Register */ + uint8_t csr; /* IDMA Channel Status Register */ + uint8_t res1; + uint8_t fcr; /* IDMA Function Code Register */ + uint8_t res2; + + /* offset +812 */ + uint16_t gimr; /* Global Interrupt Mode Register */ + uint16_t ipr; /* Interrupt Pending Register */ + uint16_t imr; /* Interrupt Mask Register */ + uint16_t isr; /* Interrupt In-Service Register */ + uint16_t res3; + uint16_t res4; + + /* offset +81e */ + uint16_t pacnt; /* Port A Control Register */ + uint16_t paddr; /* Port A Data Direction Register */ + uint16_t padat; /* Port A Data Register */ + uint16_t pbcnt; /* Port B Control Register */ + uint16_t pbddr; /* Port B Data Direction Register */ + uint16_t pbdat; /* Port B Data Register */ + uint16_t res5; + + /* offset +82c */ + uint16_t res6; + uint16_t res7; + + uint16_t br0; /* Base Register (CS0) */ + uint16_t or0; /* Option Register (CS0) */ + uint16_t br1; /* Base Register (CS1) */ + uint16_t or1; /* Option Register (CS1) */ + uint16_t br2; /* Base Register (CS2) */ + uint16_t or2; /* Option Register (CS2) */ + uint16_t br3; /* Base Register (CS3) */ + uint16_t or3; /* Option Register (CS3) */ + + /* offset +840 */ + uint16_t tmr1; /* Timer Unit 1 Mode Register */ + uint16_t trr1; /* Timer Unit 1 Reference Register */ + uint16_t tcr1; /* Timer Unit 1 Capture Register */ + uint16_t tcn1; /* Timer Unit 1 Counter */ + uint8_t res8; + uint8_t ter1; /* Timer Unit 1 Event Register */ + uint16_t wrr; /* Watchdog Reference Register */ + uint16_t wcn; /* Watchdog Counter */ + uint16_t res9; + uint16_t tmr2; /* Timer Unit 2 Mode Register */ + uint16_t trr2; /* Timer Unit 2 Reference Register */ + uint16_t tcr2; /* Timer Unit 2 Capture Register */ + uint16_t tcn2; /* Timer Unit 2 Counter */ + uint8_t resa; + uint8_t ter2; /* Timer Unit 2 Event Register */ + uint16_t resb; + uint16_t resc; + uint16_t resd; + + /* offset +860 */ + uint8_t cr; /* Command Register */ + uint8_t rese[0x1f]; + + /* offset +880, +890, +8a0 */ + m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ + + /* offset +8b0 */ + uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ + uint16_t simask; /* Serial Interface Mask Register */ + uint16_t simode; /* Serial Interface Mode Register */ +} m302_internalReg_t ; + + +/* + * MC68302 dual-port RAM structure. + * (Includes System RAM, Parameter RAM, and Internal Registers). + * Section 2.8 + */ +typedef struct { + uint8_t mem[0x240]; /* +000 User Data Memory */ + uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */ + m302_SCC_t scc1; /* +400 SCC1 */ + m302_SCC_t scc2; /* +500 SCC2 */ + m302_SCC_t scc3; /* +600 SCC3 */ + uint8_t res2[0x100]; /* +700 reserved, (not implemented) */ + m302_internalReg_t reg; /* +800 68302 Internal Registers */ +} m302_dualPortRAM_t; + +/* some useful defines the some of the registers above */ + + +/* ---- + MC68302 Chip Select Registers + p3-46 2nd Edition + + */ +#define BR_ENABLED 1 +#define BR_DISABLED 0 +#define BR_FC_NULL 0 +#define BR_READ_ONLY 0 +#define BR_READ_WRITE 2 +#define OR_DTACK_0 0x0000 +#define OR_DTACK_1 0x2000 +#define OR_DTACK_2 0x4000 +#define OR_DTACK_3 0x6000 +#define OR_DTACK_4 0x8000 +#define OR_DTACK_5 0xA000 +#define OR_DTACK_6 0xC000 +#define OR_DTACK_EXT 0xE000 +#define OR_SIZE_64K 0x1FE0 +#define OR_SIZE_128K 0x1FC0 +#define OR_SIZE_256K 0x1F80 +#define OR_SIZE_512K 0x1F00 +#define OR_SIZE_1M 0x1E00 +#define OR_SIZE_2M 0x1C00 +#define OR_MASK_RW 0x0000 +#define OR_NO_MASK_RW 0x0002 +#define OR_MASK_FC 0x0000 +#define OR_NO_MASK_FC 0x0001 + +#define MAKE_BR(base_address, enable, rw, fc) \ + ((base_address >> 11) | fc | rw | enable) + +#define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \ + (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask) + +#define __REG_CAT(r, n) r ## n +#define WRITE_BR(csel, base_address, enable, rw, fc) \ + __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc) +#define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \ + __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) + +/* ---- + MC68302 Watchdog Timer Enable Bit + + */ +#define WATCHDOG_ENABLE (1) +#define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0) +#define WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD) +#define DISABLE_WATCHDOG() (m302.reg.wrr = 0) + +/* + * Declare the variable that's used to reference the variables in + * the dual-port RAM. + */ +extern volatile m302_dualPortRAM_t m302; + +#endif diff --git a/cpukit/score/cpu/m68k/include/rtems/m68k/m68360.h b/cpukit/score/cpu/m68k/include/rtems/m68k/m68360.h new file mode 100644 index 0000000000..dc181d0cdf --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/m68k/m68360.h @@ -0,0 +1,899 @@ +/** + * @file + * + * @brief Definitions for Motorola MC68360 Processor + */ +/* + ************************************************************************** + ************************************************************************** + ** ** + ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) ** + ** ** + ** HARDWARE DECLARATIONS ** + ** ** + ** ** + ** Submitted By: ** + ** ** + ** W. Eric Norum ** + ** Saskatchewan Accelerator Laboratory ** + ** University of Saskatchewan ** + ** 107 North Road ** + ** Saskatoon, Saskatchewan, CANADA ** + ** S7N 5C6 ** + ** ** + ** eric@skatter.usask.ca ** + ** ** + ************************************************************************** + ************************************************************************** + */ + +#ifndef _RTEMS_M68K_M68360_H +#define _RTEMS_M68K_M68360_H + +/* + ************************************************************************* + * REGISTER SUBBLOCKS * + ************************************************************************* + */ + +/* + * Memory controller registers + */ +typedef struct m360MEMCRegisters_ { + unsigned long br; + unsigned long or; + unsigned long _pad[2]; +} m360MEMCRegisters_t; + +/* + * Serial Communications Controller registers + */ +typedef struct m360SCCRegisters_ { + unsigned long gsmr_l; + unsigned long gsmr_h; + unsigned short psmr; + unsigned short _pad0; + unsigned short todr; + unsigned short dsr; + unsigned short scce; + unsigned short _pad1; + unsigned short sccm; + unsigned char _pad2; + unsigned char sccs; + unsigned long _pad3[2]; +} m360SCCRegisters_t; + +/* + * Serial Management Controller registers + */ +typedef struct m360SMCRegisters_ { + unsigned short _pad0; + unsigned short smcmr; + unsigned short _pad1; + unsigned char smce; + unsigned char _pad2; + unsigned short _pad3; + unsigned char smcm; + unsigned char _pad4; + unsigned long _pad5; +} m360SMCRegisters_t; + + +/* + ************************************************************************* + * Miscellaneous Parameters * + ************************************************************************* + */ +typedef struct m360MiscParms_ { + unsigned short rev_num; + unsigned short _res1; + unsigned long _res2; + unsigned long _res3; +} m360MiscParms_t; + +/* + ************************************************************************* + * RISC Timers * + ************************************************************************* + */ +typedef struct m360TimerParms_ { + unsigned short tm_base; + unsigned short _tm_ptr; + unsigned short _r_tmr; + unsigned short _r_tmv; + unsigned long tm_cmd; + unsigned long tm_cnt; +} m360TimerParms_t; + +/* + * RISC Controller Configuration Register (RCCR) + * All other bits in this register are either reserved or + * used only with a Motorola-supplied RAM microcode packge. + */ +#define M360_RCCR_TIME (1<<15) /* Enable timer */ +#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ + +/* + * Command register + * Set up this register before issuing a M360_CR_OP_SET_TIMER command. + */ +#define M360_TM_CMD_V (1<<31) /* Set to enable timer */ +#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */ +#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ +#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ + +/* + ************************************************************************* + * DMA Controllers * + ************************************************************************* + */ +typedef struct m360IDMAparms_ { + unsigned short ibase; + unsigned short ibptr; + unsigned long _istate; + unsigned long _itemp; +} m360IDMAparms_t; + +/* + ************************************************************************* + * Serial Communication Controllers * + ************************************************************************* + */ +typedef struct m360SCCparms_ { + unsigned short rbase; + unsigned short tbase; + unsigned char rfcr; + unsigned char tfcr; + unsigned short mrblr; + unsigned long _rstate; + unsigned long _pad0; + unsigned short _rbptr; + unsigned short _pad1; + unsigned long _pad2; + unsigned long _tstate; + unsigned long _pad3; + unsigned short _tbptr; + unsigned short _pad4; + unsigned long _pad5; + unsigned long _rcrc; + unsigned long _tcrc; + union { + struct { + unsigned long _res0; + unsigned long _res1; + unsigned short max_idl; + unsigned short _idlc; + unsigned short brkcr; + unsigned short parec; + unsigned short frmec; + unsigned short nosec; + unsigned short brkec; + unsigned short brklen; + unsigned short uaddr[2]; + unsigned short _rtemp; + unsigned short toseq; + unsigned short character[8]; + unsigned short rccm; + unsigned short rccr; + unsigned short rlbc; + } uart; + struct { + unsigned long crc_p; + unsigned long crc_c; + } transparent; + + } un; +} m360SCCparms_t; + +typedef struct m360SCCENparms_ { + unsigned short rbase; + unsigned short tbase; + unsigned char rfcr; + unsigned char tfcr; + unsigned short mrblr; + unsigned long _rstate; + unsigned long _pad0; + unsigned short _rbptr; + unsigned short _pad1; + unsigned long _pad2; + unsigned long _tstate; + unsigned long _pad3; + unsigned short _tbptr; + unsigned short _pad4; + unsigned long _pad5; + unsigned long _rcrc; + unsigned long _tcrc; + union { + struct { + unsigned long _res0; + unsigned long _res1; + unsigned short max_idl; + unsigned short _idlc; + unsigned short brkcr; + unsigned short parec; + unsigned short frmec; + unsigned short nosec; + unsigned short brkec; + unsigned short brklen; + unsigned short uaddr[2]; + unsigned short _rtemp; + unsigned short toseq; + unsigned short character[8]; + unsigned short rccm; + unsigned short rccr; + unsigned short rlbc; + } uart; + struct { + unsigned long c_pres; + unsigned long c_mask; + unsigned long crcec; + unsigned long alec; + unsigned long disfc; + unsigned short pads; + unsigned short ret_lim; + unsigned short _ret_cnt; + unsigned short mflr; + unsigned short minflr; + unsigned short maxd1; + unsigned short maxd2; + unsigned short _maxd; + unsigned short dma_cnt; + unsigned short _max_b; + unsigned short gaddr1; + unsigned short gaddr2; + unsigned short gaddr3; + unsigned short gaddr4; + unsigned long _tbuf0data0; + unsigned long _tbuf0data1; + unsigned long _tbuf0rba0; + unsigned long _tbuf0crc; + unsigned short _tbuf0bcnt; + unsigned short paddr_h; + unsigned short paddr_m; + unsigned short paddr_l; + unsigned short p_per; + unsigned short _rfbd_ptr; + unsigned short _tfbd_ptr; + unsigned short _tlbd_ptr; + unsigned long _tbuf1data0; + unsigned long _tbuf1data1; + unsigned long _tbuf1rba0; + unsigned long _tbuf1crc; + unsigned short _tbuf1bcnt; + unsigned short _tx_len; + unsigned short iaddr1; + unsigned short iaddr2; + unsigned short iaddr3; + unsigned short iaddr4; + unsigned short _boff_cnt; + unsigned short taddr_h; + unsigned short taddr_m; + unsigned short taddr_l; + } ethernet; + struct { + unsigned long crc_p; + unsigned long crc_c; + } transparent; + } un; +} m360SCCENparms_t; + +/* + * Receive and transmit function code register bits + * These apply to the function code registers of all devices, not just SCC. + */ +#define M360_RFCR_MOT (1<<4) +#define M360_RFCR_DMA_SPACE 0x8 +#define M360_TFCR_MOT (1<<4) +#define M360_TFCR_DMA_SPACE 0x8 + +/* + ************************************************************************* + * Serial Management Controllers * + ************************************************************************* + */ +typedef struct m360SMCparms_ { + unsigned short rbase; + unsigned short tbase; + unsigned char rfcr; + unsigned char tfcr; + unsigned short mrblr; + unsigned long _rstate; + unsigned long _pad0; + unsigned short _rbptr; + unsigned short _pad1; + unsigned long _pad2; + unsigned long _tstate; + unsigned long _pad3; + unsigned short _tbptr; + unsigned short _pad4; + unsigned long _pad5; + union { + struct { + unsigned short max_idl; + unsigned short _pad0; + unsigned short brklen; + unsigned short brkec; + unsigned short brkcr; + unsigned short _r_mask; + } uart; + struct { + unsigned short _pad0[5]; + } transparent; + } un; +} m360SMCparms_t; + +/* + * Mode register + */ +#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */ +#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */ +#define M360_SMCMR_PARITY (1<<9) /* Enable parity */ +#define M360_SMCMR_EVEN (1<<8) /* Even parity */ +#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */ +#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */ +#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ +#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ +#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */ +#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */ +#define M360_SMCMR_REN (1<<0) /* Enable receiver */ + +/* + * Event and mask registers (SMCE, SMCM) + */ +#define M360_SMCE_BRK (1<<4) +#define M360_SMCE_BSY (1<<2) +#define M360_SMCE_TX (1<<1) +#define M360_SMCE_RX (1<<0) + +/* + ************************************************************************* + * Serial Peripheral Interface * + ************************************************************************* + */ +typedef struct m360SPIparms_ { + unsigned short rbase; + unsigned short tbase; + unsigned char rfcr; + unsigned char tfcr; + unsigned short mrblr; + unsigned long _rstate; + unsigned long _pad0; + unsigned short _rbptr; + unsigned short _pad1; + unsigned long _pad2; + unsigned long _tstate; + unsigned long _pad3; + unsigned short _tbptr; + unsigned short _pad4; + unsigned long _pad5; +} m360SPIparms_t; + +/* + * Mode register (SPMODE) + */ +#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */ +#define M360_SPMODE_CI (1<<13) /* Clock invert */ +#define M360_SPMODE_CP (1<<12) /* Clock phase */ +#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ +#define M360_SPMODE_REV (1<<10) /* Reverse data */ +#define M360_SPMODE_MASTER (1<<9) /* SPI is master */ +#define M360_SPMODE_EN (1<<8) /* Enable SPI */ +#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */ +#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */ + +/* + * Mode register (SPCOM) + */ +#define M360_SPCOM_STR (1<<7) /* Start transmit */ + +/* + * Event and mask registers (SPIE, SPIM) + */ +#define M360_SPIE_MME (1<<5) /* Multi-master error */ +#define M360_SPIE_TXE (1<<4) /* Tx error */ +#define M360_SPIE_BSY (1<<2) /* Busy condition*/ +#define M360_SPIE_TXB (1<<1) /* Tx buffer */ +#define M360_SPIE_RXB (1<<0) /* Rx buffer */ + +/* + ************************************************************************* + * SDMA (SCC, SMC, SPI) Buffer Descriptors * + ************************************************************************* + */ +typedef struct m360BufferDescriptor_ { + unsigned short status; + unsigned short length; + volatile void *buffer; +} m360BufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M360_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M360_BD_ADDRESS (1<<10) /* SCC UART */ +#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M360_BD_MISS (1<<8) /* Ethernet */ +#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M360_BD_LONG (1<<5) /* Ethernet */ +#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M360_BD_NONALIGNED (1<<4) /* Ethernet */ +#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M360_BD_SHORT (1<<3) /* Ethernet */ +#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */ +#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M360_BD_COLLISION (1<<0) /* Ethernet */ +#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */ +#define M360_BD_MASTER_ERROR (1<<0) /* SPI */ + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M360_BD_PAD (1<<14) /* Ethernet */ +#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M360_BD_TX_CRC (1<<10) /* Ethernet */ +#define M360_BD_DEFER (1<<9) /* Ethernet */ +#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ +#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M360_BD_CTS_LOST (1<<0) /* SCC UART */ + +/* + ************************************************************************* + * IDMA Buffer Descriptors * + ************************************************************************* + */ +typedef struct m360IDMABufferDescriptor_ { + unsigned short status; + unsigned short _pad; + unsigned long length; + void *source; + void *destination; +} m360IDMABufferDescriptor_t; + +/* + ************************************************************************* + * RISC Communication Processor Module Command Register (CR) * + ************************************************************************* + */ +#define M360_CR_RST (1<<15) /* Reset communication processor */ +#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ +#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ +#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ +#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ +#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ +#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */ +#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */ +#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ +#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ +#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ +#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */ +#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ +#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */ +#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ +#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */ +#define M360_CR_CHAN_SCC2 (4<<4) +#define M360_CR_CHAN_SPI (5<<4) +#define M360_CR_CHAN_TIMER (5<<4) +#define M360_CR_CHAN_SCC3 (8<<4) +#define M360_CR_CHAN_SMC1 (9<<4) +#define M360_CR_CHAN_IDMA1 (9<<4) +#define M360_CR_CHAN_SCC4 (12<<4) +#define M360_CR_CHAN_SMC2 (13<<4) +#define M360_CR_CHAN_IDMA2 (13<<4) +#define M360_CR_FLG (1<<0) /* Command flag */ + +/* + ************************************************************************* + * System Protection Control Register (SYPCR) * + ************************************************************************* + */ +#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */ +#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */ +#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */ +#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */ +#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */ +#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */ +#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */ +#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */ + +/* + ************************************************************************* + * Memory Control Registers * + ************************************************************************* + */ +#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */ +#define M360_GMR_RFEN (1<<23) /* Refresh enable */ +#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */ +#define M360_GMR_PGS(x) ((x)<<18) /* Page size */ +#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */ +#define M360_GMR_DPS_16BIT (1<<16) +#define M360_GMR_DPS_8BIT (2<<16) +#define M360_GMR_DPS_DSACK (3<<16) +#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */ +#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */ +#define M360_GMR_SYNC (1<<13) /* Synchronous external access */ +#define M360_GMR_EMWS (1<<12) /* External master wait state */ +#define M360_GMR_OPAR (1<<11) /* Odd parity */ +#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */ +#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */ +#define M360_GMR_NCS (1<<8) /* No CPU space */ +#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */ +#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */ +#define M360_GMR_GAMX (1<<5) /* Global address mux enable */ + +#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */ +#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */ +#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */ +#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */ +#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */ +#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */ +#define M360_MEMC_BR_WP (1<<1) /* Write Protect */ +#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */ +#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1) +#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */ +#define M360_MEMC_OR_4KB 0x0FFFF000 +#define M360_MEMC_OR_8KB 0x0FFFE000 +#define M360_MEMC_OR_16KB 0x0FFFC000 +#define M360_MEMC_OR_32KB 0x0FFF8000 +#define M360_MEMC_OR_64KB 0x0FFF0000 +#define M360_MEMC_OR_128KB 0x0FFE0000 +#define M360_MEMC_OR_256KB 0x0FFC0000 +#define M360_MEMC_OR_512KB 0x0FF80000 +#define M360_MEMC_OR_1MB 0x0FF00000 +#define M360_MEMC_OR_2MB 0x0FE00000 +#define M360_MEMC_OR_4MB 0x0FC00000 +#define M360_MEMC_OR_8MB 0x0F800000 +#define M360_MEMC_OR_16MB 0x0F000000 +#define M360_MEMC_OR_32MB 0x0E000000 +#define M360_MEMC_OR_64MB 0x0C000000 +#define M360_MEMC_OR_128MB 0x08000000 +#define M360_MEMC_OR_256MB 0x00000000 +#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */ +#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */ +#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */ +#define M360_MEMC_OR_32BIT (0<<1) /* Port size */ +#define M360_MEMC_OR_16BIT (1<<1) +#define M360_MEMC_OR_8BIT (2<<1) +#define M360_MEMC_OR_DSACK (3<<1) +#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */ + +/* + ************************************************************************* + * SI Mode Register (SIMODE) * + ************************************************************************* + */ +#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ +#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ +#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ +#define M360_SI_SMC2_BRG2 (1<<28) +#define M360_SI_SMC2_BRG3 (2<<28) +#define M360_SI_SMC2_BRG4 (3<<28) +#define M360_SI_SMC2_CLK5 (0<<28) +#define M360_SI_SMC2_CLK6 (1<<28) +#define M360_SI_SMC2_CLK7 (2<<28) +#define M360_SI_SMC2_CLK8 (3<<28) +#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ +#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ +#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ +#define M360_SI_SMC1_BRG2 (1<<12) +#define M360_SI_SMC1_BRG3 (2<<12) +#define M360_SI_SMC1_BRG4 (3<<12) +#define M360_SI_SMC1_CLK1 (0<<12) +#define M360_SI_SMC1_CLK2 (1<<12) +#define M360_SI_SMC1_CLK3 (2<<12) +#define M360_SI_SMC1_CLK4 (3<<12) + +/* + ************************************************************************* + * SDMA Configuration Register (SDMA) * + ************************************************************************* + */ +#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */ +#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */ +#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */ +#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */ +#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */ + +/* + ************************************************************************* + * Baud (sic) Rate Generators * + ************************************************************************* + */ +#define M360_BRG_RST (1<<17) /* Reset generator */ +#define M360_BRG_EN (1<<16) /* Enable generator */ +#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ +#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ +#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ +#define M360_BRG_ATB (1<<13) /* Autobaud */ +#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */ +#define M360_BRG_57600 (26<<1) +#define M360_BRG_38400 (40<<1) +#define M360_BRG_19200 (80<<1) +#define M360_BRG_9600 (162<<1) +#define M360_BRG_4800 (324<<1) +#define M360_BRG_2400 (650<<1) +#define M360_BRG_1200 (1301<<1) +#define M360_BRG_600 (2603<<1) +#define M360_BRG_300 ((324<<1) | 1) +#define M360_BRG_150 ((650<<1) | 1) +#define M360_BRG_75 ((1301<<1) | 1) + +/* + ************************************************************************* + * MC68360 DUAL-PORT RAM AND REGISTERS * + ************************************************************************* + */ +typedef struct m360_ { + /* + * Dual-port RAM + */ + unsigned char dpram0[0x400]; /* Microcode program */ + unsigned char dpram1[0x200]; + unsigned char dpram2[0x100]; /* Microcode scratch */ + unsigned char dpram3[0x100]; /* Not on REV A or B masks */ + unsigned char _rsv0[0xC00-0x800]; + m360SCCENparms_t scc1p; + unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)]; + m360MiscParms_t miscp; + unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)]; + m360SCCparms_t scc2p; + unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)]; + m360SPIparms_t spip; + unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)]; + m360TimerParms_t tmp; + unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)]; + m360SCCparms_t scc3p; + unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)]; + m360IDMAparms_t idma1p; + unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)]; + m360SMCparms_t smc1p; + unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)]; + m360SCCparms_t scc4p; + unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)]; + m360IDMAparms_t idma2p; + unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)]; + m360SMCparms_t smc2p; + unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)]; + + /* + * SIM Block + */ + unsigned long mcr; + unsigned long _pad00; + unsigned char avr; + unsigned char rsr; + unsigned short _pad01; + unsigned char clkocr; + unsigned char _pad02; + unsigned short _pad03; + unsigned short pllcr; + unsigned short _pad04; + unsigned short cdvcr; + unsigned short pepar; + unsigned long _pad05[2]; + unsigned short _pad06; + unsigned char sypcr; + unsigned char swiv; + unsigned short _pad07; + unsigned short picr; + unsigned short _pad08; + unsigned short pitr; + unsigned short _pad09; + unsigned char _pad10; + unsigned char swsr; + unsigned long bkar; + unsigned long bcar; + unsigned long _pad11[2]; + + /* + * MEMC Block + */ + unsigned long gmr; + unsigned short mstat; + unsigned short _pad12; + unsigned long _pad13[2]; + m360MEMCRegisters_t memc[8]; + unsigned char _pad14[0xF0-0xD0]; + unsigned char _pad15[0x100-0xF0]; + unsigned char _pad16[0x500-0x100]; + + /* + * IDMA1 Block + */ + unsigned short iccr; + unsigned short _pad17; + unsigned short cmr1; + unsigned short _pad18; + unsigned long sapr1; + unsigned long dapr1; + unsigned long bcr1; + unsigned char fcr1; + unsigned char _pad19; + unsigned char cmar1; + unsigned char _pad20; + unsigned char csr1; + unsigned char _pad21; + unsigned short _pad22; + + /* + * SDMA Block + */ + unsigned char sdsr; + unsigned char _pad23; + unsigned short sdcr; + unsigned long sdar; + + /* + * IDMA2 Block + */ + unsigned short _pad24; + unsigned short cmr2; + unsigned long sapr2; + unsigned long dapr2; + unsigned long bcr2; + unsigned char fcr2; + unsigned char _pad26; + unsigned char cmar2; + unsigned char _pad27; + unsigned char csr2; + unsigned char _pad28; + unsigned short _pad29; + unsigned long _pad30; + + /* + * CPIC Block + */ + unsigned long cicr; + unsigned long cipr; + unsigned long cimr; + unsigned long cisr; + + /* + * Parallel I/O Block + */ + unsigned short padir; + unsigned short papar; + unsigned short paodr; + unsigned short padat; + unsigned long _pad31[2]; + unsigned short pcdir; + unsigned short pcpar; + unsigned short pcso; + unsigned short pcdat; + unsigned short pcint; + unsigned short _pad32; + unsigned long _pad33[5]; + + /* + * TIMER Block + */ + unsigned short tgcr; + unsigned short _pad34; + unsigned long _pad35[3]; + unsigned short tmr1; + unsigned short tmr2; + unsigned short trr1; + unsigned short trr2; + unsigned short tcr1; + unsigned short tcr2; + unsigned short tcn1; + unsigned short tcn2; + unsigned short tmr3; + unsigned short tmr4; + unsigned short trr3; + unsigned short trr4; + unsigned short tcr3; + unsigned short tcr4; + unsigned short tcn3; + unsigned short tcn4; + unsigned short ter1; + unsigned short ter2; + unsigned short ter3; + unsigned short ter4; + unsigned long _pad36[2]; + + /* + * CP Block + */ + unsigned short cr; + unsigned short _pad37; + unsigned short rccr; + unsigned short _pad38; + unsigned long _pad39[3]; + unsigned short _pad40; + unsigned short rter; + unsigned short _pad41; + unsigned short rtmr; + unsigned long _pad42[5]; + + /* + * BRG Block + */ + unsigned long brgc1; + unsigned long brgc2; + unsigned long brgc3; + unsigned long brgc4; + + /* + * SCC Block + */ + m360SCCRegisters_t scc1; + m360SCCRegisters_t scc2; + m360SCCRegisters_t scc3; + m360SCCRegisters_t scc4; + + /* + * SMC Block + */ + m360SMCRegisters_t smc1; + m360SMCRegisters_t smc2; + + /* + * SPI Block + */ + unsigned short spmode; + unsigned short _pad43[2]; + unsigned char spie; + unsigned char _pad44; + unsigned short _pad45; + unsigned char spim; + unsigned char _pad46[2]; + unsigned char spcom; + unsigned short _pad47[2]; + + /* + * PIP Block + */ + unsigned short pipc; + unsigned short _pad48; + unsigned short ptpr; + unsigned long pbdir; + unsigned long pbpar; + unsigned short _pad49; + unsigned short pbodr; + unsigned long pbdat; + unsigned long _pad50[6]; + + /* + * SI Block + */ + unsigned long simode; + unsigned char sigmr; + unsigned char _pad51; + unsigned char sistr; + unsigned char sicmr; + unsigned long _pad52; + unsigned long sicr; + unsigned short _pad53; + unsigned short sirp[2]; + unsigned short _pad54; + unsigned long _pad55[2]; + unsigned char siram[256]; +} m360_t; + +extern volatile m360_t m360; + +/* + * definitions for the port b SPI pin bits + */ +#define M360_PB_SPI_MISO_MSK (1<< 3) +#define M360_PB_SPI_MOSI_MSK (1<< 2) +#define M360_PB_SPI_CLK_MSK (1<< 1) + +#endif /* _RTEMS_M68K_M68360_H */ diff --git a/cpukit/score/cpu/m68k/include/rtems/m68k/qsm.h b/cpukit/score/cpu/m68k/include/rtems/m68k/qsm.h new file mode 100644 index 0000000000..32dbc1d5f9 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/m68k/qsm.h @@ -0,0 +1,204 @@ +/** + * @file + * + * @brief Motorola M68K Queued Serial Module + * + * The QSM contains two serial interfaces: (a) the queued serial + * peripheral interface (QSPI) and the serial communication interface + * (SCI). The QSPI provides peripheral expansion and/or interprocessor + * communication through a full-duplex, synchronous, three-wire bus. A + * self contained RAM queue permits serial data transfers without CPU + * intervention and automatic continuous sampling. The SCI provides a + * standard non-return to zero mark/space format with wakeup functions + * to allow the CPU to run uninterrupted until woken + * + * For more information, refer to Motorola's "Modular Microcontroller + * Family Queued Serial Module Reference Manual" (Motorola document + * QSMRM/AD). + */ + +/* + * This file was created by John S. Gwynne to support Motorola's 68332 MCU. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. Redistribution of source code and documentation must retain + * the above authorship, this list of conditions and the + * following disclaimer. + * 2. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * This software is provided "AS IS" without warranty of any kind, + * either expressed or implied, including, but not limited to, the + * implied warranties of merchantability, title and fitness for a + * particular purpose. + * + *------------------------------------------------------------------ + */ + +#ifndef _RTEMS_M68K_QSM_H +#define _RTEMS_M68K_QSM_H + +/* SAM-- shift and mask */ +#undef SAM +#define SAM(a,b,c) ((a << b) & c) + + +/* QSM_CRB (QSM Control Register Block) base address of the QSM + control registers */ +#if SIM_MM == 0 +#define QSM_CRB 0x7ffc00 +#else +#undef SIM_MM +#define SIM_MM 1 +#define QSM_CRB 0xfffc00 +#endif + + +#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) + /* QSM Configuration Register */ +#define STOP 0x8000 /* Stop Enable */ +#define FRZ 0x6000 /* Freeze Control */ +#define SUPV 0x0080 /* Supervisor/Unrestricted */ +#define IARB 0x000f /* Inerrupt Arbitration */ + + +#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) + /* QSM Test Register */ +/* Used only for factor testing */ + + +#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB) + /* QSM Interrupt Level Register */ +#define ILQSPI 0x38 /* Interrupt Level for QSPI */ +#define ILSCI 0x07 /* Interrupt Level for SCI */ + + +#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) + /* QSM Interrupt Vector Register */ +#define INTV 0xff /* Interrupt Vector Number */ + + +#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) + /* SCI Control Register 0 */ +#define SCBR 0x1fff /* SCI Baud Rate */ + + +#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) + /* SCI Control Register 1 */ +#define LOOPS 0x4000 /* Loop Mode */ +#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ +#define ILT 0x1000 /* Idle-Line Detect Type */ +#define PT 0x0800 /* Parity Type */ +#define PE 0x0400 /* Parity Enable */ +#define M 0x0200 /* Mode Select */ +#define WAKE 0x0100 /* Wakeup by Address Mark */ +#define TIE 0x0080 /* Transmit Complete Interrupt Enable */ +#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */ +#define RIE 0x0020 /* Receiver Interrupt Enable */ +#define ILIE 0x0010 /* Idle-Line Interrupt Enable */ +#define TE 0x0008 /* Transmitter Enable */ +#define RE 0x0004 /* Receiver Enable */ +#define RWU 0x0002 /* Receiver Wakeup */ +#define SBK 0x0001 /* Send Break */ + + +#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) + /* SCI Status Register */ +#define TDRE 0x0100 /* Transmit Data Register Empty */ +#define TC 0x0080 /* Transmit Complete */ +#define RDRF 0x0040 /* Receive Data Register Full */ +#define RAF 0x0020 /* Receiver Active */ +#define IDLE 0x0010 /* Idle-Line Detected */ +#define OR 0x0008 /* Overrun Error */ +#define NF 0x0004 /* Noise Error Flag */ +#define FE 0x0002 /* Framing Error */ +#define PF 0x0001 /* Parity Error */ + + +#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) + /* SCI Data Register */ + + +#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) + /* Port QS Data Register */ + +#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) + /* PORT QS Pin Assignment Rgister */ +/* Any bit cleared (zero) defines the corresponding pin to be an I/O + pin. Any bit set defines the corresponding pin to be a QSPI + signal. */ +/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which + case it becomes the SPI serial clock SCK. */ +/* note: PQS7 is a digital I/O pin unless the SCI transmitter is + enabled in which case it becomes the SCI serial output TxD. */ +#define QSMFun 0x0 +#define QSMDis 0x1 +/* + * PQSPAR Field | QSM Function | Discrete I/O pin + *------------------+--------------+------------------ */ +#define PQSPA0 0 /* MISO | PQS0 */ +#define PQSPA1 1 /* MOSI | PQS1 */ +#define PQSPA2 2 /* SCK | PQS2 (see note)*/ +#define PQSPA3 3 /* PCSO/!SS | PQS3 */ +#define PQSPA4 4 /* PCS1 | PQS4 */ +#define PQSPA5 5 /* PCS2 | PQS5 */ +#define PQSPA6 6 /* PCS3 | PQS6 */ +#define PQSPA7 7 /* TxD | PQS7 (see note)*/ + + +#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) + /* PORT QS Data Direction Register */ +/* Clearing a bit makes the corresponding pin an input; setting a bit + makes the pin an output. */ + + +#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) + /* QSPI Control Register 0 */ +#define MSTR 0x8000 /* Master/Slave Mode Select */ +#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ +#define BITS 0x3c00 /* Bits Per Transfer */ +#define CPOL 0x0200 /* Clock Polarity */ +#define CPHA 0x0100 /* Clock Phase */ +#define SPBR 0x00ff /* Serial Clock Baud Rate */ + + +#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) + /* QSPI Control Register 1 */ +#define SPE 0x8000 /* QSPI Enable */ +#define DSCKL 0x7f00 /* Delay before SCK */ +#define DTL 0x00ff /* Length of Delay after Transfer */ + + +#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) + /* QSPI Control Register 2 */ +#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ +#define WREN 0x4000 /* Wrap Enable */ +#define WRTO 0x2000 /* Wrap To */ +#define ENDQP 0x0f00 /* Ending Queue Pointer */ +#define NEWQP 0x000f /* New Queue Pointer Value */ + + +#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) + /* QSPI Control Register 3 */ +#define LOOPQ 0x0400 /* QSPI Loop Mode */ +#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ +#define HALT 0x0100 /* Halt */ + + +#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) + /* QSPI Status Register */ +#define SPIF 0x0080 /* QSPI Finished Flag */ +#define MODF 0x0040 /* Mode Fault Flag */ +#define HALTA 0x0020 /* Halt Acknowlwdge Flag */ +#define CPTQP x0000f /* Completed Queue Pointer */ + +#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) + /* QSPI Receive Data RAM */ +#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) + /* QSPI Transmit Data RAM */ +#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) + /* QSPI Command RAM */ + +#endif /* _RTEMS_M68K_QSM_H */ diff --git a/cpukit/score/cpu/m68k/include/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/include/rtems/m68k/sim.h new file mode 100644 index 0000000000..cec6b84cc1 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/m68k/sim.h @@ -0,0 +1,333 @@ +/** + * @file + * + * @brief Motorola M68K System Integration Module + * + * The system integration module (SIM) is used on many Motorola 16- + * and 32-bit MCUs for the following functions: + * + * () System configuration and protection. Bus and software watchdog + * monitors are provided in addition to periodic interrupt generators. + * + * () Clock signal generation for other intermodule bus (IMB) members + * and external devices. + * + * () The generation of chip-select signals that simplify external + * circuitry interface. + * + * () Data ports that are available for general purpose input and + * output. + * + * () A system test block that is intended only for factory tests. + * + * For more information, refer to Motorola's "Modular Microcontroller + * Family System Integration Module Reference Manual" (Motorola document + * SIMRM/AD). + */ + +/* + * This file was created by John S. Gwynne to support Motorola's 68332 MCU. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. Redistribution of source code and documentation must retain + * the above authorship, this list of conditions and the + * following disclaimer. + * 2. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * This software is provided "AS IS" without warranty of any kind, + * either expressed or implied, including, but not limited to, the + * implied warranties of merchantability, title and fitness for a + * particular purpose. + * + *------------------------------------------------------------------ + */ + +#ifndef _RTEMS_M68K_SIM_H +#define _RTEMS_M68K_SIM_H + + +/* SAM-- shift and mask */ +#undef SAM +#define SAM(a,b,c) ((a << b) & c) + +/* + * These macros make this file usable from assembly. + */ + +#ifdef ASM +#define SIM_VOLATILE_USHORT_POINTER +#define SIM_VOLATILE_UCHAR_POINTER +#else +#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const) +#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const) +#endif + +/* SIM_CRB (SIM Control Register Block) base address of the SIM + control registers */ +#ifndef SIM_CRB +#if SIM_MM == 0 +#define SIM_CRB 0x7ffa00 +#else /* SIM_MM */ +#undef SIM_MM +#define SIM_MM 1 +#define SIM_CRB 0xfffa00 +#endif /* SIM_MM */ +#endif /* SIM_CRB */ + + +#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB) + /* Module Configuration Register */ +#define EXOFF 0x8000 /* External Clock Off */ +#define FRZSW 0x4000 /* Freeze Software Enable */ +#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ +#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ +#define SHEN 0x0300 /* Show Cycle Enable */ +#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ +#define MM 0x0040 /* Module Mapping */ +#define IARB 0x000f /* Interrupt Arbitration Field */ + + + +#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB) + /* SIM Test Register */ +/* Used only for factor testing */ + + + +#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) + /* Clock Synthesizer Control Register */ +#define VCO 0x8000 /* Frequency Control (VCO) */ +#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ +#define COUNTER 0x3f00 /* Frequency Control Counter */ +#define EDIV 0x0080 /* ECLK Divide Rate */ +#define SLIMP 0x0010 /* Limp Mode Status */ +#define SLOCK 0x0008 /* Synthesizer Lock */ +#define RSTEN 0x0004 /* Reset Enable */ +#define STSIM 0x0002 /* Stop Mode SIM Clock */ +#define STEXT 0x0001 /* Stop Mode External Clock */ + + + +#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB) + /* Reset Status Register */ +#define EXT 0x0080 /* External Reset */ +#define POW 0x0040 /* Power-On Reset */ +#define SW 0x0020 /* Software Watchdog Reset */ +#define DBF 0x0010 /* Double Bus Fault Reset */ +#define LOC 0x0004 /* Loss of Clock Reset */ +#define SYS 0x0002 /* System Reset */ +#define TST 0x0001 /* Test Submodule Reset */ + + + +#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB) + /* System Integration Test Register */ +/* Used only for factor testing */ + + + +#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB) +#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB) + /* Port E Data Register */ +#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB) + /* Port E Data Direction Register */ +#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB) + /* Port E Pin Assignment Register */ +/* Any bit cleared (zero) defines the corresponding pin to be an I/O + pin. Any bit set defines the corresponding pin to be a bus control + signal. */ + + + +#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB) +#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB) + /* Port F Data Register */ +#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB) + /* Port E Data Direction Register */ +#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB) +/* Any bit cleared (zero) defines the corresponding pin to be an I/O + pin. Any bit set defines the corresponding pin to be a bus control + signal. */ + + + +#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB) +/* !!! can write to only once after reset !!! */ + /* System Protection Control Register */ +#define SWE 0x80 /* Software Watch Enable */ +#define SWP 0x40 /* Software Watchdog Prescale */ +#define SWT 0x30 /* Software Watchdog Timing */ +#define HME 0x08 /* Halt Monitor Enable */ +#define BME 0x04 /* Bus Monitor External Enable */ +#define BMT 0x03 /* Bus Monitor Timing */ + + + +#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB) + /* Periodic Interrupt Control Reg. */ +#define PIRQL 0x0700 /* Periodic Interrupt Request Level */ +#define PIV 0x00ff /* Periodic Interrupt Level */ + + + +#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB) + /* Periodic Interrupt Timer Register */ +#define PTP 0x0100 /* Periodic Timer Prescaler Control */ +#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ + + + +#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB) + /* Software Service Register */ +/* write 0x55 then 0xaa to service the software watchdog */ + + + +#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB) + /* Test Module Master Shift A */ +#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB) + /* Test Module Master Shift A */ +#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB) + /* Test Module Shift Count */ +#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB) + /* Test Module Repetition Counter */ +#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB) + /* Test Module Control */ +#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB) + /* Test Module Distributed */ +/* Used only for factor testing */ + + + +#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB) + /* Port C Data */ + + + +#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB) + /* Chip Select Pin Assignment + Resgister 0 */ +/* CSPAR0 contains seven two-bit fields that determine the functions + of corresponding chip-select pins. CSPAR0[15:14] are not + used. These bits always read zero; write have no effect. CSPAR0 bit + 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ +#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB) + /* Chip Select Pin Assignment + Register 1 */ +/* CSPAR1 contains five two-bit fields that determine the finctions of + corresponding chip-select pins. CSPAR1[15:10] are not used. These + bits always read zero; writes have no effect. */ +/* + * + * Bit Field | Description + * ------------+--------------- + * 00 | Discrete Output + * 01 | Alternate Function + * 10 | Chip Select (8-bit port) + * 11 | Chip Select (16-bit port) + */ +#define DisOut 0x0 +#define AltFun 0x1 +#define CS8bit 0x2 +#define CS16bit 0x3 +/* + * + * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output + *-----------------+--------------------+--------------------+---------------*/ +#define CS_5 12 /* !CS5 | FC2 | PC2 */ +#define CS_4 10 /* !CS4 | FC1 | PC1 */ +#define CS_3 8 /* !CS3 | FC0 | PC0 */ +#define CS_2 6 /* !CS2 | !BGACK | */ +#define CS_1 4 /* !CS1 | !BG | */ +#define CS_0 2 /* !CS0 | !BR | */ +#define CSBOOT 0 /* !CSBOOT | | */ +/* | | | */ +#define CS_10 8 /* !CS10 | ADDR23 | ECLK */ +#define CS_9 6 /* !CS9 | ADDR22 | PC6 */ +#define CS_8 4 /* !CS8 | ADDR21 | PC5 */ +#define CS_7 2 /* !CS7 | ADDR20 | PC4 */ +#define CS_6 0 /* !CS6 | ADDR19 | PC3 */ + +#define BS_2K 0x0 +#define BS_8K 0x1 +#define BS_16K 0x2 +#define BS_64K 0x3 +#define BS_128K 0x4 +#define BS_256K 0x5 +#define BS_512K 0x6 +#define BS_1M 0x7 + +#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB) +#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB) +#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB) +#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB) +#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB) +#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB) +#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB) +#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB) +#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB) +#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB) +#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB) +#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB) + +#define MODE 0x8000 +#define Disable 0 +#define LowerByte 0x2000 +#define UpperByte 0x4000 +#define BothBytes 0x6000 +#define ReadOnly 0x0800 +#define WriteOnly 0x1000 +#define ReadWrite 0x1800 +#define SyncAS 0x0 +#define SyncDS 0x0400 + +#define WaitStates_0 (0x0 << 6) +#define WaitStates_1 (0x1 << 6) +#define WaitStates_2 (0x2 << 6) +#define WaitStates_3 (0x3 << 6) +#define WaitStates_4 (0x4 << 6) +#define WaitStates_5 (0x5 << 6) +#define WaitStates_6 (0x6 << 6) +#define WaitStates_7 (0x7 << 6) +#define WaitStates_8 (0x8 << 6) +#define WaitStates_9 (0x9 << 6) +#define WaitStates_10 (0xa << 6) +#define WaitStates_11 (0xb << 6) +#define WaitStates_12 (0xc << 6) +#define WaitStates_13 (0xd << 6) +#define FastTerm (0xe << 6) +#define External (0xf << 6) + +#define CPUSpace (0x0 << 4) +#define UserSpace (0x1 << 4) +#define SupSpace (0x2 << 4) +#define UserSupSpace (0x3 << 4) + +#define IPLevel_any 0x0 +#define IPLevel_1 0x2 +#define IPLevel_2 0x4 +#define IPLevel_3 0x6 +#define IPLevel_4 0x8 +#define IPLevel_5 0xa +#define IPLevel_6 0xc +#define IPLevel_7 0xe + +#define AVEC 1 + +#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB) +#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB) +#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB) +#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB) +#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB) +#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB) +#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB) +#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB) +#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB) +#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB) +#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB) +#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB) + +#endif /* _RTEMS_M68K_SIM_H */ diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h new file mode 100644 index 0000000000..2be10c9638 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h @@ -0,0 +1,735 @@ +/** + * @file + * + * @brief Motorola M68K CPU Dependent Source + * + * This include file contains information pertaining to the Motorola + * m68xxx processor family. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * M68K Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Use the m68k's hardware interrupt stack support and have the + * interrupt manager allocate the memory for it. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1) +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 +#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 +#else +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 +#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 +#endif +#define CPU_ALLOCATE_INTERRUPT_STACK 1 + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/* + * Some family members have no FP, some have an FPU such as the + * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). + * + * NOTE: If on a CPU without hardware FP, then one can use software + * emulation. The gcc software FP emulation code has data which + * must be contexted switched on a per task basis. + */ + +#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) + #define CPU_HARDWARE_FP TRUE + #define CPU_SOFTWARE_FP FALSE +#else + #define CPU_HARDWARE_FP FALSE + #if defined( __GNUC__ ) + #define CPU_SOFTWARE_FP TRUE + #else + #define CPU_SOFTWARE_FP FALSE + #endif +#endif + +/* + * All tasks are not by default floating point tasks on this CPU. + * The IDLE task does not have a floating point context on this CPU. + * It is safe to use the deferred floating point context switch + * algorithm on this CPU. + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE +#define CPU_IDLE_TASK_IS_FP FALSE +#define CPU_USE_DEFERRED_FP_SWITCH TRUE +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 16 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +#define CPU_MAXIMUM_PROCESSORS 32 + +#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) + #if defined( __mc68060__ ) + #define M68K_FP_STATE_SIZE 16 + #else + #define M68K_FP_STATE_SIZE 216 + #endif +#endif + +#ifndef ASM + +/* structures */ + +/* + * Basic integer context for the m68k family. + */ + +typedef struct { + uint32_t sr; /* (sr) status register */ + uint32_t d2; /* (d2) data register 2 */ + uint32_t d3; /* (d3) data register 3 */ + uint32_t d4; /* (d4) data register 4 */ + uint32_t d5; /* (d5) data register 5 */ + uint32_t d6; /* (d6) data register 6 */ + uint32_t d7; /* (d7) data register 7 */ + void *a2; /* (a2) address register 2 */ + void *a3; /* (a3) address register 3 */ + void *a4; /* (a4) address register 4 */ + void *a5; /* (a5) address register 5 */ + void *a6; /* (a6) address register 6 */ + void *a7_msp; /* (a7) master stack pointer */ + #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) + uint8_t fpu_dis; + #endif +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->a7_msp + +/* + * Floating point context areas and support routines + */ + +#if ( CPU_SOFTWARE_FP == TRUE ) + /* + * This is the same as gcc's view of the software FP condition code + * register _fpCCR. The implementation of the emulation code is + * in the gcc-VERSION/config/m68k directory. This structure is + * correct as of gcc 2.7.2.2. + */ + typedef struct { + uint16_t _exception_bits; + uint16_t _trap_enable_bits; + uint16_t _sticky_bits; + uint16_t _rounding_mode; + uint16_t _format; + uint16_t _last_operation; + union { + float sf; + double df; + } _operand1; + union { + float sf; + double df; + } _operand2; + } Context_Control_fp; + + #define _CPU_Context_Initialize_fp( _fp_area ) \ + { \ + Context_Control_fp *_fp; \ + _fp = *(Context_Control_fp **)_fp_area; \ + _fp->_exception_bits = 0; \ + _fp->_trap_enable_bits = 0; \ + _fp->_sticky_bits = 0; \ + _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ + _fp->_format = 0; /* NIL */ \ + _fp->_last_operation = 0; /* NOOP */ \ + _fp->_operand1.df = 0; \ + _fp->_operand2.df = 0; \ + } +#endif + +#if ( CPU_HARDWARE_FP == TRUE ) + #if defined( __mcoldfire__ ) + /* We need memset() to initialize the FP context */ + #include + + #if ( M68K_HAS_FPU == 1 ) + /* + * The Cache Control Register (CACR) has write-only access. It is also + * used to enable and disable the FPU. We need to maintain a copy of + * this register to allow per thread values. + */ + extern uint32_t _CPU_cacr_shadow; + #endif + + /* We assume that each ColdFire core with a FPU has also an EMAC unit */ + typedef struct { + uint32_t emac_macsr; + uint32_t emac_acc0; + uint32_t emac_acc1; + uint32_t emac_acc2; + uint32_t emac_acc3; + uint32_t emac_accext01; + uint32_t emac_accext23; + uint32_t emac_mask; + #if ( M68K_HAS_FPU == 1 ) + uint16_t fp_state_format; + uint16_t fp_state_fpcr; + double fp_state_op; + uint32_t fp_state_fpsr; + + /* + * We need to save the FP Instruction Address Register (FPIAR), because + * a context switch can occur within a FP exception before the handler + * was able to save this register. + */ + uint32_t fp_fpiar; + + double fp_data [8]; + #endif + } Context_Control_fp; + + /* + * The reset value for all context relevant registers except the FP data + * registers is zero. The reset value of the FP data register is NAN. The + * restore of the reset FP state will reset the FP data registers, so the + * initial value of them can be arbitrary here. + */ + #define _CPU_Context_Initialize_fp( _fp_area ) \ + memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) + #else + /* + * FP context save area for the M68881/M68882 and 68060 numeric + * coprocessors. + */ + typedef struct { + /* + * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE + * 96 bytes for FMOVEM FP0-7 + * 12 bytes for FMOVEM CREGS + * 4 bytes for non-null flag + */ + uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112]; + } Context_Control_fp; + + /* + * The floating-point context is saved/restored via FSAVE/FRESTORE which + * use a growing down stack. Initialize the stack and adjust the FP area + * pointer accordingly. + */ + #define _CPU_Context_Initialize_fp( _fp_area ) \ + { \ + uint32_t *_fp_context = _Addresses_Add_offset( \ + *(_fp_area), CPU_CONTEXT_FP_SIZE - 4); \ + *(--(_fp_context)) = 0; \ + *(_fp_area) = (void *)(_fp_context); \ + } + #endif +#endif + +/* + * The following structures define the set of information saved + * on the current stack by RTEMS upon receipt of each exc/interrupt. + * These are not used by m68k handlers. + * The exception frame is for rdbg. + */ + +typedef struct { + uint32_t vecnum; /* vector number */ +} CPU_Interrupt_frame; + +typedef struct { + uint32_t vecnum; /* vector number */ + uint32_t sr; /* status register */ + uint32_t pc; /* program counter */ + uint32_t d0, d1, d2, d3, d4, d5, d6, d7; + uint32_t a0, a1, a2, a3, a4, a5, a6, a7; +} CPU_Exception_frame; + +/* variables */ + +extern void* _VBR; + +#endif /* ASM */ + +/* constants */ + +/* + * This defines the number of levels and the mask used to pick those + * bits out of a thread mode. + */ + +#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ +#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ + +/* + * context size area for floating point + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * extra stack required by the MPCI receive server thread + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 + +/* + * m68k family supports 256 distinct vectors. + */ + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * Minimum size of a thread's stack. + */ + +#define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE + +/* + * Maximum priority of a thread. Note based from 0 which is the idle task. + */ +#define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM + +#define CPU_SIZEOF_POINTER 4 + +/* + * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. + */ + +#define CPU_ALIGNMENT 4 +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * On m68k thread stacks require no further alignment after allocation + * from the Workspace. + */ + +#define CPU_STACK_ALIGNMENT 0 + +#ifndef ASM + +/* macros */ + +/* + * ISR handler macros + * + * These macros perform the following functions: + * + initialize the RTEMS vector table + * + disable all maskable CPU interrupts + * + restore previous interrupt level (enable) + * + temporarily restore interrupts (flash) + * + set a particular level + */ + +#define _CPU_Initialize_vectors() + +#define _CPU_ISR_Disable( _level ) \ + m68k_disable_interrupts( _level ) + +#define _CPU_ISR_Enable( _level ) \ + m68k_enable_interrupts( _level ) + +#define _CPU_ISR_Flash( _level ) \ + m68k_flash_interrupts( _level ) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & 0x0700 ) == 0; +} + +#define _CPU_ISR_Set_level( _newlevel ) \ + m68k_set_interrupt_level( _newlevel ) + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* + * Context handler macros + * + * These macros perform the following functions: + * + initialize a context area + * + restart the current thread + * + calculate the initial pointer into a FP context area + * + initialize an FP context area + */ + +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +/* end of Context handler macros */ + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * Fatal Error manager macros + * + * These macros perform the following functions: + * + disable interrupts and halt the CPU + */ + +#if ( defined(__mcoldfire__) ) +#define _CPU_Fatal_halt( _source, _error ) \ + { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ + "or.l %2,%%d0\n\t" \ + "move.w %%d0,%%sr\n\t" \ + "move.l %1,%%d0\n\t" \ + "move.l #0xDEADBEEF,%%d1\n\t" \ + "halt" \ + : "=g" (_error) \ + : "0" (_error), "d"(0x0700) \ + : "d0", "d1" ); \ + } +#else +#define _CPU_Fatal_halt( _source, _error ) \ + { __asm__ volatile( "movl %0,%%d0; " \ + "orw #0x0700,%%sr; " \ + "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ + } +#endif + +/* end of Fatal Error manager macros */ + +/* + * Bitfield handler macros + * + * These macros perform the following functions: + * + scan for the highest numbered (MSB) set in a 16 bit bitfield + * + * NOTE: + * + * It appears that on the M68020 bitfield are always 32 bits wide + * when in a register. This code forces the bitfield to be in + * memory (it really always is anyway). This allows us to + * have a real 16 bit wide bitfield which operates "correctly." + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE FALSE + +#if ( M68K_HAS_BFFFO != 1 ) +/* + * Lookup table for BFFFO simulation + */ +extern const unsigned char _CPU_m68k_BFFFO_table[256]; +#endif + +#if ( M68K_HAS_BFFFO == 1 ) + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); + +#elif ( __mcfisaaplus__ ) + /* This is simplified by the fact that RTEMS never calls it with _value=0 */ +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + __asm__ volatile ( \ + " swap %0\n" \ + " ff1.l %0\n" \ + : "=d" ((_output)) \ + : "0" ((_value)) \ + : "cc" ) ; + +#else +/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in + _CPU_Priority_bits_index is not needed), handles the 0 case, and + does not molest _value -- jsg */ +#if ( defined(__mcoldfire__) ) + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + register int dumby; \ + \ + __asm__ volatile ( \ + " clr.l %1\n" \ + " move.w %2,%1\n" \ + " lsr.l #8,%1\n" \ + " beq.s 1f\n" \ + " move.b (%3,%1),%0\n" \ + " bra.s 0f\n" \ + "1: move.w %2,%1\n" \ + " move.b (%3,%1),%0\n" \ + " addq.l #8,%0\n" \ + "0: and.l #0xff,%0\n" \ + : "=&d" ((_output)), "=&d" ((dumby)) \ + : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ + : "cc" ) ; \ + } +#elif ( M68K_HAS_EXTB_L == 1 ) +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + register int dumby; \ + \ + __asm__ volatile ( " move.w %2,%1\n" \ + " lsr.w #8,%1\n" \ + " beq.s 1f\n" \ + " move.b (%3,%1.w),%0\n" \ + " extb.l %0\n" \ + " bra.s 0f\n" \ + "1: moveq.l #8,%0\n" \ + " add.b (%3,%2.w),%0\n" \ + "0:\n" \ + : "=&d" ((_output)), "=&d" ((dumby)) \ + : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ + : "cc" ) ; \ + } +#else +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + register int dumby; \ + \ + __asm__ volatile ( " move.w %2,%1\n" \ + " lsr.w #8,%1\n" \ + " beq.s 1f\n" \ + " move.b (%3,%1.w),%0\n" \ + " and.l #0x000000ff,%0\n"\ + " bra.s 0f\n" \ + "1: moveq.l #8,%0\n" \ + " add.b (%3,%2.w),%0\n" \ + "0:\n" \ + : "=&d" ((_output)), "=&d" ((dumby)) \ + : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ + : "cc" ) ; \ + } +#endif + +#endif + +/* end of Bitfield handler macros */ + +/* + * Priority handler macros + * + * These macros perform the following functions: + * + return a mask with the bit for this major/minor portion of + * of thread priority set. + * + translate the bit number returned by "Bitfield_find_first_bit" + * into an index into the thread ready chain bit maps + */ + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 0x8000 >> (_bit_number) ) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +void _CPU_Context_Restart_self( + Context_Control *the_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/** + * This method prints the CPU exception frame. + * + * @param[in] frame points to the frame to be printed + */ +void _CPU_Exception_frame_print( + const CPU_Exception_frame *frame +); + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#if (M68K_HAS_FPSP_PACKAGE == 1) +/* + * Hooks for the Floating Point Support Package (FPSP) provided by Motorola + * + * NOTES: + * + * Motorola 68k family CPU's before the 68040 used a coprocessor + * (68881 or 68882) to handle floating point. The 68040 has internal + * floating point support -- but *not* the complete support provided by + * the 68881 or 68882. The leftover functions are taken care of by the + * M68040 Floating Point Support Package. Quoting from the MC68040 + * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): + * + * "When used with the M68040FPSP, the MC68040 FPU is fully + * compliant with IEEE floating-point standards." + * + * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and + * is invoked early in the application code to ensure that proper FP + * behavior is installed. This is not left to the BSP to call, since + * this would force all applications using that BSP to use FPSP which + * is not necessarily desirable. + * + * There is a similar package for the 68060 but RTEMS does not yet + * support the 68060. + */ + +void M68KFPSPInstallExceptionHandlers (void); + +extern int (*_FPSP_install_raw_handler)( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +#endif + + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/m68k/include/rtems/score/m68k.h b/cpukit/score/cpu/m68k/include/rtems/score/m68k.h new file mode 100644 index 0000000000..818578c078 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/score/m68k.h @@ -0,0 +1,502 @@ +/** + * @file + * + * @brief Motorola M68K CPU Dependent Source + * + * This include file contains information pertaining to the Motorola + * m68xxx processor family. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_M68K_H +#define _RTEMS_SCORE_M68K_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section contains the information required to build + * RTEMS for a particular member of the Motorola MC68xxx + * family. It does this by setting variables to indicate + * which implementation dependent features are present in + * a particular member of the family. + * + * Currently recognized: + * -m68000 + * -m68000 -msoft-float + * -m68020 + * -m68020 -msoft-float + * -m68030 + * -m68040 -msoft-float + * -m68040 + * -m68040 -msoft-float + * -m68060 + * -m68060 -msoft-float + * -m68302 (no FP) (deprecated, use -m68000) + * -m68332 (no FP) (deprecated, use -mcpu32) + * -mcpu32 (no FP) + * -m5200 (no FP) + * -m528x (no FP, ISA A+) + * + * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between + * the CPU32 and CPU32+. The option -mcpu32 generates code which can + * be run on either core. RTEMS distinguishes between these two cores + * because they have different alignment rules which impact performance. + * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should + * be defined in your custom file (see make/custom/gen68360.cfg for an + * example of how to do this. If gcc ever distinguishes between these + * two cores, then RTEMS__mcpu32p__ usage will be replaced with the + * appropriate compiler defined predefine. + * + * Here is some information on the 040 variants (courtesy of Doug McBride, + * mcbride@rodin.colorado.edu): + * + * "The 68040 is a superset of the 68EC040 and the 68LC040. The + * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the + * 68EC040 have renamed the DLE pin as JS0 which must be tied to + * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The + * 68EC040 has access control units instead of memory management units. + * The 68EC040 should not have the PFLUSH or PTEST instructions executed + * (cause an indeterminate result). The 68EC040 and 68LC040 do not + * implement the DLE or multiplexed bus modes. The 68EC040 does not + * implement the output buffer impedance selection mode of operation." + * + * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction + * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, + * 68010, 68302, 68306, 68307). This instruction is available on the 68020 + * up and the cpu32 based models. + * + * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned + * data access (68020, 68030, 68040, 68060, CPU32+). + * + * NOTE: + * Eventually it would be nice to evaluate doing a lot of this section + * by having each model specify which core it uses and then go from there. + */ + +/* + * Handle the Coldfire family based on the instruction set. + */ +#if defined(__mcoldfire__) + +# define CPU_NAME "Motorola ColdFire" + +# if defined(__mcfisaa__) +/* Motorola ColdFire ISA A */ +# define CPU_MODEL_NAME "mcfisaa" +# define M68K_HAS_VBR 1 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_PREINDEXING 0 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 + +# elif defined(__mcfisaaplus__) +/* Motorola ColdFire ISA A+ */ +# define CPU_MODEL_NAME "mcfisaaplus" +# define M68K_HAS_VBR 1 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_PREINDEXING 0 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 + +# elif defined(__mcfisab__) +/* Motorola ColdFire ISA B */ +# define CPU_MODEL_NAME "mcfisab" +# define M68K_HAS_VBR 1 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_PREINDEXING 0 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 + +# else +# error "Unsupported Coldfire ISA -- Please notify RTEMS" +# endif + +/* + * Assume the FPU support is independent. I think it is just the ISA B + * instruction set. + */ +# if defined (__mcffpu__) +# define M68K_HAS_FPU 1 + /* + * td: can we be sure that all CFs with FPU also have an EMAC? + */ +# define M68K_HAS_EMAC 1 +# define M68K_HAS_FPSP_PACKAGE 0 +# else +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 +# endif + +/* + * Tiny RTEMS support. Small stack and limited priorities. + * + * These CPUs have very limited on-CPU memory which cannot + * be expanded. We have to be gentle with them or nothing + * will every run. + */ +# if (defined(__mcf_cpu_52221) || \ + defined(__mcf_cpu_52223) || \ + defined(__mcf_cpu_52230) || \ + defined(__mcf_cpu_52231) || \ + defined(__mcf_cpu_52232) || \ + defined(__mcf_cpu_52233) || \ + defined(__mcf_cpu_52234) || \ + defined(__mcf_cpu_52235) || \ + defined(__mcf_cpu_52225) || \ + defined(__mcf_cpu_52235)) + #define M68K_CPU_STACK_MINIMUM_SIZE 1024 + /* Define the lowest priority. Based from 0 to this is 16 levels. */ + #define M68K_CPU_PRIORITY_MAXIMUM 15 +# else + #define M68K_CPU_STACK_MINIMUM_SIZE 4096 + /* Use the default number of priorities */ + #define M68K_CPU_PRIORITY_MAXIMUM 255 +# endif + +#else + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. Notice the only exception to this is that + * gcc does not distinguish between CPU32 and CPU32+. This + * feature selection logic is setup such that if RTEMS__mcpu32p__ + * is defined, then CPU32+ rules are used. Otherwise, the safe + * but less efficient CPU32 rules are used for the CPU32+. + */ + +# define CPU_NAME "Motorola MC68xxx" + +/* + * One stack size fits all 68000 processors. + */ +# define M68K_CPU_STACK_MINIMUM_SIZE 4096 + +# if (defined(__mc68020__) && !defined(__mcpu32__)) + +# define CPU_MODEL_NAME "m68020" +# define M68K_HAS_VBR 1 +# define M68K_HAS_SEPARATE_STACKS 1 +# define M68K_HAS_BFFFO 1 +# define M68K_HAS_PREINDEXING 1 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 +# if defined (__HAVE_68881__) +# define M68K_HAS_FPU 1 +# define M68K_HAS_FPSP_PACKAGE 0 +# else +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 +# endif + +# elif defined(__mc68030__) + +# define CPU_MODEL_NAME "m68030" +# define M68K_HAS_VBR 1 +# define M68K_HAS_SEPARATE_STACKS 1 +# define M68K_HAS_BFFFO 1 +# define M68K_HAS_PREINDEXING 1 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 +# if defined (__HAVE_68881__) +# define M68K_HAS_FPU 1 +# define M68K_HAS_FPSP_PACKAGE 0 +# else +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 +# endif + +# elif defined(__mc68040__) + +# define CPU_MODEL_NAME "m68040" +# define M68K_HAS_VBR 1 +# define M68K_HAS_SEPARATE_STACKS 1 +# define M68K_HAS_BFFFO 1 +# define M68K_HAS_PREINDEXING 1 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 +# if defined (__HAVE_68881__) +# define M68K_HAS_FPU 1 +# define M68K_HAS_FPSP_PACKAGE 1 +# else +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 +# endif + +# elif defined(__mc68060__) + +# define CPU_MODEL_NAME "m68060" +# define M68K_HAS_VBR 1 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_BFFFO 1 +# define M68K_HAS_PREINDEXING 1 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 +# if defined (__HAVE_68881__) +# define M68K_HAS_FPU 1 +# define M68K_HAS_FPSP_PACKAGE 0 +# else +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 +# endif + +# elif defined(__mc68302__) + +# define CPU_MODEL_NAME "m68302" +# define M68K_HAS_VBR 0 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_PREINDEXING 0 +# define M68K_HAS_EXTB_L 0 +# define M68K_HAS_MISALIGNED 0 +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 + + /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ +# elif defined(RTEMS__mcpu32p__) + +# define CPU_MODEL_NAME "mcpu32+" +# define M68K_HAS_VBR 1 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_PREINDEXING 1 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 1 +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 + +# elif defined(__mcpu32__) + +# define CPU_MODEL_NAME "mcpu32" +# define M68K_HAS_VBR 1 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_PREINDEXING 1 +# define M68K_HAS_EXTB_L 1 +# define M68K_HAS_MISALIGNED 0 +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 + +# elif defined(__mc68000__) + +# define CPU_MODEL_NAME "m68000" +# define M68K_HAS_VBR 0 +# define M68K_HAS_SEPARATE_STACKS 0 +# define M68K_HAS_BFFFO 0 +# define M68K_HAS_PREINDEXING 0 +# define M68K_HAS_EXTB_L 0 +# define M68K_HAS_MISALIGNED 0 +# if defined (__HAVE_68881__) +# define M68K_HAS_FPU 1 +# define M68K_HAS_FPSP_PACKAGE 0 +# else +# define M68K_HAS_FPU 0 +# define M68K_HAS_FPSP_PACKAGE 0 +# endif + +# else + +# error "Unsupported 68000 CPU model -- are you sure you're running a 68k compiler?" + +# endif + +/* + * No Tiny RTEMS support on the standard 68000 family. + */ +# define M68K_CPU_STACK_MINIMUM_SIZE 4096 +# define M68K_CPU_PRIORITY_MAXIMUM 255 + +#endif + +/* + * OBSOLETE: Backward compatibility only - Don't use. + * Use __mcoldfire__ instead. + */ +#if defined(__mcoldfire__) +#define M68K_COLDFIRE_ARCH 1 +#else +#define M68K_COLDFIRE_ARCH 0 +#endif + +#ifndef ASM + +#if ( defined(__mcoldfire__) ) +#define m68k_disable_interrupts( _level ) \ + do { register uint32_t _tmpsr = 0x0700; \ + __asm__ volatile ( "move.w %%sr,%0\n\t" \ + "or.l %0,%1\n\t" \ + "move.w %1,%%sr" \ + : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) \ + : "cc" ); \ + } while( 0 ) +#else +#define m68k_disable_interrupts( _level ) \ + __asm__ volatile ( "move.w %%sr,%0\n\t" \ + "or.w #0x0700,%%sr" \ + : "=d" (_level) \ + : : "cc" ) +#endif + +#define m68k_enable_interrupts( _level ) \ + __asm__ volatile ( "move.w %0,%%sr " : : "d" (_level) : "cc"); + +#if ( defined(__mcoldfire__) ) +#define m68k_flash_interrupts( _level ) \ + do { register uint32_t _tmpsr = 0x0700; \ + asm volatile ( "move.w %2,%%sr\n\t" \ + "or.l %2,%1\n\t" \ + "move.w %1,%%sr" \ + : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) \ + : "cc"); \ + } while( 0 ) +#else +#define m68k_flash_interrupts( _level ) \ + __asm__ volatile ( "move.w %0,%%sr\n\t" \ + "or.w #0x0700,%%sr" \ + : : "d" (_level) \ + : "cc" ) +#endif + +#define m68k_get_interrupt_level( _level ) \ + do { \ + register uint32_t _tmpsr; \ + \ + __asm__ volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ + _level = (_tmpsr & 0x0700) >> 8; \ + } while (0) + +#define m68k_set_interrupt_level( _newlevel ) \ + do { \ + register uint32_t _tmpsr; \ + \ + __asm__ volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ + _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ + __asm__ volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \ + } while (0) + +#if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) ) +#define m68k_get_vbr( vbr ) \ + __asm__ volatile ( "movec %%vbr,%0 " : "=r" (vbr)) + +#define m68k_set_vbr( vbr ) \ + __asm__ volatile ( "movec %0,%%vbr " : : "r" (vbr)) + +#elif ( defined(__mcoldfire__) ) +extern void* _VBR; +#define m68k_get_vbr( _vbr ) _vbr = &_VBR + +#define m68k_set_vbr( _vbr ) \ + do { \ + __asm__ volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \ + _VBR = (void *)_vbr; \ + } while(0) + +#else +#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR +#define m68k_set_vbr( _vbr ) +#endif + +/* + * Access Control Registers + */ +#define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) +#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) +#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) + +/* + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + */ +#if ( defined(__mcoldfire__) ) + +/* There are no rotate commands in Coldfire architecture. We will use + * generic implementation of endian swapping for Coldfire. + */ +static inline uint32_t m68k_swap_u32( + uint32_t value + ) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +static inline uint16_t m68k_swap_u16( + uint16_t value +) +{ + return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); +} + +#else + +static inline uint32_t m68k_swap_u32( + uint32_t value +) +{ + uint32_t swapped = value; + + __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); + __asm__ volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); + __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); + + return( swapped ); +} + +static inline uint16_t m68k_swap_u16( + uint16_t value +) +{ + uint16_t swapped = value; + + __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); + + return( swapped ); +} +#endif + +#define CPU_swap_u32( value ) m68k_swap_u32( value ) +#define CPU_swap_u16( value ) m68k_swap_u16( value ) + + +/* + * _CPU_virtual_to_physical + * + * This function is used to map virtual addresses to physical + * addresses. + * + * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE + * PHYSICAL ADDRESSES + */ +static inline void * _CPU_virtual_to_physical ( + const void * d_addr ) +{ + return (void *) d_addr; +} + + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_M68K_H */ diff --git a/cpukit/score/cpu/m68k/include/rtems/score/types.h b/cpukit/score/cpu/m68k/include/rtems/score/types.h new file mode 100644 index 0000000000..947c6ace69 --- /dev/null +++ b/cpukit/score/cpu/m68k/include/rtems/score/types.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @brief Motorola M68K CPU Type Definitions + * + * This include file contains type definitions pertaining to the Motorola + * m68xxx processor family. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/m68k/preinstall.am b/cpukit/score/cpu/m68k/preinstall.am deleted file mode 100644 index a580b7a4b5..0000000000 --- a/cpukit/score/cpu/m68k/preinstall.am +++ /dev/null @@ -1,70 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/m68k - @: > $(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/m68k/m68302.h: rtems/m68k/m68302.h $(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/m68k/m68302.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/m68k/m68302.h - -$(PROJECT_INCLUDE)/rtems/m68k/m68360.h: rtems/m68k/m68360.h $(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/m68k/m68360.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/m68k/m68360.h - -$(PROJECT_INCLUDE)/rtems/m68k/qsm.h: rtems/m68k/qsm.h $(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/m68k/qsm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/m68k/qsm.h - -$(PROJECT_INCLUDE)/rtems/m68k/sim.h: rtems/m68k/sim.h $(PROJECT_INCLUDE)/rtems/m68k/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/m68k/sim.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/m68k/sim.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/m68k.h: rtems/score/m68k.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/m68k.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/m68k.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/m68k/rtems/asm.h b/cpukit/score/cpu/m68k/rtems/asm.h deleted file mode 100644 index cbd2a7f8b2..0000000000 --- a/cpukit/score/cpu/m68k/rtems/asm.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) -#define sp REG (sp) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) -#define vbr REG (vbr) -#define dfc REG (dfc) -#define sfc REG (sfc) - -/* mcf52xx special regs */ -#define cacr REG (cacr) -#define acr0 REG (acr0) -#define acr1 REG (acr1) -#define rambar0 REG (rambar0) -#define mbar REG (mbar) - -/* additional v4e special regs */ -#define rambar1 REG (rambar1) -#define macsr REG (macsr) -#define acc0 REG (acc0) -#define acc1 REG (acc1) -#define acc2 REG (acc2) -#define acc3 REG (acc3) -#define accext01 REG (accext01) -#define accext23 REG (accext23) -#define mask REG (mask) - - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) -#define fpsr REG (fpsr) - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h deleted file mode 100644 index acf55f50c5..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h +++ /dev/null @@ -1,659 +0,0 @@ -/** - * @file - * - * @brief Definitions for Motorola MC68302 Processor - * - * Section references in this file refer to revision 2 of Motorola's - * "MC68302 Integrated Multiprotocol Processor User's Manual". - * (Motorola document MC68302UM/AD REV 2.) - * - * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k - * on 17 February, 1993. - */ - -/* - * COPYRIGHT 1995 David W. Glessner. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above copyright notice, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - */ - -#ifndef _RTEMS_M68K_M68302_H -#define _RTEMS_M68K_M68302_H - -/* - * BAR - Base Address Register - * Section 2.7 - */ -#define M302_BAR (*((volatile uint16_t *) 0xf2)) - -/* - * SCR - System Control Register - * Section 3.8.1 - */ -#define M302_SCR (*((volatile uint32_t *) 0xf4)) -/* - * SCR bits - */ -#define RBIT_SCR_IPA 0x08000000 -#define RBIT_SCR_HWT 0x04000000 -#define RBIT_SCR_WPV 0x02000000 -#define RBIT_SCR_ADC 0x01000000 - -#define RBIT_SCR_ERRE 0x00400000 -#define RBIT_SCR_VGE 0x00200000 -#define RBIT_SCR_WPVE 0x00100000 -#define RBIT_SCR_RMCST 0x00080000 -#define RBIT_SCR_EMWS 0x00040000 -#define RBIT_SCR_ADCE 0x00020000 -#define RBIT_SCR_BCLM 0x00010000 - -#define RBIT_SCR_FRZW 0x00008000 -#define RBIT_SCR_FRZ2 0x00004000 -#define RBIT_SCR_FRZ1 0x00002000 -#define RBIT_SCR_SAM 0x00001000 -#define RBIT_SCR_HWDEN 0x00000800 -#define RBIT_SCR_HWDCN2 0x00000400 -#define RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */ -#define RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */ - -#define RBIT_SCR_LPREC 0x00000080 -#define RBIT_SCR_LPP16 0x00000040 -#define RBIT_SCR_LPEN 0x00000020 -#define RBIT_SCR_LPCLKDIV 0x0000001f - - -/* - * 68000 interrupt and trap vector numbers - */ -#define M68K_IVEC_BUS_ERROR 2 -#define M68K_IVEC_ADDRESS_ERROR 3 -#define M68K_IVEC_ILLEGAL_OPCODE 4 -#define M68K_IVEC_ZERO_DIVIDE 5 -#define M68K_IVEC_CHK 6 -#define M68K_IVEC_TRAPV 7 -#define M68K_IVEC_PRIVILEGE 8 -#define M68K_IVEC_TRACE 9 -#define M68K_IVEC_LINE_A 10 -#define M68K_IVEC_LINE_F 11 -/* Unassigned, Reserved 12-14 */ -#define M68K_IVEC_UNINITIALIZED_INT 15 -/* Unassigned, Reserved 16-23 */ -#define M68K_IVEC_SPURIOUS_INT 24 - -#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 -#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 -#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 -#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 -#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 -#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 -#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 - -#define M68K_IVEC_TRAP0 32 -#define M68K_IVEC_TRAP1 33 -#define M68K_IVEC_TRAP2 34 -#define M68K_IVEC_TRAP3 35 -#define M68K_IVEC_TRAP4 36 -#define M68K_IVEC_TRAP5 37 -#define M68K_IVEC_TRAP6 38 -#define M68K_IVEC_TRAP7 39 -#define M68K_IVEC_TRAP8 40 -#define M68K_IVEC_TRAP9 41 -#define M68K_IVEC_TRAP10 42 -#define M68K_IVEC_TRAP11 43 -#define M68K_IVEC_TRAP12 44 -#define M68K_IVEC_TRAP13 45 -#define M68K_IVEC_TRAP14 46 -#define M68K_IVEC_TRAP15 47 -/* - * Unassigned, Reserved 48-59 - * - * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). - */ - -/* - * MC68302 Interrupt Vectors - * Section 3.2 - */ -enum m68302_ivec_e { - M302_IVEC_ERR =0, - M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ - M302_IVEC_SMC2 =2, - M302_IVEC_SMC1 =3, - M302_IVEC_TIMER3 =4, - M302_IVEC_SCP =5, - M302_IVEC_TIMER2 =6, - M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ - M302_IVEC_SCC3 =8, - M302_IVEC_TIMER1 =9, - M302_IVEC_SCC2 =10, - M302_IVEC_IDMA =11, - M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ - M302_IVEC_SCC1 =13, - M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ - M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ - M302_IVEC_IRQ1 =17, /* External Device */ - M302_IVEC_IRQ6 =22, /* External Device */ - M302_IVEC_IRQ7 =23 /* External Device */ -}; - - -/* - * GIMR - Global Interrupt Mode Register - * Section 3.2.5.1 - */ -#define RBIT_GIMR_MOD (1<<15) -#define RBIT_GIMR_IV7 (1<<14) -#define RBIT_GIMR_IV6 (1<<13) -#define RBIT_GIMR_IV1 (1<<12) -#define RBIT_GIMR_ET7 (1<<10) -#define RBIT_GIMR_ET6 (1<<9) -#define RBIT_GIMR_ET1 (1<<8) -#define RBIT_GIMR_VECTOR (7<<5) - -/* - * IPR - Interrupt Pending Register (Section 3.2.5.2) - * IMR - Interrupt Mask Register (Section 3.2.5.3) - * ISR - Interrupt In-Service Register (Section 3.2.5.4) - */ -#define RBIT_IPR_PB11 (1<<15) -#define RBIT_IPR_PB10 (1<<14) -#define RBIT_IPR_SCC1 (1<<13) -#define RBIT_IPR_SDMA (1<<12) -#define RBIT_IPR_IDMA (1<<11) -#define RBIT_IPR_SCC2 (1<<10) -#define RBIT_IPR_TIMER1 (1<<9) -#define RBIT_IPR_SCC3 (1<<8) -#define RBIT_IPR_PB9 (1<<7) -#define RBIT_IPR_TIMER2 (1<<6) -#define RBIT_IPR_SCP (1<<5) -#define RBIT_IPR_TIMER3 (1<<4) -#define RBIT_IPR_SMC1 (1<<3) -#define RBIT_IPR_SMC2 (1<<2) -#define RBIT_IPR_PB8 (1<<1) -#define RBIT_IPR_ERR (1<<0) - -#define RBIT_ISR_PB11 (1<<15) -#define RBIT_ISR_PB10 (1<<14) -#define RBIT_ISR_SCC1 (1<<13) -#define RBIT_ISR_SDMA (1<<12) -#define RBIT_ISR_IDMA (1<<11) -#define RBIT_ISR_SCC2 (1<<10) -#define RBIT_ISR_TIMER1 (1<<9) -#define RBIT_ISR_SCC3 (1<<8) -#define RBIT_ISR_PB9 (1<<7) -#define RBIT_ISR_TIMER2 (1<<6) -#define RBIT_ISR_SCP (1<<5) -#define RBIT_ISR_TIMER3 (1<<4) -#define RBIT_ISR_SMC1 (1<<3) -#define RBIT_ISR_SMC2 (1<<2) -#define RBIT_ISR_PB8 (1<<1) - -#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ -#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ -#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ -#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ -#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ -#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ -#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ -#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ -#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ -#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ -#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ -#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ -#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ -#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ -#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ - - -/* - * DRAM Refresh - * Section 3.9 - * - * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 - * structures in the parameter RAM. - * - * Access to the DRAM registers can be accomplished by - * the following approach: - * - * volatile m302_DRAM_refresh_t *dram; - * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; - * - * Then simply use pointer references (e.g. dram->count = 3). - */ -typedef struct { - uint16_t dram_high; /* DRAM high address and FC */ - uint16_t dram_low; /* DRAM low address */ - uint16_t increment; /* increment step (bytes/row) */ - uint16_t count; /* RAM refresh cycle count (#rows) */ - uint16_t t_ptr_h; /* temporary refresh high addr & FC */ - uint16_t t_ptr_l; /* temporary refresh low address */ - uint16_t t_count; /* temporary refresh cycles count */ - uint16_t res; /* reserved */ -} m302_DRAM_refresh_t; - - -/* - * TMR - Timer Mode Register (for timers 1 and 2) - * Section 3.5.2.1 - */ -#define RBIT_TMR_ICLK_STOP (0<<1) -#define RBIT_TMR_ICLK_MASTER (1<<1) -#define RBIT_TMR_ICLK_MASTER16 (2<<1) -#define RBIT_TMR_ICLK_TIN (3<<1) - -#define RBIT_TMR_OM (1<<5) -#define RBIT_TMR_ORI (1<<4) -#define RBIT_TMR_FRR (1<<3) -#define RBIT_TMR_RST (1<<0) - - -/* - * TER - Timer Event Register (for timers 1 and 2) - * Section 3.5.2.5 - */ -#define RBIT_TER_REF (1<<1) /* Output Reference Event */ -#define RBIT_TER_CAP (1<<0) /* Capture Event */ - - -/* - * SCC Buffer Descriptors and Buffer Descriptors Table - * Section 4.5.5 - */ -typedef struct m302_SCC_bd { - uint16_t status; /* status and control */ - uint16_t length; /* data length */ - volatile uint8_t *buffer; /* data buffer pointer */ -} m302_SCC_bd_t; - -typedef struct { - m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ - m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ -} m302_SCC_bd_table_t; - - -/* - * SCC Parameter RAM (offset 0x080 from an SCC Base) - * Section 4.5.6 - * - * Each SCC parameter RAM area begins at offset 0x80 from each SCC base - * area (0x400, 0x500, or 0x600 from the dual-port RAM base). - * - * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific - * portion of the SCC parameter RAM. - */ -typedef struct { - uint8_t rfcr; /* Rx Function Code */ - uint8_t tfcr; /* Tx Function Code */ - uint16_t mrblr; /* Maximum Rx Buffer Length */ - uint16_t _rstate; /* Rx Internal State */ - uint8_t res2; - uint8_t rbd; /* Rx Internal Buffer Number */ - uint32_t _rdptr; /* Rx Internal Data Pointer */ - uint16_t _rcount; /* Rx Internal Byte Count */ - uint16_t _rtmp; /* Rx Temp */ - uint16_t _tstate; /* Tx Internal State */ - uint8_t res7; - uint8_t tbd; /* Tx Internal Buffer Number */ - uint32_t _tdptr; /* Tx Internal Data Pointer */ - uint16_t _tcount; /* Tx Internal Byte Count */ - uint16_t _ttmp; /* Tx Temp */ -} m302_SCC_parameters_t; - -/* - * UART-Specific SCC Parameter RAM - * Section 4.5.11.3 - */ -typedef struct { - uint16_t max_idl; /* Maximum IDLE Characters (rx) */ - uint16_t idlc; /* Temporary rx IDLE counter */ - uint16_t brkcr; /* Break Count Register (tx) */ - uint16_t parec; /* Receive Parity Error Counter */ - uint16_t frmec; /* Receive Framing Error Counter */ - uint16_t nosec; /* Receive Noise Counter */ - uint16_t brkec; /* Receive Break Condition Counter */ - uint16_t uaddr1; /* UART ADDRESS Character 1 */ - uint16_t uaddr2; /* UART ADDRESS Character 2 */ - uint16_t rccr; /* Receive Control Character Register */ - uint16_t character[8]; /* Control Characters 1 through 8*/ -} m302_SCC_UartSpecific_t; -/* - * This definition allows for the checking of receive buffers - * for errors. - */ - -#define RCV_ERR 0x003F - -/* - * UART receive buffer descriptor bit definitions. - * Section 4.5.11.14 - */ -#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ -#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ -#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ -#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ -#define RBIT_UART_BR (1<<5) /* break sequence was received */ -#define RBIT_UART_FR (1<<4) /* framing error was received */ -#define RBIT_UART_PR (1<<3) /* parity error was received */ -#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ -#define RBIT_UART_CD (1<<0) /* carrier detect lost */ -#define RBIT_UART_STATUS 0x003B /* all status bits */ - -/* - * UART transmit buffer descriptor bit definitions. - * Section 4.5.11.15 - */ -#define RBIT_UART_CR (1<<11) /* clear-to-send report - * this results in two idle bits - * between back-to-back frames - */ -#define RBIT_UART_A (1<<10) /* buffer contains address characters - * only valid in multidrop mode (UM0=1) - */ -#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ -#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ - -/* - * UART event register - * Section 4.5.11.16 - */ -#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ -#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ -#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ -#define M302_UART_EV_BRK (1<<4) /* break character was received */ -#define M302_UART_EV_CCR (1<<3) /* control character received */ -#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ -#define M302_UART_EV_RX (1<<0) /* buffer has been received */ - - -/* - * HDLC-Specific SCC Parameter RAM - * Section 4.5.12.3 - * - * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC - * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC - */ -typedef struct { - uint16_t rcrc_l; /* Temp Receive CRC Low */ - uint16_t rcrc_h; /* Temp Receive CRC High */ - uint16_t c_mask_l; /* CRC Mask Low */ - uint16_t c_mask_h; /* CRC Mask High */ - uint16_t tcrc_l; /* Temp Transmit CRC Low */ - uint16_t tcrc_h; /* Temp Transmit CRC High */ - - uint16_t disfc; /* Discard Frame Counter */ - uint16_t crcec; /* CRC Error Counter */ - uint16_t abtsc; /* Abort Sequence Counter */ - uint16_t nmarc; /* Nonmatching Address Received Cntr */ - uint16_t retrc; /* Frame Retransmission Counter */ - - uint16_t mflr; /* Maximum Frame Length Register */ - uint16_t max_cnt; /* Maximum_Length Counter */ - - uint16_t hmask; /* User Defined Frame Address Mask */ - uint16_t haddr1; /* User Defined Frame Address */ - uint16_t haddr2; /* " */ - uint16_t haddr3; /* " */ - uint16_t haddr4; /* " */ -} m302_SCC_HdlcSpecific_t; -/* - * HDLC receiver buffer descriptor bit definitions - * Section 4.5.12.10 - */ -#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ -#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ -#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ -#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ -#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ -#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ -#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ -#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ - -/* - * HDLC transmit buffer descriptor bit definitions - * Section 4.5.12.11 - */ -#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ -#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ -#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ -#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ -#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ -#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ -#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ - -/* - * HDLC event register bit definitions - * Section 4.5.12.12 - */ -#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ -#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ -#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ -#define RBIT_HDLC_TXE 0x10 /* transmit error */ -#define RBIT_HDLC_RXF 0x08 /* received frame */ -#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to - * lack of buffers - */ -#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ -#define RBIT_HDLC_RXB 0x01 /* received buffer */ - - - -typedef struct { - m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ - m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ - union { /* +09C Protocol-Specific Parm RAM */ - m302_SCC_UartSpecific_t uart; - m302_SCC_HdlcSpecific_t hdlc; - } prot; - uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */ -} m302_SCC_t; - - -/* - * Common SCC Registers - */ -typedef struct { - uint16_t res1; - uint16_t scon; /* SCC Configuration Register 4.5.2 */ - uint16_t scm; /* SCC Mode Register 4.5.3 */ - uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */ - uint8_t scce; /* SCC Event Register 4.5.8.1 */ - uint8_t res2; - uint8_t sccm; /* SCC Mask Register 4.5.8.2 */ - uint8_t res3; - uint8_t sccs; /* SCC Status Register 4.5.8.3 */ - uint8_t res4; - uint16_t res5; -} m302_SCC_Registers_t; - -/* - * SCON - SCC Configuration Register - * Section 4.5.2 - */ -#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) - * When set, the TXD driver is an - * open-drain output */ -#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ -#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ -#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ - -/* - * SCM - SCC Mode Register bit definitions - * Section 4.5.3 - * The parameter-specific mode bits occupy bits 15 through 6. - */ -#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ -#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ - - -/* - * Internal MC68302 Registers - * starts at offset 0x800 from dual-port RAM base - * Section 2.8 - */ -typedef struct { - /* offset +800 */ - uint16_t res0; - uint16_t cmr; /* IDMA Channel Mode Register */ - uint32_t sapr; /* IDMA Source Address Pointer */ - uint32_t dapr; /* IDMA Destination Address Pointer */ - uint16_t bcr; /* IDMA Byte Count Register */ - uint8_t csr; /* IDMA Channel Status Register */ - uint8_t res1; - uint8_t fcr; /* IDMA Function Code Register */ - uint8_t res2; - - /* offset +812 */ - uint16_t gimr; /* Global Interrupt Mode Register */ - uint16_t ipr; /* Interrupt Pending Register */ - uint16_t imr; /* Interrupt Mask Register */ - uint16_t isr; /* Interrupt In-Service Register */ - uint16_t res3; - uint16_t res4; - - /* offset +81e */ - uint16_t pacnt; /* Port A Control Register */ - uint16_t paddr; /* Port A Data Direction Register */ - uint16_t padat; /* Port A Data Register */ - uint16_t pbcnt; /* Port B Control Register */ - uint16_t pbddr; /* Port B Data Direction Register */ - uint16_t pbdat; /* Port B Data Register */ - uint16_t res5; - - /* offset +82c */ - uint16_t res6; - uint16_t res7; - - uint16_t br0; /* Base Register (CS0) */ - uint16_t or0; /* Option Register (CS0) */ - uint16_t br1; /* Base Register (CS1) */ - uint16_t or1; /* Option Register (CS1) */ - uint16_t br2; /* Base Register (CS2) */ - uint16_t or2; /* Option Register (CS2) */ - uint16_t br3; /* Base Register (CS3) */ - uint16_t or3; /* Option Register (CS3) */ - - /* offset +840 */ - uint16_t tmr1; /* Timer Unit 1 Mode Register */ - uint16_t trr1; /* Timer Unit 1 Reference Register */ - uint16_t tcr1; /* Timer Unit 1 Capture Register */ - uint16_t tcn1; /* Timer Unit 1 Counter */ - uint8_t res8; - uint8_t ter1; /* Timer Unit 1 Event Register */ - uint16_t wrr; /* Watchdog Reference Register */ - uint16_t wcn; /* Watchdog Counter */ - uint16_t res9; - uint16_t tmr2; /* Timer Unit 2 Mode Register */ - uint16_t trr2; /* Timer Unit 2 Reference Register */ - uint16_t tcr2; /* Timer Unit 2 Capture Register */ - uint16_t tcn2; /* Timer Unit 2 Counter */ - uint8_t resa; - uint8_t ter2; /* Timer Unit 2 Event Register */ - uint16_t resb; - uint16_t resc; - uint16_t resd; - - /* offset +860 */ - uint8_t cr; /* Command Register */ - uint8_t rese[0x1f]; - - /* offset +880, +890, +8a0 */ - m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ - - /* offset +8b0 */ - uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ - uint16_t simask; /* Serial Interface Mask Register */ - uint16_t simode; /* Serial Interface Mode Register */ -} m302_internalReg_t ; - - -/* - * MC68302 dual-port RAM structure. - * (Includes System RAM, Parameter RAM, and Internal Registers). - * Section 2.8 - */ -typedef struct { - uint8_t mem[0x240]; /* +000 User Data Memory */ - uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */ - m302_SCC_t scc1; /* +400 SCC1 */ - m302_SCC_t scc2; /* +500 SCC2 */ - m302_SCC_t scc3; /* +600 SCC3 */ - uint8_t res2[0x100]; /* +700 reserved, (not implemented) */ - m302_internalReg_t reg; /* +800 68302 Internal Registers */ -} m302_dualPortRAM_t; - -/* some useful defines the some of the registers above */ - - -/* ---- - MC68302 Chip Select Registers - p3-46 2nd Edition - - */ -#define BR_ENABLED 1 -#define BR_DISABLED 0 -#define BR_FC_NULL 0 -#define BR_READ_ONLY 0 -#define BR_READ_WRITE 2 -#define OR_DTACK_0 0x0000 -#define OR_DTACK_1 0x2000 -#define OR_DTACK_2 0x4000 -#define OR_DTACK_3 0x6000 -#define OR_DTACK_4 0x8000 -#define OR_DTACK_5 0xA000 -#define OR_DTACK_6 0xC000 -#define OR_DTACK_EXT 0xE000 -#define OR_SIZE_64K 0x1FE0 -#define OR_SIZE_128K 0x1FC0 -#define OR_SIZE_256K 0x1F80 -#define OR_SIZE_512K 0x1F00 -#define OR_SIZE_1M 0x1E00 -#define OR_SIZE_2M 0x1C00 -#define OR_MASK_RW 0x0000 -#define OR_NO_MASK_RW 0x0002 -#define OR_MASK_FC 0x0000 -#define OR_NO_MASK_FC 0x0001 - -#define MAKE_BR(base_address, enable, rw, fc) \ - ((base_address >> 11) | fc | rw | enable) - -#define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \ - (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask) - -#define __REG_CAT(r, n) r ## n -#define WRITE_BR(csel, base_address, enable, rw, fc) \ - __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc) -#define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \ - __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) - -/* ---- - MC68302 Watchdog Timer Enable Bit - - */ -#define WATCHDOG_ENABLE (1) -#define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0) -#define WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD) -#define DISABLE_WATCHDOG() (m302.reg.wrr = 0) - -/* - * Declare the variable that's used to reference the variables in - * the dual-port RAM. - */ -extern volatile m302_dualPortRAM_t m302; - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68360.h b/cpukit/score/cpu/m68k/rtems/m68k/m68360.h deleted file mode 100644 index dc181d0cdf..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/m68360.h +++ /dev/null @@ -1,899 +0,0 @@ -/** - * @file - * - * @brief Definitions for Motorola MC68360 Processor - */ -/* - ************************************************************************** - ************************************************************************** - ** ** - ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) ** - ** ** - ** HARDWARE DECLARATIONS ** - ** ** - ** ** - ** Submitted By: ** - ** ** - ** W. Eric Norum ** - ** Saskatchewan Accelerator Laboratory ** - ** University of Saskatchewan ** - ** 107 North Road ** - ** Saskatoon, Saskatchewan, CANADA ** - ** S7N 5C6 ** - ** ** - ** eric@skatter.usask.ca ** - ** ** - ************************************************************************** - ************************************************************************** - */ - -#ifndef _RTEMS_M68K_M68360_H -#define _RTEMS_M68K_M68360_H - -/* - ************************************************************************* - * REGISTER SUBBLOCKS * - ************************************************************************* - */ - -/* - * Memory controller registers - */ -typedef struct m360MEMCRegisters_ { - unsigned long br; - unsigned long or; - unsigned long _pad[2]; -} m360MEMCRegisters_t; - -/* - * Serial Communications Controller registers - */ -typedef struct m360SCCRegisters_ { - unsigned long gsmr_l; - unsigned long gsmr_h; - unsigned short psmr; - unsigned short _pad0; - unsigned short todr; - unsigned short dsr; - unsigned short scce; - unsigned short _pad1; - unsigned short sccm; - unsigned char _pad2; - unsigned char sccs; - unsigned long _pad3[2]; -} m360SCCRegisters_t; - -/* - * Serial Management Controller registers - */ -typedef struct m360SMCRegisters_ { - unsigned short _pad0; - unsigned short smcmr; - unsigned short _pad1; - unsigned char smce; - unsigned char _pad2; - unsigned short _pad3; - unsigned char smcm; - unsigned char _pad4; - unsigned long _pad5; -} m360SMCRegisters_t; - - -/* - ************************************************************************* - * Miscellaneous Parameters * - ************************************************************************* - */ -typedef struct m360MiscParms_ { - unsigned short rev_num; - unsigned short _res1; - unsigned long _res2; - unsigned long _res3; -} m360MiscParms_t; - -/* - ************************************************************************* - * RISC Timers * - ************************************************************************* - */ -typedef struct m360TimerParms_ { - unsigned short tm_base; - unsigned short _tm_ptr; - unsigned short _r_tmr; - unsigned short _r_tmv; - unsigned long tm_cmd; - unsigned long tm_cnt; -} m360TimerParms_t; - -/* - * RISC Controller Configuration Register (RCCR) - * All other bits in this register are either reserved or - * used only with a Motorola-supplied RAM microcode packge. - */ -#define M360_RCCR_TIME (1<<15) /* Enable timer */ -#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ - -/* - * Command register - * Set up this register before issuing a M360_CR_OP_SET_TIMER command. - */ -#define M360_TM_CMD_V (1<<31) /* Set to enable timer */ -#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */ -#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ -#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ - -/* - ************************************************************************* - * DMA Controllers * - ************************************************************************* - */ -typedef struct m360IDMAparms_ { - unsigned short ibase; - unsigned short ibptr; - unsigned long _istate; - unsigned long _itemp; -} m360IDMAparms_t; - -/* - ************************************************************************* - * Serial Communication Controllers * - ************************************************************************* - */ -typedef struct m360SCCparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; - unsigned long _rcrc; - unsigned long _tcrc; - union { - struct { - unsigned long _res0; - unsigned long _res1; - unsigned short max_idl; - unsigned short _idlc; - unsigned short brkcr; - unsigned short parec; - unsigned short frmec; - unsigned short nosec; - unsigned short brkec; - unsigned short brklen; - unsigned short uaddr[2]; - unsigned short _rtemp; - unsigned short toseq; - unsigned short character[8]; - unsigned short rccm; - unsigned short rccr; - unsigned short rlbc; - } uart; - struct { - unsigned long crc_p; - unsigned long crc_c; - } transparent; - - } un; -} m360SCCparms_t; - -typedef struct m360SCCENparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; - unsigned long _rcrc; - unsigned long _tcrc; - union { - struct { - unsigned long _res0; - unsigned long _res1; - unsigned short max_idl; - unsigned short _idlc; - unsigned short brkcr; - unsigned short parec; - unsigned short frmec; - unsigned short nosec; - unsigned short brkec; - unsigned short brklen; - unsigned short uaddr[2]; - unsigned short _rtemp; - unsigned short toseq; - unsigned short character[8]; - unsigned short rccm; - unsigned short rccr; - unsigned short rlbc; - } uart; - struct { - unsigned long c_pres; - unsigned long c_mask; - unsigned long crcec; - unsigned long alec; - unsigned long disfc; - unsigned short pads; - unsigned short ret_lim; - unsigned short _ret_cnt; - unsigned short mflr; - unsigned short minflr; - unsigned short maxd1; - unsigned short maxd2; - unsigned short _maxd; - unsigned short dma_cnt; - unsigned short _max_b; - unsigned short gaddr1; - unsigned short gaddr2; - unsigned short gaddr3; - unsigned short gaddr4; - unsigned long _tbuf0data0; - unsigned long _tbuf0data1; - unsigned long _tbuf0rba0; - unsigned long _tbuf0crc; - unsigned short _tbuf0bcnt; - unsigned short paddr_h; - unsigned short paddr_m; - unsigned short paddr_l; - unsigned short p_per; - unsigned short _rfbd_ptr; - unsigned short _tfbd_ptr; - unsigned short _tlbd_ptr; - unsigned long _tbuf1data0; - unsigned long _tbuf1data1; - unsigned long _tbuf1rba0; - unsigned long _tbuf1crc; - unsigned short _tbuf1bcnt; - unsigned short _tx_len; - unsigned short iaddr1; - unsigned short iaddr2; - unsigned short iaddr3; - unsigned short iaddr4; - unsigned short _boff_cnt; - unsigned short taddr_h; - unsigned short taddr_m; - unsigned short taddr_l; - } ethernet; - struct { - unsigned long crc_p; - unsigned long crc_c; - } transparent; - } un; -} m360SCCENparms_t; - -/* - * Receive and transmit function code register bits - * These apply to the function code registers of all devices, not just SCC. - */ -#define M360_RFCR_MOT (1<<4) -#define M360_RFCR_DMA_SPACE 0x8 -#define M360_TFCR_MOT (1<<4) -#define M360_TFCR_DMA_SPACE 0x8 - -/* - ************************************************************************* - * Serial Management Controllers * - ************************************************************************* - */ -typedef struct m360SMCparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; - union { - struct { - unsigned short max_idl; - unsigned short _pad0; - unsigned short brklen; - unsigned short brkec; - unsigned short brkcr; - unsigned short _r_mask; - } uart; - struct { - unsigned short _pad0[5]; - } transparent; - } un; -} m360SMCparms_t; - -/* - * Mode register - */ -#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */ -#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */ -#define M360_SMCMR_PARITY (1<<9) /* Enable parity */ -#define M360_SMCMR_EVEN (1<<8) /* Even parity */ -#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */ -#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */ -#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ -#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ -#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */ -#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */ -#define M360_SMCMR_REN (1<<0) /* Enable receiver */ - -/* - * Event and mask registers (SMCE, SMCM) - */ -#define M360_SMCE_BRK (1<<4) -#define M360_SMCE_BSY (1<<2) -#define M360_SMCE_TX (1<<1) -#define M360_SMCE_RX (1<<0) - -/* - ************************************************************************* - * Serial Peripheral Interface * - ************************************************************************* - */ -typedef struct m360SPIparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; -} m360SPIparms_t; - -/* - * Mode register (SPMODE) - */ -#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */ -#define M360_SPMODE_CI (1<<13) /* Clock invert */ -#define M360_SPMODE_CP (1<<12) /* Clock phase */ -#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ -#define M360_SPMODE_REV (1<<10) /* Reverse data */ -#define M360_SPMODE_MASTER (1<<9) /* SPI is master */ -#define M360_SPMODE_EN (1<<8) /* Enable SPI */ -#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */ -#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */ - -/* - * Mode register (SPCOM) - */ -#define M360_SPCOM_STR (1<<7) /* Start transmit */ - -/* - * Event and mask registers (SPIE, SPIM) - */ -#define M360_SPIE_MME (1<<5) /* Multi-master error */ -#define M360_SPIE_TXE (1<<4) /* Tx error */ -#define M360_SPIE_BSY (1<<2) /* Busy condition*/ -#define M360_SPIE_TXB (1<<1) /* Tx buffer */ -#define M360_SPIE_RXB (1<<0) /* Rx buffer */ - -/* - ************************************************************************* - * SDMA (SCC, SMC, SPI) Buffer Descriptors * - ************************************************************************* - */ -typedef struct m360BufferDescriptor_ { - unsigned short status; - unsigned short length; - volatile void *buffer; -} m360BufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M360_BD_ADDRESS (1<<10) /* SCC UART */ -#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M360_BD_MISS (1<<8) /* Ethernet */ -#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M360_BD_LONG (1<<5) /* Ethernet */ -#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M360_BD_NONALIGNED (1<<4) /* Ethernet */ -#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M360_BD_SHORT (1<<3) /* Ethernet */ -#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */ -#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_COLLISION (1<<0) /* Ethernet */ -#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */ -#define M360_BD_MASTER_ERROR (1<<0) /* SPI */ - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_PAD (1<<14) /* Ethernet */ -#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M360_BD_TX_CRC (1<<10) /* Ethernet */ -#define M360_BD_DEFER (1<<9) /* Ethernet */ -#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ -#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M360_BD_CTS_LOST (1<<0) /* SCC UART */ - -/* - ************************************************************************* - * IDMA Buffer Descriptors * - ************************************************************************* - */ -typedef struct m360IDMABufferDescriptor_ { - unsigned short status; - unsigned short _pad; - unsigned long length; - void *source; - void *destination; -} m360IDMABufferDescriptor_t; - -/* - ************************************************************************* - * RISC Communication Processor Module Command Register (CR) * - ************************************************************************* - */ -#define M360_CR_RST (1<<15) /* Reset communication processor */ -#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ -#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ -#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ -#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ -#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ -#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */ -#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */ -#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ -#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ -#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ -#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */ -#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ -#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */ -#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ -#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */ -#define M360_CR_CHAN_SCC2 (4<<4) -#define M360_CR_CHAN_SPI (5<<4) -#define M360_CR_CHAN_TIMER (5<<4) -#define M360_CR_CHAN_SCC3 (8<<4) -#define M360_CR_CHAN_SMC1 (9<<4) -#define M360_CR_CHAN_IDMA1 (9<<4) -#define M360_CR_CHAN_SCC4 (12<<4) -#define M360_CR_CHAN_SMC2 (13<<4) -#define M360_CR_CHAN_IDMA2 (13<<4) -#define M360_CR_FLG (1<<0) /* Command flag */ - -/* - ************************************************************************* - * System Protection Control Register (SYPCR) * - ************************************************************************* - */ -#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */ -#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */ -#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */ -#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */ -#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */ -#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */ -#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */ -#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */ - -/* - ************************************************************************* - * Memory Control Registers * - ************************************************************************* - */ -#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */ -#define M360_GMR_RFEN (1<<23) /* Refresh enable */ -#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */ -#define M360_GMR_PGS(x) ((x)<<18) /* Page size */ -#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */ -#define M360_GMR_DPS_16BIT (1<<16) -#define M360_GMR_DPS_8BIT (2<<16) -#define M360_GMR_DPS_DSACK (3<<16) -#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */ -#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */ -#define M360_GMR_SYNC (1<<13) /* Synchronous external access */ -#define M360_GMR_EMWS (1<<12) /* External master wait state */ -#define M360_GMR_OPAR (1<<11) /* Odd parity */ -#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */ -#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */ -#define M360_GMR_NCS (1<<8) /* No CPU space */ -#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */ -#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */ -#define M360_GMR_GAMX (1<<5) /* Global address mux enable */ - -#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */ -#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */ -#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */ -#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */ -#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */ -#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */ -#define M360_MEMC_BR_WP (1<<1) /* Write Protect */ -#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */ -#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1) -#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */ -#define M360_MEMC_OR_4KB 0x0FFFF000 -#define M360_MEMC_OR_8KB 0x0FFFE000 -#define M360_MEMC_OR_16KB 0x0FFFC000 -#define M360_MEMC_OR_32KB 0x0FFF8000 -#define M360_MEMC_OR_64KB 0x0FFF0000 -#define M360_MEMC_OR_128KB 0x0FFE0000 -#define M360_MEMC_OR_256KB 0x0FFC0000 -#define M360_MEMC_OR_512KB 0x0FF80000 -#define M360_MEMC_OR_1MB 0x0FF00000 -#define M360_MEMC_OR_2MB 0x0FE00000 -#define M360_MEMC_OR_4MB 0x0FC00000 -#define M360_MEMC_OR_8MB 0x0F800000 -#define M360_MEMC_OR_16MB 0x0F000000 -#define M360_MEMC_OR_32MB 0x0E000000 -#define M360_MEMC_OR_64MB 0x0C000000 -#define M360_MEMC_OR_128MB 0x08000000 -#define M360_MEMC_OR_256MB 0x00000000 -#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */ -#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */ -#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */ -#define M360_MEMC_OR_32BIT (0<<1) /* Port size */ -#define M360_MEMC_OR_16BIT (1<<1) -#define M360_MEMC_OR_8BIT (2<<1) -#define M360_MEMC_OR_DSACK (3<<1) -#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */ - -/* - ************************************************************************* - * SI Mode Register (SIMODE) * - ************************************************************************* - */ -#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ -#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ -#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ -#define M360_SI_SMC2_BRG2 (1<<28) -#define M360_SI_SMC2_BRG3 (2<<28) -#define M360_SI_SMC2_BRG4 (3<<28) -#define M360_SI_SMC2_CLK5 (0<<28) -#define M360_SI_SMC2_CLK6 (1<<28) -#define M360_SI_SMC2_CLK7 (2<<28) -#define M360_SI_SMC2_CLK8 (3<<28) -#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ -#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ -#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ -#define M360_SI_SMC1_BRG2 (1<<12) -#define M360_SI_SMC1_BRG3 (2<<12) -#define M360_SI_SMC1_BRG4 (3<<12) -#define M360_SI_SMC1_CLK1 (0<<12) -#define M360_SI_SMC1_CLK2 (1<<12) -#define M360_SI_SMC1_CLK3 (2<<12) -#define M360_SI_SMC1_CLK4 (3<<12) - -/* - ************************************************************************* - * SDMA Configuration Register (SDMA) * - ************************************************************************* - */ -#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */ -#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */ -#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */ -#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */ -#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */ - -/* - ************************************************************************* - * Baud (sic) Rate Generators * - ************************************************************************* - */ -#define M360_BRG_RST (1<<17) /* Reset generator */ -#define M360_BRG_EN (1<<16) /* Enable generator */ -#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ -#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ -#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ -#define M360_BRG_ATB (1<<13) /* Autobaud */ -#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */ -#define M360_BRG_57600 (26<<1) -#define M360_BRG_38400 (40<<1) -#define M360_BRG_19200 (80<<1) -#define M360_BRG_9600 (162<<1) -#define M360_BRG_4800 (324<<1) -#define M360_BRG_2400 (650<<1) -#define M360_BRG_1200 (1301<<1) -#define M360_BRG_600 (2603<<1) -#define M360_BRG_300 ((324<<1) | 1) -#define M360_BRG_150 ((650<<1) | 1) -#define M360_BRG_75 ((1301<<1) | 1) - -/* - ************************************************************************* - * MC68360 DUAL-PORT RAM AND REGISTERS * - ************************************************************************* - */ -typedef struct m360_ { - /* - * Dual-port RAM - */ - unsigned char dpram0[0x400]; /* Microcode program */ - unsigned char dpram1[0x200]; - unsigned char dpram2[0x100]; /* Microcode scratch */ - unsigned char dpram3[0x100]; /* Not on REV A or B masks */ - unsigned char _rsv0[0xC00-0x800]; - m360SCCENparms_t scc1p; - unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)]; - m360MiscParms_t miscp; - unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)]; - m360SCCparms_t scc2p; - unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)]; - m360SPIparms_t spip; - unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)]; - m360TimerParms_t tmp; - unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)]; - m360SCCparms_t scc3p; - unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)]; - m360IDMAparms_t idma1p; - unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)]; - m360SMCparms_t smc1p; - unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)]; - m360SCCparms_t scc4p; - unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)]; - m360IDMAparms_t idma2p; - unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)]; - m360SMCparms_t smc2p; - unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)]; - - /* - * SIM Block - */ - unsigned long mcr; - unsigned long _pad00; - unsigned char avr; - unsigned char rsr; - unsigned short _pad01; - unsigned char clkocr; - unsigned char _pad02; - unsigned short _pad03; - unsigned short pllcr; - unsigned short _pad04; - unsigned short cdvcr; - unsigned short pepar; - unsigned long _pad05[2]; - unsigned short _pad06; - unsigned char sypcr; - unsigned char swiv; - unsigned short _pad07; - unsigned short picr; - unsigned short _pad08; - unsigned short pitr; - unsigned short _pad09; - unsigned char _pad10; - unsigned char swsr; - unsigned long bkar; - unsigned long bcar; - unsigned long _pad11[2]; - - /* - * MEMC Block - */ - unsigned long gmr; - unsigned short mstat; - unsigned short _pad12; - unsigned long _pad13[2]; - m360MEMCRegisters_t memc[8]; - unsigned char _pad14[0xF0-0xD0]; - unsigned char _pad15[0x100-0xF0]; - unsigned char _pad16[0x500-0x100]; - - /* - * IDMA1 Block - */ - unsigned short iccr; - unsigned short _pad17; - unsigned short cmr1; - unsigned short _pad18; - unsigned long sapr1; - unsigned long dapr1; - unsigned long bcr1; - unsigned char fcr1; - unsigned char _pad19; - unsigned char cmar1; - unsigned char _pad20; - unsigned char csr1; - unsigned char _pad21; - unsigned short _pad22; - - /* - * SDMA Block - */ - unsigned char sdsr; - unsigned char _pad23; - unsigned short sdcr; - unsigned long sdar; - - /* - * IDMA2 Block - */ - unsigned short _pad24; - unsigned short cmr2; - unsigned long sapr2; - unsigned long dapr2; - unsigned long bcr2; - unsigned char fcr2; - unsigned char _pad26; - unsigned char cmar2; - unsigned char _pad27; - unsigned char csr2; - unsigned char _pad28; - unsigned short _pad29; - unsigned long _pad30; - - /* - * CPIC Block - */ - unsigned long cicr; - unsigned long cipr; - unsigned long cimr; - unsigned long cisr; - - /* - * Parallel I/O Block - */ - unsigned short padir; - unsigned short papar; - unsigned short paodr; - unsigned short padat; - unsigned long _pad31[2]; - unsigned short pcdir; - unsigned short pcpar; - unsigned short pcso; - unsigned short pcdat; - unsigned short pcint; - unsigned short _pad32; - unsigned long _pad33[5]; - - /* - * TIMER Block - */ - unsigned short tgcr; - unsigned short _pad34; - unsigned long _pad35[3]; - unsigned short tmr1; - unsigned short tmr2; - unsigned short trr1; - unsigned short trr2; - unsigned short tcr1; - unsigned short tcr2; - unsigned short tcn1; - unsigned short tcn2; - unsigned short tmr3; - unsigned short tmr4; - unsigned short trr3; - unsigned short trr4; - unsigned short tcr3; - unsigned short tcr4; - unsigned short tcn3; - unsigned short tcn4; - unsigned short ter1; - unsigned short ter2; - unsigned short ter3; - unsigned short ter4; - unsigned long _pad36[2]; - - /* - * CP Block - */ - unsigned short cr; - unsigned short _pad37; - unsigned short rccr; - unsigned short _pad38; - unsigned long _pad39[3]; - unsigned short _pad40; - unsigned short rter; - unsigned short _pad41; - unsigned short rtmr; - unsigned long _pad42[5]; - - /* - * BRG Block - */ - unsigned long brgc1; - unsigned long brgc2; - unsigned long brgc3; - unsigned long brgc4; - - /* - * SCC Block - */ - m360SCCRegisters_t scc1; - m360SCCRegisters_t scc2; - m360SCCRegisters_t scc3; - m360SCCRegisters_t scc4; - - /* - * SMC Block - */ - m360SMCRegisters_t smc1; - m360SMCRegisters_t smc2; - - /* - * SPI Block - */ - unsigned short spmode; - unsigned short _pad43[2]; - unsigned char spie; - unsigned char _pad44; - unsigned short _pad45; - unsigned char spim; - unsigned char _pad46[2]; - unsigned char spcom; - unsigned short _pad47[2]; - - /* - * PIP Block - */ - unsigned short pipc; - unsigned short _pad48; - unsigned short ptpr; - unsigned long pbdir; - unsigned long pbpar; - unsigned short _pad49; - unsigned short pbodr; - unsigned long pbdat; - unsigned long _pad50[6]; - - /* - * SI Block - */ - unsigned long simode; - unsigned char sigmr; - unsigned char _pad51; - unsigned char sistr; - unsigned char sicmr; - unsigned long _pad52; - unsigned long sicr; - unsigned short _pad53; - unsigned short sirp[2]; - unsigned short _pad54; - unsigned long _pad55[2]; - unsigned char siram[256]; -} m360_t; - -extern volatile m360_t m360; - -/* - * definitions for the port b SPI pin bits - */ -#define M360_PB_SPI_MISO_MSK (1<< 3) -#define M360_PB_SPI_MOSI_MSK (1<< 2) -#define M360_PB_SPI_CLK_MSK (1<< 1) - -#endif /* _RTEMS_M68K_M68360_H */ diff --git a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h deleted file mode 100644 index 32dbc1d5f9..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K Queued Serial Module - * - * The QSM contains two serial interfaces: (a) the queued serial - * peripheral interface (QSPI) and the serial communication interface - * (SCI). The QSPI provides peripheral expansion and/or interprocessor - * communication through a full-duplex, synchronous, three-wire bus. A - * self contained RAM queue permits serial data transfers without CPU - * intervention and automatic continuous sampling. The SCI provides a - * standard non-return to zero mark/space format with wakeup functions - * to allow the CPU to run uninterrupted until woken - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family Queued Serial Module Reference Manual" (Motorola document - * QSMRM/AD). - */ - -/* - * This file was created by John S. Gwynne to support Motorola's 68332 MCU. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - */ - -#ifndef _RTEMS_M68K_QSM_H -#define _RTEMS_M68K_QSM_H - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - - -/* QSM_CRB (QSM Control Register Block) base address of the QSM - control registers */ -#if SIM_MM == 0 -#define QSM_CRB 0x7ffc00 -#else -#undef SIM_MM -#define SIM_MM 1 -#define QSM_CRB 0xfffc00 -#endif - - -#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) - /* QSM Configuration Register */ -#define STOP 0x8000 /* Stop Enable */ -#define FRZ 0x6000 /* Freeze Control */ -#define SUPV 0x0080 /* Supervisor/Unrestricted */ -#define IARB 0x000f /* Inerrupt Arbitration */ - - -#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) - /* QSM Test Register */ -/* Used only for factor testing */ - - -#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB) - /* QSM Interrupt Level Register */ -#define ILQSPI 0x38 /* Interrupt Level for QSPI */ -#define ILSCI 0x07 /* Interrupt Level for SCI */ - - -#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) - /* QSM Interrupt Vector Register */ -#define INTV 0xff /* Interrupt Vector Number */ - - -#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) - /* SCI Control Register 0 */ -#define SCBR 0x1fff /* SCI Baud Rate */ - - -#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) - /* SCI Control Register 1 */ -#define LOOPS 0x4000 /* Loop Mode */ -#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ -#define ILT 0x1000 /* Idle-Line Detect Type */ -#define PT 0x0800 /* Parity Type */ -#define PE 0x0400 /* Parity Enable */ -#define M 0x0200 /* Mode Select */ -#define WAKE 0x0100 /* Wakeup by Address Mark */ -#define TIE 0x0080 /* Transmit Complete Interrupt Enable */ -#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */ -#define RIE 0x0020 /* Receiver Interrupt Enable */ -#define ILIE 0x0010 /* Idle-Line Interrupt Enable */ -#define TE 0x0008 /* Transmitter Enable */ -#define RE 0x0004 /* Receiver Enable */ -#define RWU 0x0002 /* Receiver Wakeup */ -#define SBK 0x0001 /* Send Break */ - - -#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) - /* SCI Status Register */ -#define TDRE 0x0100 /* Transmit Data Register Empty */ -#define TC 0x0080 /* Transmit Complete */ -#define RDRF 0x0040 /* Receive Data Register Full */ -#define RAF 0x0020 /* Receiver Active */ -#define IDLE 0x0010 /* Idle-Line Detected */ -#define OR 0x0008 /* Overrun Error */ -#define NF 0x0004 /* Noise Error Flag */ -#define FE 0x0002 /* Framing Error */ -#define PF 0x0001 /* Parity Error */ - - -#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) - /* SCI Data Register */ - - -#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) - /* Port QS Data Register */ - -#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) - /* PORT QS Pin Assignment Rgister */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a QSPI - signal. */ -/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which - case it becomes the SPI serial clock SCK. */ -/* note: PQS7 is a digital I/O pin unless the SCI transmitter is - enabled in which case it becomes the SCI serial output TxD. */ -#define QSMFun 0x0 -#define QSMDis 0x1 -/* - * PQSPAR Field | QSM Function | Discrete I/O pin - *------------------+--------------+------------------ */ -#define PQSPA0 0 /* MISO | PQS0 */ -#define PQSPA1 1 /* MOSI | PQS1 */ -#define PQSPA2 2 /* SCK | PQS2 (see note)*/ -#define PQSPA3 3 /* PCSO/!SS | PQS3 */ -#define PQSPA4 4 /* PCS1 | PQS4 */ -#define PQSPA5 5 /* PCS2 | PQS5 */ -#define PQSPA6 6 /* PCS3 | PQS6 */ -#define PQSPA7 7 /* TxD | PQS7 (see note)*/ - - -#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) - /* PORT QS Data Direction Register */ -/* Clearing a bit makes the corresponding pin an input; setting a bit - makes the pin an output. */ - - -#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) - /* QSPI Control Register 0 */ -#define MSTR 0x8000 /* Master/Slave Mode Select */ -#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ -#define BITS 0x3c00 /* Bits Per Transfer */ -#define CPOL 0x0200 /* Clock Polarity */ -#define CPHA 0x0100 /* Clock Phase */ -#define SPBR 0x00ff /* Serial Clock Baud Rate */ - - -#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) - /* QSPI Control Register 1 */ -#define SPE 0x8000 /* QSPI Enable */ -#define DSCKL 0x7f00 /* Delay before SCK */ -#define DTL 0x00ff /* Length of Delay after Transfer */ - - -#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) - /* QSPI Control Register 2 */ -#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ -#define WREN 0x4000 /* Wrap Enable */ -#define WRTO 0x2000 /* Wrap To */ -#define ENDQP 0x0f00 /* Ending Queue Pointer */ -#define NEWQP 0x000f /* New Queue Pointer Value */ - - -#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) - /* QSPI Control Register 3 */ -#define LOOPQ 0x0400 /* QSPI Loop Mode */ -#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ -#define HALT 0x0100 /* Halt */ - - -#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) - /* QSPI Status Register */ -#define SPIF 0x0080 /* QSPI Finished Flag */ -#define MODF 0x0040 /* Mode Fault Flag */ -#define HALTA 0x0020 /* Halt Acknowlwdge Flag */ -#define CPTQP x0000f /* Completed Queue Pointer */ - -#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) - /* QSPI Receive Data RAM */ -#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) - /* QSPI Transmit Data RAM */ -#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) - /* QSPI Command RAM */ - -#endif /* _RTEMS_M68K_QSM_H */ diff --git a/cpukit/score/cpu/m68k/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/rtems/m68k/sim.h deleted file mode 100644 index cec6b84cc1..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/sim.h +++ /dev/null @@ -1,333 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K System Integration Module - * - * The system integration module (SIM) is used on many Motorola 16- - * and 32-bit MCUs for the following functions: - * - * () System configuration and protection. Bus and software watchdog - * monitors are provided in addition to periodic interrupt generators. - * - * () Clock signal generation for other intermodule bus (IMB) members - * and external devices. - * - * () The generation of chip-select signals that simplify external - * circuitry interface. - * - * () Data ports that are available for general purpose input and - * output. - * - * () A system test block that is intended only for factory tests. - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family System Integration Module Reference Manual" (Motorola document - * SIMRM/AD). - */ - -/* - * This file was created by John S. Gwynne to support Motorola's 68332 MCU. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - */ - -#ifndef _RTEMS_M68K_SIM_H -#define _RTEMS_M68K_SIM_H - - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - -/* - * These macros make this file usable from assembly. - */ - -#ifdef ASM -#define SIM_VOLATILE_USHORT_POINTER -#define SIM_VOLATILE_UCHAR_POINTER -#else -#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const) -#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const) -#endif - -/* SIM_CRB (SIM Control Register Block) base address of the SIM - control registers */ -#ifndef SIM_CRB -#if SIM_MM == 0 -#define SIM_CRB 0x7ffa00 -#else /* SIM_MM */ -#undef SIM_MM -#define SIM_MM 1 -#define SIM_CRB 0xfffa00 -#endif /* SIM_MM */ -#endif /* SIM_CRB */ - - -#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB) - /* Module Configuration Register */ -#define EXOFF 0x8000 /* External Clock Off */ -#define FRZSW 0x4000 /* Freeze Software Enable */ -#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ -#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ -#define SHEN 0x0300 /* Show Cycle Enable */ -#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ -#define MM 0x0040 /* Module Mapping */ -#define IARB 0x000f /* Interrupt Arbitration Field */ - - - -#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB) - /* SIM Test Register */ -/* Used only for factor testing */ - - - -#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) - /* Clock Synthesizer Control Register */ -#define VCO 0x8000 /* Frequency Control (VCO) */ -#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ -#define COUNTER 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ - - - -#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB) - /* Reset Status Register */ -#define EXT 0x0080 /* External Reset */ -#define POW 0x0040 /* Power-On Reset */ -#define SW 0x0020 /* Software Watchdog Reset */ -#define DBF 0x0010 /* Double Bus Fault Reset */ -#define LOC 0x0004 /* Loss of Clock Reset */ -#define SYS 0x0002 /* System Reset */ -#define TST 0x0001 /* Test Submodule Reset */ - - - -#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB) - /* System Integration Test Register */ -/* Used only for factor testing */ - - - -#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB) -#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB) - /* Port E Data Register */ -#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB) - /* Port E Data Direction Register */ -#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB) - /* Port E Pin Assignment Register */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB) -#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB) - /* Port F Data Register */ -#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB) - /* Port E Data Direction Register */ -#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB) -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB) -/* !!! can write to only once after reset !!! */ - /* System Protection Control Register */ -#define SWE 0x80 /* Software Watch Enable */ -#define SWP 0x40 /* Software Watchdog Prescale */ -#define SWT 0x30 /* Software Watchdog Timing */ -#define HME 0x08 /* Halt Monitor Enable */ -#define BME 0x04 /* Bus Monitor External Enable */ -#define BMT 0x03 /* Bus Monitor Timing */ - - - -#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB) - /* Periodic Interrupt Control Reg. */ -#define PIRQL 0x0700 /* Periodic Interrupt Request Level */ -#define PIV 0x00ff /* Periodic Interrupt Level */ - - - -#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB) - /* Periodic Interrupt Timer Register */ -#define PTP 0x0100 /* Periodic Timer Prescaler Control */ -#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ - - - -#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB) - /* Software Service Register */ -/* write 0x55 then 0xaa to service the software watchdog */ - - - -#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB) - /* Test Module Shift Count */ -#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB) - /* Test Module Repetition Counter */ -#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB) - /* Test Module Control */ -#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB) - /* Test Module Distributed */ -/* Used only for factor testing */ - - - -#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB) - /* Port C Data */ - - - -#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB) - /* Chip Select Pin Assignment - Resgister 0 */ -/* CSPAR0 contains seven two-bit fields that determine the functions - of corresponding chip-select pins. CSPAR0[15:14] are not - used. These bits always read zero; write have no effect. CSPAR0 bit - 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ -#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB) - /* Chip Select Pin Assignment - Register 1 */ -/* CSPAR1 contains five two-bit fields that determine the finctions of - corresponding chip-select pins. CSPAR1[15:10] are not used. These - bits always read zero; writes have no effect. */ -/* - * - * Bit Field | Description - * ------------+--------------- - * 00 | Discrete Output - * 01 | Alternate Function - * 10 | Chip Select (8-bit port) - * 11 | Chip Select (16-bit port) - */ -#define DisOut 0x0 -#define AltFun 0x1 -#define CS8bit 0x2 -#define CS16bit 0x3 -/* - * - * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output - *-----------------+--------------------+--------------------+---------------*/ -#define CS_5 12 /* !CS5 | FC2 | PC2 */ -#define CS_4 10 /* !CS4 | FC1 | PC1 */ -#define CS_3 8 /* !CS3 | FC0 | PC0 */ -#define CS_2 6 /* !CS2 | !BGACK | */ -#define CS_1 4 /* !CS1 | !BG | */ -#define CS_0 2 /* !CS0 | !BR | */ -#define CSBOOT 0 /* !CSBOOT | | */ -/* | | | */ -#define CS_10 8 /* !CS10 | ADDR23 | ECLK */ -#define CS_9 6 /* !CS9 | ADDR22 | PC6 */ -#define CS_8 4 /* !CS8 | ADDR21 | PC5 */ -#define CS_7 2 /* !CS7 | ADDR20 | PC4 */ -#define CS_6 0 /* !CS6 | ADDR19 | PC3 */ - -#define BS_2K 0x0 -#define BS_8K 0x1 -#define BS_16K 0x2 -#define BS_64K 0x3 -#define BS_128K 0x4 -#define BS_256K 0x5 -#define BS_512K 0x6 -#define BS_1M 0x7 - -#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB) -#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB) -#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB) -#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB) -#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB) -#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB) -#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB) -#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB) -#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB) -#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB) -#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB) -#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB) - -#define MODE 0x8000 -#define Disable 0 -#define LowerByte 0x2000 -#define UpperByte 0x4000 -#define BothBytes 0x6000 -#define ReadOnly 0x0800 -#define WriteOnly 0x1000 -#define ReadWrite 0x1800 -#define SyncAS 0x0 -#define SyncDS 0x0400 - -#define WaitStates_0 (0x0 << 6) -#define WaitStates_1 (0x1 << 6) -#define WaitStates_2 (0x2 << 6) -#define WaitStates_3 (0x3 << 6) -#define WaitStates_4 (0x4 << 6) -#define WaitStates_5 (0x5 << 6) -#define WaitStates_6 (0x6 << 6) -#define WaitStates_7 (0x7 << 6) -#define WaitStates_8 (0x8 << 6) -#define WaitStates_9 (0x9 << 6) -#define WaitStates_10 (0xa << 6) -#define WaitStates_11 (0xb << 6) -#define WaitStates_12 (0xc << 6) -#define WaitStates_13 (0xd << 6) -#define FastTerm (0xe << 6) -#define External (0xf << 6) - -#define CPUSpace (0x0 << 4) -#define UserSpace (0x1 << 4) -#define SupSpace (0x2 << 4) -#define UserSupSpace (0x3 << 4) - -#define IPLevel_any 0x0 -#define IPLevel_1 0x2 -#define IPLevel_2 0x4 -#define IPLevel_3 0x6 -#define IPLevel_4 0x8 -#define IPLevel_5 0xa -#define IPLevel_6 0xc -#define IPLevel_7 0xe - -#define AVEC 1 - -#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB) -#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB) -#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB) -#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB) -#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB) -#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB) -#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB) -#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB) -#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB) -#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB) -#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB) -#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB) - -#endif /* _RTEMS_M68K_SIM_H */ diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h deleted file mode 100644 index 2be10c9638..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ /dev/null @@ -1,735 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Dependent Source - * - * This include file contains information pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * M68K Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Use the m68k's hardware interrupt stack support and have the - * interrupt manager allocate the memory for it. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1) -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 -#else -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 -#endif -#define CPU_ALLOCATE_INTERRUPT_STACK 1 - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Some family members have no FP, some have an FPU such as the - * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). - * - * NOTE: If on a CPU without hardware FP, then one can use software - * emulation. The gcc software FP emulation code has data which - * must be contexted switched on a per task basis. - */ - -#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) - #define CPU_HARDWARE_FP TRUE - #define CPU_SOFTWARE_FP FALSE -#else - #define CPU_HARDWARE_FP FALSE - #if defined( __GNUC__ ) - #define CPU_SOFTWARE_FP TRUE - #else - #define CPU_SOFTWARE_FP FALSE - #endif -#endif - -/* - * All tasks are not by default floating point tasks on this CPU. - * The IDLE task does not have a floating point context on this CPU. - * It is safe to use the deferred floating point context switch - * algorithm on this CPU. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 16 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -#define CPU_MAXIMUM_PROCESSORS 32 - -#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) - #if defined( __mc68060__ ) - #define M68K_FP_STATE_SIZE 16 - #else - #define M68K_FP_STATE_SIZE 216 - #endif -#endif - -#ifndef ASM - -/* structures */ - -/* - * Basic integer context for the m68k family. - */ - -typedef struct { - uint32_t sr; /* (sr) status register */ - uint32_t d2; /* (d2) data register 2 */ - uint32_t d3; /* (d3) data register 3 */ - uint32_t d4; /* (d4) data register 4 */ - uint32_t d5; /* (d5) data register 5 */ - uint32_t d6; /* (d6) data register 6 */ - uint32_t d7; /* (d7) data register 7 */ - void *a2; /* (a2) address register 2 */ - void *a3; /* (a3) address register 3 */ - void *a4; /* (a4) address register 4 */ - void *a5; /* (a5) address register 5 */ - void *a6; /* (a6) address register 6 */ - void *a7_msp; /* (a7) master stack pointer */ - #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) - uint8_t fpu_dis; - #endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->a7_msp - -/* - * Floating point context areas and support routines - */ - -#if ( CPU_SOFTWARE_FP == TRUE ) - /* - * This is the same as gcc's view of the software FP condition code - * register _fpCCR. The implementation of the emulation code is - * in the gcc-VERSION/config/m68k directory. This structure is - * correct as of gcc 2.7.2.2. - */ - typedef struct { - uint16_t _exception_bits; - uint16_t _trap_enable_bits; - uint16_t _sticky_bits; - uint16_t _rounding_mode; - uint16_t _format; - uint16_t _last_operation; - union { - float sf; - double df; - } _operand1; - union { - float sf; - double df; - } _operand2; - } Context_Control_fp; - - #define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - Context_Control_fp *_fp; \ - _fp = *(Context_Control_fp **)_fp_area; \ - _fp->_exception_bits = 0; \ - _fp->_trap_enable_bits = 0; \ - _fp->_sticky_bits = 0; \ - _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ - _fp->_format = 0; /* NIL */ \ - _fp->_last_operation = 0; /* NOOP */ \ - _fp->_operand1.df = 0; \ - _fp->_operand2.df = 0; \ - } -#endif - -#if ( CPU_HARDWARE_FP == TRUE ) - #if defined( __mcoldfire__ ) - /* We need memset() to initialize the FP context */ - #include - - #if ( M68K_HAS_FPU == 1 ) - /* - * The Cache Control Register (CACR) has write-only access. It is also - * used to enable and disable the FPU. We need to maintain a copy of - * this register to allow per thread values. - */ - extern uint32_t _CPU_cacr_shadow; - #endif - - /* We assume that each ColdFire core with a FPU has also an EMAC unit */ - typedef struct { - uint32_t emac_macsr; - uint32_t emac_acc0; - uint32_t emac_acc1; - uint32_t emac_acc2; - uint32_t emac_acc3; - uint32_t emac_accext01; - uint32_t emac_accext23; - uint32_t emac_mask; - #if ( M68K_HAS_FPU == 1 ) - uint16_t fp_state_format; - uint16_t fp_state_fpcr; - double fp_state_op; - uint32_t fp_state_fpsr; - - /* - * We need to save the FP Instruction Address Register (FPIAR), because - * a context switch can occur within a FP exception before the handler - * was able to save this register. - */ - uint32_t fp_fpiar; - - double fp_data [8]; - #endif - } Context_Control_fp; - - /* - * The reset value for all context relevant registers except the FP data - * registers is zero. The reset value of the FP data register is NAN. The - * restore of the reset FP state will reset the FP data registers, so the - * initial value of them can be arbitrary here. - */ - #define _CPU_Context_Initialize_fp( _fp_area ) \ - memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) - #else - /* - * FP context save area for the M68881/M68882 and 68060 numeric - * coprocessors. - */ - typedef struct { - /* - * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE - * 96 bytes for FMOVEM FP0-7 - * 12 bytes for FMOVEM CREGS - * 4 bytes for non-null flag - */ - uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112]; - } Context_Control_fp; - - /* - * The floating-point context is saved/restored via FSAVE/FRESTORE which - * use a growing down stack. Initialize the stack and adjust the FP area - * pointer accordingly. - */ - #define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - uint32_t *_fp_context = _Addresses_Add_offset( \ - *(_fp_area), CPU_CONTEXT_FP_SIZE - 4); \ - *(--(_fp_context)) = 0; \ - *(_fp_area) = (void *)(_fp_context); \ - } - #endif -#endif - -/* - * The following structures define the set of information saved - * on the current stack by RTEMS upon receipt of each exc/interrupt. - * These are not used by m68k handlers. - * The exception frame is for rdbg. - */ - -typedef struct { - uint32_t vecnum; /* vector number */ -} CPU_Interrupt_frame; - -typedef struct { - uint32_t vecnum; /* vector number */ - uint32_t sr; /* status register */ - uint32_t pc; /* program counter */ - uint32_t d0, d1, d2, d3, d4, d5, d6, d7; - uint32_t a0, a1, a2, a3, a4, a5, a6, a7; -} CPU_Exception_frame; - -/* variables */ - -extern void* _VBR; - -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ - -/* - * context size area for floating point - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * m68k family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE - -/* - * Maximum priority of a thread. Note based from 0 which is the idle task. - */ -#define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM - -#define CPU_SIZEOF_POINTER 4 - -/* - * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On m68k thread stacks require no further alignment after allocation - * from the Workspace. - */ - -#define CPU_STACK_ALIGNMENT 0 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() - -#define _CPU_ISR_Disable( _level ) \ - m68k_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) \ - m68k_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) \ - m68k_flash_interrupts( _level ) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & 0x0700 ) == 0; -} - -#define _CPU_ISR_Set_level( _newlevel ) \ - m68k_set_interrupt_level( _newlevel ) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* end of Context handler macros */ - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#if ( defined(__mcoldfire__) ) -#define _CPU_Fatal_halt( _source, _error ) \ - { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ - "or.l %2,%%d0\n\t" \ - "move.w %%d0,%%sr\n\t" \ - "move.l %1,%%d0\n\t" \ - "move.l #0xDEADBEEF,%%d1\n\t" \ - "halt" \ - : "=g" (_error) \ - : "0" (_error), "d"(0x0700) \ - : "d0", "d1" ); \ - } -#else -#define _CPU_Fatal_halt( _source, _error ) \ - { __asm__ volatile( "movl %0,%%d0; " \ - "orw #0x0700,%%sr; " \ - "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ - } -#endif - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * It appears that on the M68020 bitfield are always 32 bits wide - * when in a register. This code forces the bitfield to be in - * memory (it really always is anyway). This allows us to - * have a real 16 bit wide bitfield which operates "correctly." - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE - -#if ( M68K_HAS_BFFFO != 1 ) -/* - * Lookup table for BFFFO simulation - */ -extern const unsigned char _CPU_m68k_BFFFO_table[256]; -#endif - -#if ( M68K_HAS_BFFFO == 1 ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); - -#elif ( __mcfisaaplus__ ) - /* This is simplified by the fact that RTEMS never calls it with _value=0 */ -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - __asm__ volatile ( \ - " swap %0\n" \ - " ff1.l %0\n" \ - : "=d" ((_output)) \ - : "0" ((_value)) \ - : "cc" ) ; - -#else -/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in - _CPU_Priority_bits_index is not needed), handles the 0 case, and - does not molest _value -- jsg */ -#if ( defined(__mcoldfire__) ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( \ - " clr.l %1\n" \ - " move.w %2,%1\n" \ - " lsr.l #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1),%0\n" \ - " bra.s 0f\n" \ - "1: move.w %2,%1\n" \ - " move.b (%3,%1),%0\n" \ - " addq.l #8,%0\n" \ - "0: and.l #0xff,%0\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#elif ( M68K_HAS_EXTB_L == 1 ) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " extb.l %0\n" \ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#else -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " and.l #0x000000ff,%0\n"\ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#endif - -#endif - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000 >> (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** - * This method prints the CPU exception frame. - * - * @param[in] frame points to the frame to be printed - */ -void _CPU_Exception_frame_print( - const CPU_Exception_frame *frame -); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#if (M68K_HAS_FPSP_PACKAGE == 1) -/* - * Hooks for the Floating Point Support Package (FPSP) provided by Motorola - * - * NOTES: - * - * Motorola 68k family CPU's before the 68040 used a coprocessor - * (68881 or 68882) to handle floating point. The 68040 has internal - * floating point support -- but *not* the complete support provided by - * the 68881 or 68882. The leftover functions are taken care of by the - * M68040 Floating Point Support Package. Quoting from the MC68040 - * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): - * - * "When used with the M68040FPSP, the MC68040 FPU is fully - * compliant with IEEE floating-point standards." - * - * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and - * is invoked early in the application code to ensure that proper FP - * behavior is installed. This is not left to the BSP to call, since - * this would force all applications using that BSP to use FPSP which - * is not necessarily desirable. - * - * There is a similar package for the 68060 but RTEMS does not yet - * support the 68060. - */ - -void M68KFPSPInstallExceptionHandlers (void); - -extern int (*_FPSP_install_raw_handler)( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#endif - - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/score/cpuatomic.h b/cpukit/score/cpu/m68k/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/m68k/rtems/score/cpuimpl.h b/cpukit/score/cpu/m68k/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/m68k/rtems/score/m68k.h b/cpukit/score/cpu/m68k/rtems/score/m68k.h deleted file mode 100644 index 818578c078..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/m68k.h +++ /dev/null @@ -1,502 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Dependent Source - * - * This include file contains information pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_M68K_H -#define _RTEMS_SCORE_M68K_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Motorola MC68xxx - * family. It does this by setting variables to indicate - * which implementation dependent features are present in - * a particular member of the family. - * - * Currently recognized: - * -m68000 - * -m68000 -msoft-float - * -m68020 - * -m68020 -msoft-float - * -m68030 - * -m68040 -msoft-float - * -m68040 - * -m68040 -msoft-float - * -m68060 - * -m68060 -msoft-float - * -m68302 (no FP) (deprecated, use -m68000) - * -m68332 (no FP) (deprecated, use -mcpu32) - * -mcpu32 (no FP) - * -m5200 (no FP) - * -m528x (no FP, ISA A+) - * - * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between - * the CPU32 and CPU32+. The option -mcpu32 generates code which can - * be run on either core. RTEMS distinguishes between these two cores - * because they have different alignment rules which impact performance. - * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should - * be defined in your custom file (see make/custom/gen68360.cfg for an - * example of how to do this. If gcc ever distinguishes between these - * two cores, then RTEMS__mcpu32p__ usage will be replaced with the - * appropriate compiler defined predefine. - * - * Here is some information on the 040 variants (courtesy of Doug McBride, - * mcbride@rodin.colorado.edu): - * - * "The 68040 is a superset of the 68EC040 and the 68LC040. The - * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the - * 68EC040 have renamed the DLE pin as JS0 which must be tied to - * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The - * 68EC040 has access control units instead of memory management units. - * The 68EC040 should not have the PFLUSH or PTEST instructions executed - * (cause an indeterminate result). The 68EC040 and 68LC040 do not - * implement the DLE or multiplexed bus modes. The 68EC040 does not - * implement the output buffer impedance selection mode of operation." - * - * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction - * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, - * 68010, 68302, 68306, 68307). This instruction is available on the 68020 - * up and the cpu32 based models. - * - * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned - * data access (68020, 68030, 68040, 68060, CPU32+). - * - * NOTE: - * Eventually it would be nice to evaluate doing a lot of this section - * by having each model specify which core it uses and then go from there. - */ - -/* - * Handle the Coldfire family based on the instruction set. - */ -#if defined(__mcoldfire__) - -# define CPU_NAME "Motorola ColdFire" - -# if defined(__mcfisaa__) -/* Motorola ColdFire ISA A */ -# define CPU_MODEL_NAME "mcfisaa" -# define M68K_HAS_VBR 1 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_PREINDEXING 0 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 - -# elif defined(__mcfisaaplus__) -/* Motorola ColdFire ISA A+ */ -# define CPU_MODEL_NAME "mcfisaaplus" -# define M68K_HAS_VBR 1 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_PREINDEXING 0 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 - -# elif defined(__mcfisab__) -/* Motorola ColdFire ISA B */ -# define CPU_MODEL_NAME "mcfisab" -# define M68K_HAS_VBR 1 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_PREINDEXING 0 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 - -# else -# error "Unsupported Coldfire ISA -- Please notify RTEMS" -# endif - -/* - * Assume the FPU support is independent. I think it is just the ISA B - * instruction set. - */ -# if defined (__mcffpu__) -# define M68K_HAS_FPU 1 - /* - * td: can we be sure that all CFs with FPU also have an EMAC? - */ -# define M68K_HAS_EMAC 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -/* - * Tiny RTEMS support. Small stack and limited priorities. - * - * These CPUs have very limited on-CPU memory which cannot - * be expanded. We have to be gentle with them or nothing - * will every run. - */ -# if (defined(__mcf_cpu_52221) || \ - defined(__mcf_cpu_52223) || \ - defined(__mcf_cpu_52230) || \ - defined(__mcf_cpu_52231) || \ - defined(__mcf_cpu_52232) || \ - defined(__mcf_cpu_52233) || \ - defined(__mcf_cpu_52234) || \ - defined(__mcf_cpu_52235) || \ - defined(__mcf_cpu_52225) || \ - defined(__mcf_cpu_52235)) - #define M68K_CPU_STACK_MINIMUM_SIZE 1024 - /* Define the lowest priority. Based from 0 to this is 16 levels. */ - #define M68K_CPU_PRIORITY_MAXIMUM 15 -# else - #define M68K_CPU_STACK_MINIMUM_SIZE 4096 - /* Use the default number of priorities */ - #define M68K_CPU_PRIORITY_MAXIMUM 255 -# endif - -#else - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. Notice the only exception to this is that - * gcc does not distinguish between CPU32 and CPU32+. This - * feature selection logic is setup such that if RTEMS__mcpu32p__ - * is defined, then CPU32+ rules are used. Otherwise, the safe - * but less efficient CPU32 rules are used for the CPU32+. - */ - -# define CPU_NAME "Motorola MC68xxx" - -/* - * One stack size fits all 68000 processors. - */ -# define M68K_CPU_STACK_MINIMUM_SIZE 4096 - -# if (defined(__mc68020__) && !defined(__mcpu32__)) - -# define CPU_MODEL_NAME "m68020" -# define M68K_HAS_VBR 1 -# define M68K_HAS_SEPARATE_STACKS 1 -# define M68K_HAS_BFFFO 1 -# define M68K_HAS_PREINDEXING 1 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -# elif defined(__mc68030__) - -# define CPU_MODEL_NAME "m68030" -# define M68K_HAS_VBR 1 -# define M68K_HAS_SEPARATE_STACKS 1 -# define M68K_HAS_BFFFO 1 -# define M68K_HAS_PREINDEXING 1 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -# elif defined(__mc68040__) - -# define CPU_MODEL_NAME "m68040" -# define M68K_HAS_VBR 1 -# define M68K_HAS_SEPARATE_STACKS 1 -# define M68K_HAS_BFFFO 1 -# define M68K_HAS_PREINDEXING 1 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 1 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -# elif defined(__mc68060__) - -# define CPU_MODEL_NAME "m68060" -# define M68K_HAS_VBR 1 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_BFFFO 1 -# define M68K_HAS_PREINDEXING 1 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -# elif defined(__mc68302__) - -# define CPU_MODEL_NAME "m68302" -# define M68K_HAS_VBR 0 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_PREINDEXING 0 -# define M68K_HAS_EXTB_L 0 -# define M68K_HAS_MISALIGNED 0 -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 - - /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ -# elif defined(RTEMS__mcpu32p__) - -# define CPU_MODEL_NAME "mcpu32+" -# define M68K_HAS_VBR 1 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_PREINDEXING 1 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 1 -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 - -# elif defined(__mcpu32__) - -# define CPU_MODEL_NAME "mcpu32" -# define M68K_HAS_VBR 1 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_PREINDEXING 1 -# define M68K_HAS_EXTB_L 1 -# define M68K_HAS_MISALIGNED 0 -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 - -# elif defined(__mc68000__) - -# define CPU_MODEL_NAME "m68000" -# define M68K_HAS_VBR 0 -# define M68K_HAS_SEPARATE_STACKS 0 -# define M68K_HAS_BFFFO 0 -# define M68K_HAS_PREINDEXING 0 -# define M68K_HAS_EXTB_L 0 -# define M68K_HAS_MISALIGNED 0 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -# else - -# error "Unsupported 68000 CPU model -- are you sure you're running a 68k compiler?" - -# endif - -/* - * No Tiny RTEMS support on the standard 68000 family. - */ -# define M68K_CPU_STACK_MINIMUM_SIZE 4096 -# define M68K_CPU_PRIORITY_MAXIMUM 255 - -#endif - -/* - * OBSOLETE: Backward compatibility only - Don't use. - * Use __mcoldfire__ instead. - */ -#if defined(__mcoldfire__) -#define M68K_COLDFIRE_ARCH 1 -#else -#define M68K_COLDFIRE_ARCH 0 -#endif - -#ifndef ASM - -#if ( defined(__mcoldfire__) ) -#define m68k_disable_interrupts( _level ) \ - do { register uint32_t _tmpsr = 0x0700; \ - __asm__ volatile ( "move.w %%sr,%0\n\t" \ - "or.l %0,%1\n\t" \ - "move.w %1,%%sr" \ - : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) \ - : "cc" ); \ - } while( 0 ) -#else -#define m68k_disable_interrupts( _level ) \ - __asm__ volatile ( "move.w %%sr,%0\n\t" \ - "or.w #0x0700,%%sr" \ - : "=d" (_level) \ - : : "cc" ) -#endif - -#define m68k_enable_interrupts( _level ) \ - __asm__ volatile ( "move.w %0,%%sr " : : "d" (_level) : "cc"); - -#if ( defined(__mcoldfire__) ) -#define m68k_flash_interrupts( _level ) \ - do { register uint32_t _tmpsr = 0x0700; \ - asm volatile ( "move.w %2,%%sr\n\t" \ - "or.l %2,%1\n\t" \ - "move.w %1,%%sr" \ - : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) \ - : "cc"); \ - } while( 0 ) -#else -#define m68k_flash_interrupts( _level ) \ - __asm__ volatile ( "move.w %0,%%sr\n\t" \ - "or.w #0x0700,%%sr" \ - : : "d" (_level) \ - : "cc" ) -#endif - -#define m68k_get_interrupt_level( _level ) \ - do { \ - register uint32_t _tmpsr; \ - \ - __asm__ volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ - _level = (_tmpsr & 0x0700) >> 8; \ - } while (0) - -#define m68k_set_interrupt_level( _newlevel ) \ - do { \ - register uint32_t _tmpsr; \ - \ - __asm__ volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ - _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ - __asm__ volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \ - } while (0) - -#if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) ) -#define m68k_get_vbr( vbr ) \ - __asm__ volatile ( "movec %%vbr,%0 " : "=r" (vbr)) - -#define m68k_set_vbr( vbr ) \ - __asm__ volatile ( "movec %0,%%vbr " : : "r" (vbr)) - -#elif ( defined(__mcoldfire__) ) -extern void* _VBR; -#define m68k_get_vbr( _vbr ) _vbr = &_VBR - -#define m68k_set_vbr( _vbr ) \ - do { \ - __asm__ volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \ - _VBR = (void *)_vbr; \ - } while(0) - -#else -#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR -#define m68k_set_vbr( _vbr ) -#endif - -/* - * Access Control Registers - */ -#define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) -#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) -#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - */ -#if ( defined(__mcoldfire__) ) - -/* There are no rotate commands in Coldfire architecture. We will use - * generic implementation of endian swapping for Coldfire. - */ -static inline uint32_t m68k_swap_u32( - uint32_t value - ) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -static inline uint16_t m68k_swap_u16( - uint16_t value -) -{ - return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); -} - -#else - -static inline uint32_t m68k_swap_u32( - uint32_t value -) -{ - uint32_t swapped = value; - - __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); - __asm__ volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); - __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); - - return( swapped ); -} - -static inline uint16_t m68k_swap_u16( - uint16_t value -) -{ - uint16_t swapped = value; - - __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); - - return( swapped ); -} -#endif - -#define CPU_swap_u32( value ) m68k_swap_u32( value ) -#define CPU_swap_u16( value ) m68k_swap_u16( value ) - - -/* - * _CPU_virtual_to_physical - * - * This function is used to map virtual addresses to physical - * addresses. - * - * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE - * PHYSICAL ADDRESSES - */ -static inline void * _CPU_virtual_to_physical ( - const void * d_addr ) -{ - return (void *) d_addr; -} - - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_M68K_H */ diff --git a/cpukit/score/cpu/m68k/rtems/score/types.h b/cpukit/score/cpu/m68k/rtems/score/types.h deleted file mode 100644 index 947c6ace69..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/types.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Type Definitions - * - * This include file contains type definitions pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/mips/Makefile.am b/cpukit/score/cpu/mips/Makefile.am index 123e5232b9..fe7fa5582c 100644 --- a/cpukit/score/cpu/mips/Makefile.am +++ b/cpukit/score/cpu/mips/Makefile.am @@ -1,23 +1,9 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_mipsdir = $(includedir)/rtems/mips -include_rtems_mips_HEADERS = rtems/mips/idtcpu.h -include_rtems_mips_HEADERS += rtems/mips/iregdef.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/mips.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c cpu_asm.S libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/mips/headers.am b/cpukit/score/cpu/mips/headers.am new file mode 100644 index 0000000000..cbcf1dd91f --- /dev/null +++ b/cpukit/score/cpu/mips/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_mipsdir = $(includedir)/rtems/mips +include_rtems_mips_HEADERS = +include_rtems_mips_HEADERS += include/rtems/mips/idtcpu.h +include_rtems_mips_HEADERS += include/rtems/mips/iregdef.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/mips.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/mips/include/machine/elf_machdep.h b/cpukit/score/cpu/mips/include/machine/elf_machdep.h new file mode 100644 index 0000000000..26700ce4ce --- /dev/null +++ b/cpukit/score/cpu/mips/include/machine/elf_machdep.h @@ -0,0 +1,199 @@ +/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */ + +#ifndef _MIPS_ELF_MACHDEP_H_ +#define _MIPS_ELF_MACHDEP_H_ + +#ifdef _LP64 +#define ARCH_ELFSIZE 64 /* MD native binary size */ +#else +#define ARCH_ELFSIZE 32 /* MD native binary size */ +#endif + +#if ARCH_ELFSIZE == 32 +#define ELF32_MACHDEP_ID_CASES \ + case EM_MIPS: \ + break; + +#define ELF32_MACHDEP_ID EM_MIPS + +#elif ARCH_ELFSIZE == 64 +#define ELF64_MACHDEP_ID_CASES \ + case EM_MIPS: \ + break; + +#define ELF64_MACHDEP_ID EM_MIPS + +#endif + + +/* mips relocs. */ + +#define R_MIPS_NONE 0 +#define R_MIPS_16 1 +#define R_MIPS_32 2 +#define R_MIPS_REL32 3 +#define R_MIPS_REL R_MIPS_REL32 +#define R_MIPS_26 4 +#define R_MIPS_HI16 5 /* high 16 bits of symbol value */ +#define R_MIPS_LO16 6 /* low 16 bits of symbol value */ +#define R_MIPS_GPREL16 7 /* GP-relative reference */ +#define R_MIPS_LITERAL 8 /* Reference to literal section */ +#define R_MIPS_GOT16 9 /* Reference to global offset table */ +#define R_MIPS_GOT R_MIPS_GOT16 +#define R_MIPS_PC16 10 /* 16 bit PC relative reference */ +#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */ +#define R_MIPS_CALL R_MIPS_CALL16 +#define R_MIPS_GPREL32 12 + +/* 13, 14, 15 are not defined at this point. */ +#define R_MIPS_UNUSED1 13 +#define R_MIPS_UNUSED2 14 +#define R_MIPS_UNUSED3 15 + +/* + * The remaining relocs are apparently part of the 64-bit Irix ELF ABI. + */ +#define R_MIPS_SHIFT5 16 +#define R_MIPS_SHIFT6 17 + +#define R_MIPS_64 18 +#define R_MIPS_GOT_DISP 19 +#define R_MIPS_GOT_PAGE 20 +#define R_MIPS_GOT_OFST 21 +#define R_MIPS_GOT_HI16 22 +#define R_MIPS_GOT_LO16 23 +#define R_MIPS_SUB 24 +#define R_MIPS_INSERT_A 25 +#define R_MIPS_INSERT_B 26 +#define R_MIPS_DELETE 27 +#define R_MIPS_HIGHER 28 +#define R_MIPS_HIGHEST 29 +#define R_MIPS_CALL_HI16 30 +#define R_MIPS_CALL_LO16 31 +#define R_MIPS_SCN_DISP 32 +#define R_MIPS_REL16 33 +#define R_MIPS_ADD_IMMEDIATE 34 +#define R_MIPS_PJUMP 35 +#define R_MIPS_RELGOT 36 +#define R_MIPS_JALR 37 +/* TLS relocations */ + +#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ +#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ +#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ +#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ +#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ +#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ +#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ +#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ +#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ +#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ +#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ +#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ +#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ + +#define R_MIPS_max 51 + +#define R_TYPE(name) __CONCAT(R_MIPS_,name) + +#define R_MIPS16_min 100 +#define R_MIPS16_26 100 +#define R_MIPS16_GPREL 101 +#define R_MIPS16_GOT16 102 +#define R_MIPS16_CALL16 103 +#define R_MIPS16_HI16 104 +#define R_MIPS16_LO16 105 +#define R_MIPS16_max 106 + + +/* mips dynamic tags */ + +#define DT_MIPS_RLD_VERSION 0x70000001 +#define DT_MIPS_TIME_STAMP 0x70000002 +#define DT_MIPS_ICHECKSUM 0x70000003 +#define DT_MIPS_IVERSION 0x70000004 +#define DT_MIPS_FLAGS 0x70000005 +#define DT_MIPS_BASE_ADDRESS 0x70000006 +#define DT_MIPS_CONFLICT 0x70000008 +#define DT_MIPS_LIBLIST 0x70000009 +#define DT_MIPS_CONFLICTNO 0x7000000b +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */ +#define DT_MIPS_LIBLISTNO 0x70000010 +#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 +#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */ +#define DT_MIPS_HIPAGENO 0x70000014 +#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */ + +/* + * ELF Flags + */ +#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */ +#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */ +#define EF_MIPS_ABI2 0x00000020 /* N32 */ + +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */ +#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */ +#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */ + +#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */ +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */ +#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */ +#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */ +#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */ +#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */ + +#define EF_MIPS_ABI 0x0000f000 +#define EF_MIPS_ABI_O32 0x00001000 +#define EF_MIPS_ABI_O64 0x00002000 +#define EF_MIPS_ABI_EABI32 0x00003000 +#define EF_MIPS_ABI_EABI64 0x00004000 + +#if defined(__MIPSEB__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB +#elif defined(__MIPSEL__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB +#elif !defined(HAVE_NBTOOL_CONFIG_H) +#error neither __MIPSEL__ nor __MIPSEB__ are defined. +#endif + +#ifdef _KERNEL +#ifdef _KERNEL_OPT +#include "opt_compat_netbsd.h" +#endif +#ifdef COMPAT_16 +/* + * Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable. + * Tell the kernel ELF exec code not to try relocating the interpreter + * for dynamically-linked ELF binaries. + */ +#define ELF_INTERP_NON_RELOCATABLE +#endif /* COMPAT_16 */ + +/* + * We need to be able to include the ELF header so we can pick out the + * ABI being used. + */ +#ifdef ELFSIZE +#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe) +#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup) +#endif + +struct exec_package; + +int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +void coredump_elf32_setup(struct lwp *, void *); + +int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +void coredump_elf64_setup(struct lwp *, void *); +#endif /* _KERNEL */ + +#endif /* _MIPS_ELF_MACHDEP_H_ */ diff --git a/cpukit/score/cpu/mips/include/rtems/asm.h b/cpukit/score/cpu/mips/include/rtems/asm.h new file mode 100644 index 0000000000..9c84f61990 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/asm.h @@ -0,0 +1,160 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + */ +/* @(#)asm.h 03/15/96 1.1 */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +/* + * Debugger macros for assembly language routines. Allows the + * programmer to set up the necessary stack frame info + * required by debuggers to do stack traces. + */ + +#ifndef XDS +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg +#define ENDFRAME(name) \ + .end name +#else +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl _##name;\ +_##name: +#define ENDFRAME(name) +#endif /* XDS */ + +/* + * Hardware Floating Point Registers + */ + +#define R_FP0 0 +#define R_FP1 1 +#define R_FP2 2 +#define R_FP3 3 +#define R_FP4 4 +#define R_FP5 5 +#define R_FP6 6 +#define R_FP7 7 +#define R_FP8 8 +#define R_FP9 9 +#define R_FP10 10 +#define R_FP11 11 +#define R_FP12 12 +#define R_FP13 13 +#define R_FP14 14 +#define R_FP15 15 +#define R_FP16 16 +#define R_FP17 17 +#define R_FP18 18 +#define R_FP19 19 +#define R_FP20 20 +#define R_FP21 21 +#define R_FP22 22 +#define R_FP23 23 +#define R_FP24 24 +#define R_FP25 25 +#define R_FP26 26 +#define R_FP27 27 +#define R_FP28 28 +#define R_FP29 29 +#define R_FP30 30 +#define R_FP31 31 + +#endif +/* end of include file */ + diff --git a/cpukit/score/cpu/mips/include/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/include/rtems/mips/idtcpu.h new file mode 100644 index 0000000000..927bbec133 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/mips/idtcpu.h @@ -0,0 +1,708 @@ +/** + * @file idtcpu.h + * + * @brief CPU Related Definitions + * + * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves + * added Register definition for XContext reg. + * Look towards end of this file. + */ + +/* + * Based upon IDT provided code with the following release: + * + * This source code has been made available to you by IDT on an AS-IS + * basis. Anyone receiving this source is licensed under IDT copyrights + * to use it in any way he or she deems fit, including copying it, + * modifying it, compiling it, and redistributing it either with or + * without modifications. No license under IDT patents or patent + * applications is to be implied by the copyright license. + * + * Any user of this software should understand that IDT cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work must + * include the IDT copyright notice, this paragraph, and the preceeding + * two paragraphs in the transferred software. + * + * COPYRIGHT IDT CORPORATION 1996 + * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + */ + +#ifndef _RTEMS_MIPS_IDTCPU_H +#define _RTEMS_MIPS_IDTCPU_H + +/** + * @defgroup MipsSet_idtcpu CPU Related Definitions + * + * @ingroup MIPS + * + */ +/**@{*/ + +/* + * 950313: Ketan added Register definition for XContext reg. + * added define for WAIT instruction. + * 950421: Ketan added Register definition for Config reg (R3081) + */ + +/* +** memory configuration and mapping +*/ +#define K0BASE 0x80000000 +#define K0SIZE 0x20000000 +#define K1BASE 0xa0000000 +#define K1SIZE 0x20000000 +#define K2BASE 0xc0000000 +#define K2SIZE 0x20000000 +#if __mips == 3 +#define KSBASE 0xe0000000 +#define KSSIZE 0x20000000 +#endif + +#define KUBASE 0 +#define KUSIZE 0x80000000 + +/* +** Exception Vectors +*/ +#if __mips == 1 +#define UT_VEC K0BASE /* utlbmiss vector */ +#define DB_VEC (K0BASE+0x40) /* debug vector */ +#define E_VEC (K0BASE+0x80) /* exception vector */ +#elif __mips == 32 +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ +#define C_VEC (K0BASE+0x100) /* cache error vector */ +#define E_VEC (K0BASE+0x180) /* exception vector */ +#elif __mips == 3 +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ +#define C_VEC (K0BASE+0x100) /* cache error vector */ +#define E_VEC (K0BASE+0x180) /* exception vector */ +#else +#error "EXCEPTION VECTORS: unknown ISA level" +#endif +#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ + +/* +** Address conversion macros +*/ +#ifdef CLANGUAGE +#define CAST(as) (as) +#else +#define CAST(as) +#endif +#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ +#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ +#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ +#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ +#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ +#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ + +/* +** Cache size constants +*/ +#define MINCACHE 0x200 /* 512 For 3041. */ +#define MAXCACHE 0x40000 /* 256*1024 256k */ + +#if __mips == 32 +/* R4000 configuration register definitions */ +#define CFG_CM 0x80000000 /* Master-Checker mode */ +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ +#define CFG_ECBY2 0x00000000 /* divide by 2 */ +#define CFG_ECBY3 0x10000000 /* divide by 3 */ +#define CFG_ECBY4 0x20000000 /* divide by 4 */ +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ +#define CFG_EPD 0x00000000 /* D */ +#define CFG_EPDDX 0x01000000 /* DDX */ +#define CFG_EPDDXX 0x02000000 /* DDXX */ +#define CFG_EPDXDX 0x03000000 /* DXDX */ +#define CFG_EPDDXXX 0x04000000 /* DDXXX */ +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ +#define CFG_SBSHIFT 22 +#define CFG_SB4 0x00000000 /* 4 words */ +#define CFG_SB8 0x00400000 /* 8 words */ +#define CFG_SB16 0x00800000 /* 16 words */ +#define CFG_SB32 0x00c00000 /* 32 words */ +#define CFG_SS 0x00200000 /* Split secondary cache */ +#define CFG_SW 0x00100000 /* Secondary cache port width */ +#define CFG_EWMASK 0x000c0000 /* System port width */ +#define CFG_EWSHIFT 18 +#define CFG_EW64 0x00000000 /* 64 bit */ +#define CFG_EW32 0x00010000 /* 32 bit */ +#define CFG_SC 0x00020000 /* Secondary cache absent */ +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ +#define CFG_BE 0x00008000 /* Big Endian */ +#define CFG_EM 0x00004000 /* ECC mode enable */ +#define CFG_EB 0x00002000 /* Block ordering */ +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ +#define CFG_ICSHIFT 9 +#define CFG_DCMASK 0x000001c0 /* Data cache size */ +#define CFG_DCSHIFT 6 +#define CFG_IB 0x00000020 /* Instruction cache block size */ +#define CFG_DB 0x00000010 /* Data cache block size */ +#define CFG_CU 0x00000008 /* Update on Store Conditional */ +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ + +/* + * R4000 primary cache mode + */ +#define CFG_C_UNCACHED 2 +#define CFG_C_NONCOHERENT 3 +#define CFG_C_COHERENTXCL 4 +#define CFG_C_COHERENTXCLW 5 +#define CFG_C_COHERENTUPD 6 + +/* + * R4000 cache operations (should be in assembler...?) + */ +#define Index_Invalidate_I 0x0 /* 0 0 */ +#define Index_Writeback_Inv_D 0x1 /* 0 1 */ +#define Index_Invalidate_SI 0x2 /* 0 2 */ +#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ +#define Index_Load_Tag_I 0x4 /* 1 0 */ +#define Index_Load_Tag_D 0x5 /* 1 1 */ +#define Index_Load_Tag_SI 0x6 /* 1 2 */ +#define Index_Load_Tag_SD 0x7 /* 1 3 */ +#define Index_Store_Tag_I 0x8 /* 2 0 */ +#define Index_Store_Tag_D 0x9 /* 2 1 */ +#define Index_Store_Tag_SI 0xA /* 2 2 */ +#define Index_Store_Tag_SD 0xB /* 2 3 */ +#define Create_Dirty_Exc_D 0xD /* 3 1 */ +#define Create_Dirty_Exc_SD 0xF /* 3 3 */ +#define Hit_Invalidate_I 0x10 /* 4 0 */ +#define Hit_Invalidate_D 0x11 /* 4 1 */ +#define Hit_Invalidate_SI 0x12 /* 4 2 */ +#define Hit_Invalidate_SD 0x13 /* 4 3 */ +#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ +#define Fill_I 0x14 /* 5 0 */ +#define Hit_Writeback_D 0x19 /* 6 1 */ +#define Hit_Writeback_SD 0x1B /* 6 3 */ +#define Hit_Writeback_I 0x18 /* 6 0 */ +#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ +#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ + +/* Disabled by chris -- horrible overload of common word. +#ifndef WAIT +#define WAIT .word 0x42000020 +#endif +*/ +/* Disabled by joel -- horrible overload of common word. +#ifndef wait +#define wait .word 0x42000020 +#endif wait +*/ + +#endif + +#if __mips == 3 +/* R4000 configuration register definitions */ +#define CFG_CM 0x80000000 /* Master-Checker mode */ +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ +#define CFG_ECBY2 0x00000000 /* divide by 2 */ +#define CFG_ECBY3 0x10000000 /* divide by 3 */ +#define CFG_ECBY4 0x20000000 /* divide by 4 */ +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ +#define CFG_EPD 0x00000000 /* D */ +#define CFG_EPDDX 0x01000000 /* DDX */ +#define CFG_EPDDXX 0x02000000 /* DDXX */ +#define CFG_EPDXDX 0x03000000 /* DXDX */ +#define CFG_EPDDXXX 0x04000000 /* DDXXX */ +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ +#define CFG_SBSHIFT 22 +#define CFG_SB4 0x00000000 /* 4 words */ +#define CFG_SB8 0x00400000 /* 8 words */ +#define CFG_SB16 0x00800000 /* 16 words */ +#define CFG_SB32 0x00c00000 /* 32 words */ +#define CFG_SS 0x00200000 /* Split secondary cache */ +#define CFG_SW 0x00100000 /* Secondary cache port width */ +#define CFG_EWMASK 0x000c0000 /* System port width */ +#define CFG_EWSHIFT 18 +#define CFG_EW64 0x00000000 /* 64 bit */ +#define CFG_EW32 0x00010000 /* 32 bit */ +#define CFG_SC 0x00020000 /* Secondary cache absent */ +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ +#define CFG_BE 0x00008000 /* Big Endian */ +#define CFG_EM 0x00004000 /* ECC mode enable */ +#define CFG_EB 0x00002000 /* Block ordering */ +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ +#define CFG_ICSHIFT 9 +#define CFG_DCMASK 0x000001c0 /* Data cache size */ +#define CFG_DCSHIFT 6 +#define CFG_IB 0x00000020 /* Instruction cache block size */ +#define CFG_DB 0x00000010 /* Data cache block size */ +#define CFG_CU 0x00000008 /* Update on Store Conditional */ +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ + +/* + * R4000 primary cache mode + */ +#define CFG_C_UNCACHED 2 +#define CFG_C_NONCOHERENT 3 +#define CFG_C_COHERENTXCL 4 +#define CFG_C_COHERENTXCLW 5 +#define CFG_C_COHERENTUPD 6 + +/* + * R4000 cache operations (should be in assembler...?) + */ +#define Index_Invalidate_I 0x0 /* 0 0 */ +#define Index_Writeback_Inv_D 0x1 /* 0 1 */ +#define Index_Invalidate_SI 0x2 /* 0 2 */ +#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ +#define Index_Load_Tag_I 0x4 /* 1 0 */ +#define Index_Load_Tag_D 0x5 /* 1 1 */ +#define Index_Load_Tag_SI 0x6 /* 1 2 */ +#define Index_Load_Tag_SD 0x7 /* 1 3 */ +#define Index_Store_Tag_I 0x8 /* 2 0 */ +#define Index_Store_Tag_D 0x9 /* 2 1 */ +#define Index_Store_Tag_SI 0xA /* 2 2 */ +#define Index_Store_Tag_SD 0xB /* 2 3 */ +#define Create_Dirty_Exc_D 0xD /* 3 1 */ +#define Create_Dirty_Exc_SD 0xF /* 3 3 */ +#define Hit_Invalidate_I 0x10 /* 4 0 */ +#define Hit_Invalidate_D 0x11 /* 4 1 */ +#define Hit_Invalidate_SI 0x12 /* 4 2 */ +#define Hit_Invalidate_SD 0x13 /* 4 3 */ +#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ +#define Fill_I 0x14 /* 5 0 */ +#define Hit_Writeback_D 0x19 /* 6 1 */ +#define Hit_Writeback_SD 0x1B /* 6 3 */ +#define Hit_Writeback_I 0x18 /* 6 0 */ +#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ +#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ + +/* Disabled by chris -- horrible overload of common word. +#ifndef WAIT +#define WAIT .word 0x42000020 +#endif +*/ +/* Disabled by joel -- horrible overload of common word. +#ifndef wait +#define wait .word 0x42000020 +#endif wait +*/ + +#endif + +/* +** TLB resource defines +*/ +#if __mips == 1 +#define N_TLB_ENTRIES 64 +#define TLB_PGSIZE 0x1000 +#define RANDBASE 8 +#define TLBLO_PFNMASK 0xfffff000 +#define TLBLO_PFNSHIFT 12 +#define TLBLO_N 0x800 /* non-cacheable */ +#define TLBLO_D 0x400 /* writeable */ +#define TLBLO_V 0x200 /* valid bit */ +#define TLBLO_G 0x100 /* global access bit */ + +#define TLBHI_VPNMASK 0xfffff000 +#define TLBHI_VPNSHIFT 12 +#define TLBHI_PIDMASK 0xfc0 +#define TLBHI_PIDSHIFT 6 +#define TLBHI_NPID 64 + +#define TLBINX_PROBE 0x80000000 +#define TLBINX_INXMASK 0x00003f00 +#define TLBINX_INXSHIFT 8 + +#define TLBRAND_RANDMASK 0x00003f00 +#define TLBRAND_RANDSHIFT 8 + +#define TLBCTXT_BASEMASK 0xffe00000 +#define TLBCTXT_BASESHIFT 21 + +#define TLBCTXT_VPNMASK 0x001ffffc +#define TLBCTXT_VPNSHIFT 2 +#endif +#if __mips == 3 +#define N_TLB_ENTRIES 48 + +#define TLBHI_VPN2MASK 0xffffe000 +#define TLBHI_PIDMASK 0x000000ff +#define TLBHI_NPID 256 + +#define TLBLO_PFNMASK 0x3fffffc0 +#define TLBLO_PFNSHIFT 6 +#define TLBLO_D 0x00000004 /* writeable */ +#define TLBLO_V 0x00000002 /* valid bit */ +#define TLBLO_G 0x00000001 /* global access bit */ +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ +#define TLBLO_CSHIFT 3 + +#define TLBLO_UNCACHED (CFG_C_UNCACHED< k, 1 => u */ +#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ +#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ +#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ +#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ +#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ +#endif + +#if __mips == 3 +#define SR_CUMASK 0xf0000000 /* coproc usable bits */ +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ + +#define SR_RP 0x08000000 /* Reduced power operation */ +#define SR_FR 0x04000000 /* Additional floating point registers */ +#define SR_RE 0x02000000 /* Reverse endian in user mode */ + +#define SR_BEV 0x00400000 /* Use boot exception vectors */ +#define SR_TS 0x00200000 /* TLB shutdown */ +#define SR_SR 0x00100000 /* Soft reset */ +#define SR_CH 0x00040000 /* Cache hit */ +#define SR_CE 0x00020000 /* Use cache ECC */ +#define SR_DE 0x00010000 /* Disable cache exceptions */ + +/* +** status register interrupt masks and bits +*/ + +#define SR_IMASK 0x0000ff00 /* Interrupt mask */ +#define SR_IMASK8 0x00000000 /* mask level 8 */ +#define SR_IMASK7 0x00008000 /* mask level 7 */ +#define SR_IMASK6 0x0000c000 /* mask level 6 */ +#define SR_IMASK5 0x0000e000 /* mask level 5 */ +#define SR_IMASK4 0x0000f000 /* mask level 4 */ +#define SR_IMASK3 0x0000f800 /* mask level 3 */ +#define SR_IMASK2 0x0000fc00 /* mask level 2 */ +#define SR_IMASK1 0x0000fe00 /* mask level 1 */ +#define SR_IMASK0 0x0000ff00 /* mask level 0 */ + +#define SR_IMASKSHIFT 8 + +#define SR_IBIT8 0x00008000 /* bit level 8 */ +#define SR_IBIT7 0x00004000 /* bit level 7 */ +#define SR_IBIT6 0x00002000 /* bit level 6 */ +#define SR_IBIT5 0x00001000 /* bit level 5 */ +#define SR_IBIT4 0x00000800 /* bit level 4 */ +#define SR_IBIT3 0x00000400 /* bit level 3 */ +#define SR_IBIT2 0x00000200 /* bit level 2 */ +#define SR_IBIT1 0x00000100 /* bit level 1 */ + +#define SR_KSMASK 0x00000018 /* Kernel mode mask */ +#define SR_KSUSER 0x00000010 /* User mode */ +#define SR_KSSUPER 0x00000008 /* Supervisor mode */ +#define SR_KSKERNEL 0x00000000 /* Kernel mode */ +#define SR_ERL 0x00000004 /* Error level */ +#define SR_EXL 0x00000002 /* Exception level */ +#define SR_IE 0x00000001 /* Interrupts enabled */ +#endif + +#if __mips == 32 +#define SR_CUMASK 0xf0000000 /* coproc usable bits */ +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ + +#define SR_RP 0x08000000 /* Reduced power operation */ +#define SR_FR 0x04000000 /* Additional floating point registers */ +#define SR_RE 0x02000000 /* Reverse endian in user mode */ + +#define SR_BEV 0x00400000 /* Use boot exception vectors */ +#define SR_TS 0x00200000 /* TLB shutdown */ +#define SR_SR 0x00100000 /* Soft reset */ +#define SR_CH 0x00040000 /* Cache hit */ +#define SR_CE 0x00020000 /* Use cache ECC */ +#define SR_DE 0x00010000 /* Disable cache exceptions */ + +/* +** status register interrupt masks and bits +*/ + +#define SR_IMASK 0x0000ff00 /* Interrupt mask */ +#define SR_IMASK8 0x00000000 /* mask level 8 */ +#define SR_IMASK7 0x00008000 /* mask level 7 */ +#define SR_IMASK6 0x0000c000 /* mask level 6 */ +#define SR_IMASK5 0x0000e000 /* mask level 5 */ +#define SR_IMASK4 0x0000f000 /* mask level 4 */ +#define SR_IMASK3 0x0000f800 /* mask level 3 */ +#define SR_IMASK2 0x0000fc00 /* mask level 2 */ +#define SR_IMASK1 0x0000fe00 /* mask level 1 */ +#define SR_IMASK0 0x0000ff00 /* mask level 0 */ + +#define SR_IMASKSHIFT 8 + +#define SR_IBIT8 0x00008000 /* bit level 8 */ +#define SR_IBIT7 0x00004000 /* bit level 7 */ +#define SR_IBIT6 0x00002000 /* bit level 6 */ +#define SR_IBIT5 0x00001000 /* bit level 5 */ +#define SR_IBIT4 0x00000800 /* bit level 4 */ +#define SR_IBIT3 0x00000400 /* bit level 3 */ +#define SR_IBIT2 0x00000200 /* bit level 2 */ +#define SR_IBIT1 0x00000100 /* bit level 1 */ + +#define SR_KSMASK 0x00000018 /* Kernel mode mask */ +#define SR_KSUSER 0x00000010 /* User mode */ +#define SR_KSSUPER 0x00000008 /* Supervisor mode */ +#define SR_KSKERNEL 0x00000000 /* Kernel mode */ +#define SR_ERL 0x00000004 /* Error level */ +#define SR_EXL 0x00000002 /* Exception level */ +#define SR_IE 0x00000001 /* Interrupts enabled */ +#endif + +/* + * Cause Register + */ +#define CAUSE_BD 0x80000000 /* Branch delay slot */ +#define CAUSE_BT 0x40000000 /* Branch Taken */ +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ +#define CAUSE_CESHIFT 28 + + +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ +#define CAUSE_IPSHIFT 8 + +#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ +#define CAUSE_EXCSHIFT 2 + +#ifndef XDS +/* +** Coprocessor 0 registers +*/ +#define C0_INX $0 /* tlb index */ +#define C0_RAND $1 /* tlb random */ +#if __mips == 1 +#define C0_TLBLO $2 /* tlb entry low */ +#endif +#if __mips == 3 +#define C0_TLBLO0 $2 /* tlb entry low 0 */ +#define C0_TLBLO1 $3 /* tlb entry low 1 */ +#endif + +#if __mips == 32 +#define C0_TLBLO0 $2 /* tlb entry low 0 */ +#define C0_TLBLO1 $3 /* tlb entry low 1 */ +#endif + + +#define C0_CTXT $4 /* tlb context */ + +#if __mips == 3 +#define C0_PAGEMASK $5 /* tlb page mask */ +#define C0_WIRED $6 /* number of wired tlb entries */ +#endif + +#if __mips == 32 +#define C0_PAGEMASK $5 /* tlb page mask */ +#define C0_WIRED $6 /* number of wired tlb entries */ +#endif + +#if __mips == 1 +#define C0_TAR $6 +#endif + +#define C0_BADVADDR $8 /* bad virtual address */ + +#if __mips == 3 +#define C0_COUNT $9 /* cycle count */ +#endif +#if __mips == 32 +#define C0_COUNT $9 /* cycle count */ +#endif + +#define C0_TLBHI $10 /* tlb entry hi */ + +#if __mips == 3 +#define C0_COMPARE $11 /* cyccle count comparator */ +#endif + +#if __mips == 32 +#define C0_COMPARE $11 /* cyccle count comparator */ +#endif + +#define C0_SR $12 /* status register */ +#define C0_CAUSE $13 /* exception cause */ +#define C0_EPC $14 /* exception pc */ +#define C0_PRID $15 /* revision identifier */ + +#if __mips == 1 +#define C0_CONFIG $3 /* configuration register R3081*/ +#endif + +#if __mips == 3 +#define C0_CONFIG $16 /* configuration register */ +#define C0_LLADDR $17 /* linked load address */ +#define C0_WATCHLO $18 /* watchpoint trap register */ +#define C0_WATCHHI $19 /* watchpoint trap register */ +#define C0_XCTXT $20 /* extended tlb context */ +#define C0_ECC $26 /* secondary cache ECC control */ +#define C0_CACHEERR $27 /* cache error status */ +#define C0_TAGLO $28 /* cache tag lo */ +#define C0_TAGHI $29 /* cache tag hi */ +#define C0_ERRPC $30 /* cache error pc */ +#endif + +#if __mips == 32 +#define C0_CONFIG $16 /* configuration register */ +#define C0_LLADDR $17 /* linked load address */ +#define C0_WATCHLO $18 /* watchpoint trap register */ +#define C0_WATCHHI $19 /* watchpoint trap register */ +#define C0_XCTXT $20 /* extended tlb context */ +#define C0_ECC $26 /* secondary cache ECC control */ +#define C0_CACHEERR $27 /* cache error status */ +#define C0_TAGLO $28 /* cache tag lo */ +#define C0_TAGHI $29 /* cache tag hi */ +#define C0_ERRPC $30 /* cache error pc */ +#endif + + +#define C1_REVISION $0 +#define C1_STATUS $31 + +#endif /* XDS */ + +#ifdef R4650 +#define IWATCH $18 +#define DWATCH $19 +#define IBASE $0 +#define IBOUND $1 +#define DBASE $2 +#define DBOUND $3 +#define CALG $17 +#endif + +/**@}*/ +#endif /* _RTEMS_MIPS_IDTCPU_H */ diff --git a/cpukit/score/cpu/mips/include/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/include/rtems/mips/iregdef.h new file mode 100644 index 0000000000..5d41074184 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/mips/iregdef.h @@ -0,0 +1,337 @@ +/** + * @file iregdef.h + * + * @brief IDT R3000 Register Structure + * + * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves + * added Register definition for XContext reg. + * Look towards end of this file. + */ + +/* + * Copyright 1989 Integrated Device Technology, Inc + * All Rights Reserved + * + * Based upon IDT provided code with the following release: + * + * This source code has been made available to you by IDT on an AS-IS + * basis. Anyone receiving this source is licensed under IDT copyrights + * to use it in any way he or she deems fit, including copying it, + * modifying it, compiling it, and redistributing it either with or + * without modifications. No license under IDT patents or patent + * applications is to be implied by the copyright license. + * + * Any user of this software should understand that IDT cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work must + * include the IDT copyright notice, this paragraph, and the preceeding + * two paragraphs in the transferred software. + * + * COPYRIGHT IDT CORPORATION 1996 + * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + */ + +#ifndef _RTEMS_MIPS_IREGDEF_H +#define _RTEMS_MIPS_IREGDEF_H + +/** + * @defgroup MipsSet_iregdef Register Structure + * + * @ingroup MIPS + * + */ +/**@{*/ + +/* register names */ + +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 + +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 +#define r25 $25 +#define r26 $26 +#define r27 $27 +#define r28 $28 +#define r29 $29 +#define r30 $30 +#define r31 $31 + +#define fp0 $f0 +#define fp1 $f1 +#define fp2 $f2 +#define fp3 $f3 +#define fp4 $f4 +#define fp5 $f5 +#define fp6 $f6 +#define fp7 $f7 +#define fp8 $f8 +#define fp9 $f9 +#define fp10 $f10 +#define fp11 $f11 +#define fp12 $f12 +#define fp13 $f13 +#define fp14 $f14 +#define fp15 $f15 +#define fp16 $f16 +#define fp17 $f17 +#define fp18 $f18 +#define fp19 $f19 +#define fp20 $f20 +#define fp21 $f21 +#define fp22 $f22 +#define fp23 $f23 +#define fp24 $f24 +#define fp25 $f25 +#define fp26 $f26 +#define fp27 $f27 +#define fp28 $f28 +#define fp29 $f29 +#define fp30 $f30 +#define fp31 $f31 + +#define fcr0 $0 +#define fcr30 $30 +#define fcr31 $31 + +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers a0-a3 */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved t0-t9 */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved s0-s8 */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel usage */ +#define k1 $27 /* kernel usage */ +#define gp $28 /* sdata pointer */ +#define sp $29 /* stack pointer */ +#define s8 $30 /* yet another saved reg for the callee */ +#define fp $30 /* frame pointer - this is being phased out by MIPS */ +#define ra $31 /* return address */ + + +/* +** relative position of registers in interrupt/exception frame +*/ +#define R_R0 0 +#define R_R1 1 +#define R_R2 2 +#define R_R3 3 +#define R_R4 4 +#define R_R5 5 +#define R_R6 6 +#define R_R7 7 +#define R_R8 8 +#define R_R9 9 +#define R_R10 10 +#define R_R11 11 +#define R_R12 12 +#define R_R13 13 +#define R_R14 14 +#define R_R15 15 +#define R_R16 16 +#define R_R17 17 +#define R_R18 18 +#define R_R19 19 +#define R_R20 20 +#define R_R21 21 +#define R_R22 22 +#define R_R23 23 +#define R_R24 24 +#define R_R25 25 +#define R_R26 26 +#define R_R27 27 +#define R_R28 28 +#define R_R29 29 +#define R_R30 30 +#define R_R31 31 + +#define R_SR 32 +#define R_MDLO 33 +#define R_MDHI 34 +#define R_BADVADDR 35 +#define R_CAUSE 36 +#define R_EPC 37 + +#define R_F0 38 +#define R_F1 39 +#define R_F2 40 +#define R_F3 41 +#define R_F4 42 +#define R_F5 43 +#define R_F6 44 +#define R_F7 45 +#define R_F8 46 +#define R_F9 47 +#define R_F10 48 +#define R_F11 49 +#define R_F12 50 +#define R_F13 41 +#define R_F14 42 +#define R_F15 43 +#define R_F16 44 +#define R_F17 45 +#define R_F18 56 +#define R_F19 57 +#define R_F20 58 +#define R_F21 59 +#define R_F22 60 +#define R_F23 61 +#define R_F24 62 +#define R_F25 63 +#define R_F26 64 +#define R_F27 65 +#define R_F28 66 +#define R_F29 67 +#define R_F30 68 +#define R_F31 69 +#define R_FCSR 70 +#define R_FEIR 71 +#define R_TLBHI 72 + +#if __mips == 1 +#define R_TLBLO 73 +#endif +#if (__mips == 3 ) || ( __mips == 32) +#define R_TLBLO0 73 +#endif + +#define R_INX 74 +#define R_RAND 75 +#define R_CTXT 76 +#define R_EXCTYPE 77 +#define R_MODE 78 +#define R_PRID 79 +#define R_TAR 80 +#if __mips == 1 +#define NREGS 81 +#endif +#if (__mips == 3 ) || ( __mips == 32) +#define R_TLBLO1 81 +#define R_PAGEMASK 82 +#define R_WIRED 83 +#define R_COUNT 84 +#define R_COMPARE 85 +#define R_CONFIG 86 +#define R_LLADDR 87 +#define R_WATCHLO 88 +#define R_WATCHHI 89 +#define R_ECC 90 +#define R_CACHEERR 91 +#define R_TAGLO 92 +#define R_TAGHI 93 +#define R_ERRPC 94 +#define R_XCTXT 95 /* Ketan added from SIM64bit */ + +#define NREGS 96 +#endif + +/* +** For those who like to think in terms of the compiler names for the regs +*/ +#define R_ZERO R_R0 +#define R_AT R_R1 +#define R_V0 R_R2 +#define R_V1 R_R3 +#define R_A0 R_R4 +#define R_A1 R_R5 +#define R_A2 R_R6 +#define R_A3 R_R7 +#define R_T0 R_R8 +#define R_T1 R_R9 +#define R_T2 R_R10 +#define R_T3 R_R11 +#define R_T4 R_R12 +#define R_T5 R_R13 +#define R_T6 R_R14 +#define R_T7 R_R15 +#define R_S0 R_R16 +#define R_S1 R_R17 +#define R_S2 R_R18 +#define R_S3 R_R19 +#define R_S4 R_R20 +#define R_S5 R_R21 +#define R_S6 R_R22 +#define R_S7 R_R23 +#define R_T8 R_R24 +#define R_T9 R_R25 +#define R_K0 R_R26 +#define R_K1 R_R27 +#define R_GP R_R28 +#define R_SP R_R29 +#define R_FP R_R30 +#define R_RA R_R31 + +/* disabled for RTEMS */ +#if 0 +/* Ketan added the following */ +#if __mips == 1 +#define sreg sw +#define lreg lw +#define rmfc0 mfc0 +#define rmtc0 mtc0 +#define R_SZ 4 +#endif /* __mips == 1 */ + +/* #ifdef __mips == 3 */ +#if __mips < 3 +#define sreg sw +#define lreg lw +#define rmfc0 mfc0 +#define rmtc0 mtc0 +#define R_SZ 4 +#else +#define sreg sd +#define lreg ld +#define rmfc0 dmfc0 +#define rmtc0 dmtc0 +#define R_SZ 8 +#endif +/* #endif __mips == 3 */ +/* Ketan till here */ +#endif + +/**@}*/ +#endif /* _RTEMS_MIPS_IREGDEF_H */ diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpu.h b/cpukit/score/cpu/mips/include/rtems/score/cpu.h new file mode 100644 index 0000000000..74afc800b9 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/score/cpu.h @@ -0,0 +1,1010 @@ +/** + * @file + * + * @brief Mips CPU Dependent Header File + */ + +/* + * Conversion to MIPS port by Alan Cudmore and + * Joel Sherrill . + * + * These changes made the code conditional on standard cpp predefines, + * merged the mips1 and mips3 code sequences as much as possible, + * and moved some of the assembly code to C. Alan did much of the + * initial analysis and rework. Joel took over from there and + * wrote the JMR3904 BSP so this could be tested. Joel also + * added the new interrupt vectoring support in libcpu and + * tried to better support the various interrupt controllers. + * + */ + +/* + * Original MIP64ORION port by Craig Lebakken + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +/** + * @defgroup ScoreCPU CPU CPU + * + * @ingroup Score + * + */ +/**@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * MIPS Specific Information: + * + * Up to and including RTEMS 4.10, the MIPS port used simple vectored + * interrupts. But this was changed to the PIC model after 4.10. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + */ + +#define CPU_ISR_PASSES_FRAME_POINTER TRUE + + + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "MIPS_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if ( MIPS_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPU in which this option has been used is the + * HP PA-RISC. The HP C compiler and gcc both implicitly use the + * floating point registers to perform integer multiplies. If + * a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Mips Note: It appears the GCC can implicitly generate FPU + * and Altivec instructions when you least expect them. So make + * all tasks floating point. + */ + +#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body + * must be provided and is the default IDLE thread body instead of + * _Internal_threads_Idle_thread_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +/* we can use the low power wait instruction for the IDLE thread */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +/* our stack grows down */ +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 16 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + */ + +#define CPU_MODES_INTERRUPT_MASK 0x000000ff + +#define CPU_SIZEOF_POINTER 4 + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures + * + * Examples structures include the descriptor tables from the i386 + * and the processor control structure on the i960ca. + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +#ifndef ASM + +/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ +#if (__mips == 1) || (__mips == 32) +#define __MIPS_REGISTER_TYPE uint32_t +#define __MIPS_FPU_REGISTER_TYPE uint32_t +#elif __mips == 3 +#define __MIPS_REGISTER_TYPE uint64_t +#define __MIPS_FPU_REGISTER_TYPE uint64_t +#else +#error "mips register size: unknown architecture level!!" +#endif +typedef struct { + __MIPS_REGISTER_TYPE s0; + __MIPS_REGISTER_TYPE s1; + __MIPS_REGISTER_TYPE s2; + __MIPS_REGISTER_TYPE s3; + __MIPS_REGISTER_TYPE s4; + __MIPS_REGISTER_TYPE s5; + __MIPS_REGISTER_TYPE s6; + __MIPS_REGISTER_TYPE s7; + __MIPS_REGISTER_TYPE sp; + __MIPS_REGISTER_TYPE fp; + __MIPS_REGISTER_TYPE ra; + __MIPS_REGISTER_TYPE c0_sr; + __MIPS_REGISTER_TYPE c0_epc; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (uintptr_t) (_context)->sp + +/* WARNING: If this structure is modified, the constants in cpu.h + * must also be updated. + */ + +typedef struct { +#if ( CPU_HARDWARE_FP == TRUE ) + __MIPS_FPU_REGISTER_TYPE fp0; + __MIPS_FPU_REGISTER_TYPE fp1; + __MIPS_FPU_REGISTER_TYPE fp2; + __MIPS_FPU_REGISTER_TYPE fp3; + __MIPS_FPU_REGISTER_TYPE fp4; + __MIPS_FPU_REGISTER_TYPE fp5; + __MIPS_FPU_REGISTER_TYPE fp6; + __MIPS_FPU_REGISTER_TYPE fp7; + __MIPS_FPU_REGISTER_TYPE fp8; + __MIPS_FPU_REGISTER_TYPE fp9; + __MIPS_FPU_REGISTER_TYPE fp10; + __MIPS_FPU_REGISTER_TYPE fp11; + __MIPS_FPU_REGISTER_TYPE fp12; + __MIPS_FPU_REGISTER_TYPE fp13; + __MIPS_FPU_REGISTER_TYPE fp14; + __MIPS_FPU_REGISTER_TYPE fp15; + __MIPS_FPU_REGISTER_TYPE fp16; + __MIPS_FPU_REGISTER_TYPE fp17; + __MIPS_FPU_REGISTER_TYPE fp18; + __MIPS_FPU_REGISTER_TYPE fp19; + __MIPS_FPU_REGISTER_TYPE fp20; + __MIPS_FPU_REGISTER_TYPE fp21; + __MIPS_FPU_REGISTER_TYPE fp22; + __MIPS_FPU_REGISTER_TYPE fp23; + __MIPS_FPU_REGISTER_TYPE fp24; + __MIPS_FPU_REGISTER_TYPE fp25; + __MIPS_FPU_REGISTER_TYPE fp26; + __MIPS_FPU_REGISTER_TYPE fp27; + __MIPS_FPU_REGISTER_TYPE fp28; + __MIPS_FPU_REGISTER_TYPE fp29; + __MIPS_FPU_REGISTER_TYPE fp30; + __MIPS_FPU_REGISTER_TYPE fp31; + uint32_t fpcs; +#endif +} Context_Control_fp; + +/* + * This struct reflects the stack frame employed in ISR_Handler. Note + * that the ISR routine save some of the registers to this frame for + * all interrupts and exceptions. Other registers are saved only on + * exceptions, while others are not touched at all. The untouched + * registers are not normally disturbed by high-level language + * programs so they can be accessed when required. + * + * The registers and their ordering in this struct must directly + * correspond to the layout and ordering of * shown in iregdef.h, + * as cpu_asm.S uses those definitions to fill the stack frame. + * This struct provides access to the stack frame for C code. + * + * Similarly, this structure is used by debugger stubs and exception + * processing routines so be careful when changing the format. + * + * NOTE: The comments with this structure and cpu_asm.S should be kept + * in sync. When in doubt, look in the code to see if the + * registers you're interested in are actually treated as expected. + * The order of the first portion of this structure follows the + * order of registers expected by gdb. + */ + +typedef struct +{ + __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ + __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ + __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ + __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ + __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ + __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ + __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ + __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ + __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ + __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ + __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ + __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ + __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ + __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ + __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ + __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ + __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ + __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ + __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ + __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ + __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ + __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ + __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ + __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ + __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ + /* manipulated per-thread */ + __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ + __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ + __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ + __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ + __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ + /* but logically restored */ + __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ + __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ + /* (oddly not documented on MGV) */ + __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ + /* (oddly not documented on MGV) */ + + /* GDB does not seem to care about anything past this point */ + + __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ +#if __mips == 1 + __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ +#endif +#if (__mips == 3) || (__mips == 32) + __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ +#endif + + __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ + __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ + __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ + __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ + __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ + __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ + __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ + /* end of __mips == 1 so NREGS == 81 */ +#if (__mips == 3) || (__mips == 32) + __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ + /* end of __mips == 3 so NREGS == 96 */ +#endif + +} CPU_Interrupt_frame; + +typedef CPU_Interrupt_frame CPU_Exception_frame; + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +extern Context_Control_fp _CPU_Null_fp_context; + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +/* XXX: if needed, put more variables here */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * system initialization thread. Remember that in a multiprocessor + * system the system intialization thread becomes the MP server thread. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + */ + +#define CPU_STACK_MINIMUM_SIZE (8 * 1024) + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ + +#define CPU_ALIGNMENT 8 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +void mips_vector_exceptions( CPU_Interrupt_frame *frame ); + +/* + * ISR handler macros + */ + +/* + * Declare the function that is present in the shared libcpu directory, + * that returns the processor dependent interrupt mask. + */ + +uint32_t mips_interrupt_mask( void ); + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + */ + +#define _CPU_ISR_Disable( _level ) \ + do { \ + unsigned int _scratch; \ + mips_get_sr( _scratch ); \ + mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ + _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ + } while(0) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _level ) \ + do { \ + unsigned int _scratch; \ + mips_get_sr( _scratch ); \ + mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ + } while(0) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _xlevel ) \ + do { \ + unsigned int _scratch2 = _xlevel; \ + _CPU_ISR_Enable( _scratch2 ); \ + _CPU_ISR_Disable( _scratch2 ); \ + _xlevel = _scratch2; \ + } while(0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * On the MIPS, 0 is all on. Non-zero is all off. This only + * manipulates the IEC. + */ + +uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ + +void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + * The per-thread status register holds the interrupt enable, FP enable + * and global interrupt enable for that thread. It means each thread can + * enable its own set of interrupts. If interrupts are disabled, RTEMS + * can still dispatch via blocking calls. This is the function of the + * "Interrupt Level", and on the MIPS, it controls the IEC bit and all + * the hardware interrupts as defined in the SR. Software ints + * are automatically enabled for all threads, as they will only occur under + * program control anyhow. Besides, the interrupt level parm is only 8 bits, + * and controlling the software ints plus the others would require 9. + * + * If the Interrupt Level is 0, all ints are on. Otherwise, the + * Interrupt Level should supply a bit pattern to impose on the SR + * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 + * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of + * the Interrupt Level parameter is unused at this time. + * + * These are the only per-thread SR bits, the others are maintained + * globally & explicitly preserved by the Context Switch code in cpu_asm.s + */ + + +#if (__mips == 3) || (__mips == 32) +#define _INTON SR_IE +#if __mips_fpr==64 +#define _EXTRABITS SR_FR +#else +#define _EXTRABITS 0 +#endif /* __mips_fpr==64 */ +#endif /* __mips == 3 */ +#if __mips == 1 +#define _INTON SR_IEC +#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ +#endif /* __mips == 1 */ + + +void _CPU_Context_Initialize( + Context_Control *the_context, + uintptr_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + */ + +#if ( CPU_HARDWARE_FP == TRUE ) +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } +#endif + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ + +#define _CPU_Fatal_halt( _source, _error ) \ + do { \ + unsigned int _level; \ + _CPU_ISR_Disable(_level); \ + (void)_level; \ + loop: goto loop; \ + } while (0) + + +extern void mips_break( int error ); + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Internal_threads_Idle_thread_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + */ + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif + + + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/mips/include/rtems/score/mips.h b/cpukit/score/cpu/mips/include/rtems/score/mips.h new file mode 100644 index 0000000000..4c2c53fa6d --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/score/mips.h @@ -0,0 +1,299 @@ +/** + * @file rtems/score/mips.h + * + * @brief Information to build RTEMS for a "no cpu" while in protected mode. + * + * This file contains the information required to build + * RTEMS for a particular member of the "no cpu" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +/* + * COPYRIGHT (c) 1989-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_MIPS_H +#define _RTEMS_SCORE_MIPS_H + +/** + * @defgroup ScoreMips RTEMS no cpu Build Information + * + * @ingroup Score + * + */ +/**@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ASM +#include +#endif + +/* + * SR bits that enable/disable interrupts + * + * NOTE: XXX what about SR_ERL? + */ + +#if (__mips == 3) || (__mips == 32) +#ifdef ASM +#define SR_INTERRUPT_ENABLE_BITS 0x01 +#else +#define SR_INTERRUPT_ENABLE_BITS SR_IE +#endif + +#elif __mips == 1 +#define SR_INTERRUPT_ENABLE_BITS SR_IEC + +#else +#error "mips interrupt enable bits: unknown architecture level!" +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "no cpu" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif + + +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) || (__mips == 32) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" +#else +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "MIPS" + +/* + * RTEMS Vector numbers for exception conditions. This is a direct + * map to the causes. + */ + +#define MIPS_EXCEPTION_BASE 0 + +#define MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0 +#define MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1 +#define MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2 +#define MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3 +#define MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4 +#define MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5 +#define MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6 +#define MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7 +#define MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8 +#define MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9 +#define MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10 +#define MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11 +#define MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12 +#define MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13 +#define MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14 +/* FPE only on mips2 and higher */ +#define MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15 +#define MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16 +/* 17-22 reserved */ +#define MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23 +/* 24-30 reserved */ +#define MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31 + +#define MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32 + +/* + * Some macros to access registers + */ + +#define mips_get_sr( _x ) \ + do { \ + __asm__ volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ + } while (0) + +#define mips_set_sr( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ + } while (0) + + +/* + * Access the Cause register + */ + +#define mips_get_cause( _x ) \ + do { \ + __asm__ volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_cause( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ + } while (0) + + + + +/* + * Access the Debug Cache Invalidate Control register + */ + +#define mips_get_dcic( _x ) \ + do { \ + __asm__ volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_dcic( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ + } while (0) + + + + +/* + * Access the Breakpoint Program Counter & Mask registers + * (_x for BPC, _y for mask) + */ + +#define mips_get_bpcrm( _x, _y ) \ + do { \ + __asm__ volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ + __asm__ volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bpcrm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + __asm__ volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ + __asm__ volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ + } while (0) + + + + + + +/* + * Access the Breakpoint Data Address & Mask registers + * (_x for BDA, _y for mask) + */ + +#define mips_get_bdarm( _x, _y ) \ + do { \ + __asm__ volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ + __asm__ volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bdarm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + __asm__ volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ + __asm__ volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ + } while (0) + + + + + + + +/* + * Access FCR31 + */ + +#if ( MIPS_HAS_FPU == 1 ) + +#define mips_get_fcr31( _x ) \ + do { \ + __asm__ volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ + } while(0) + + +#define mips_set_fcr31( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ + } while(0) + +#else + +#define mips_get_fcr31( _x ) +#define mips_set_fcr31( _x ) + +#endif + +/* + * Manipulate interrupt mask + * + * mips_unmask_interrupt( _mask) + * enables interrupts - mask is positioned so it only needs to be or'ed + * into the status reg. This also does some other things !!!! Caution + * should be used if invoking this while in the middle of a debugging + * session where the client may have nested interrupts. + * + * mips_mask_interrupt( _mask ) + * disable the interrupt - mask is the complement of the bits to be + * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff + * + * + * NOTE: mips_mask_interrupt() used to be disable_int(). + * mips_unmask_interrupt() used to be enable_int(). + * + */ + +#define mips_enable_in_interrupt_mask( _mask ) \ + do { \ + unsigned int _sr; \ + mips_get_sr( _sr ); \ + _sr |= (_mask); \ + mips_set_sr( _sr ); \ + } while (0) + +#define mips_disable_in_interrupt_mask( _mask ) \ + do { \ + unsigned int _sr; \ + mips_get_sr( _sr ); \ + _sr &= ~(_mask); \ + mips_set_sr( _sr ); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* _RTEMS_SCORE_MIPS_H */ +/* end of include file */ diff --git a/cpukit/score/cpu/mips/include/rtems/score/types.h b/cpukit/score/cpu/mips/include/rtems/score/types.h new file mode 100644 index 0000000000..e3226a3bb4 --- /dev/null +++ b/cpukit/score/cpu/mips/include/rtems/score/types.h @@ -0,0 +1,56 @@ +/** + * @file rtems/score/types.h + * + * @brief Type Definitions Pertaining to the MIPS Processor Family + * + * This include file contains type definitions pertaining to the MIPS + * processor family. + */ + +/* + * COPYRIGHT (c) 1989-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +/* @(#)mipstypes.h 08/20/96 1.4 */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +/** + * @defgroup ScoreTypes MIPS Processor Family Type Definitions + * + * @ingroup Score + * + */ +/**@{*/ + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void mips_isr; +typedef void ( *mips_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +/**@}*/ +#endif diff --git a/cpukit/score/cpu/mips/preinstall.am b/cpukit/score/cpu/mips/preinstall.am deleted file mode 100644 index 8fa3cc67a3..0000000000 --- a/cpukit/score/cpu/mips/preinstall.am +++ /dev/null @@ -1,62 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/mips/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/mips - @: > $(PROJECT_INCLUDE)/rtems/mips/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/mips/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/mips/idtcpu.h: rtems/mips/idtcpu.h $(PROJECT_INCLUDE)/rtems/mips/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/mips/idtcpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/mips/idtcpu.h - -$(PROJECT_INCLUDE)/rtems/mips/iregdef.h: rtems/mips/iregdef.h $(PROJECT_INCLUDE)/rtems/mips/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/mips/iregdef.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/mips/iregdef.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/mips.h: rtems/score/mips.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/mips.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/mips.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h deleted file mode 100644 index 9c84f61990..0000000000 --- a/cpukit/score/cpu/mips/rtems/asm.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Debugger macros for assembly language routines. Allows the - * programmer to set up the necessary stack frame info - * required by debuggers to do stack traces. - */ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif /* XDS */ - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -#endif -/* end of include file */ - diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h deleted file mode 100644 index 927bbec133..0000000000 --- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h +++ /dev/null @@ -1,708 +0,0 @@ -/** - * @file idtcpu.h - * - * @brief CPU Related Definitions - * - * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves - * added Register definition for XContext reg. - * Look towards end of this file. - */ - -/* - * Based upon IDT provided code with the following release: - * - * This source code has been made available to you by IDT on an AS-IS - * basis. Anyone receiving this source is licensed under IDT copyrights - * to use it in any way he or she deems fit, including copying it, - * modifying it, compiling it, and redistributing it either with or - * without modifications. No license under IDT patents or patent - * applications is to be implied by the copyright license. - * - * Any user of this software should understand that IDT cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work must - * include the IDT copyright notice, this paragraph, and the preceeding - * two paragraphs in the transferred software. - * - * COPYRIGHT IDT CORPORATION 1996 - * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - */ - -#ifndef _RTEMS_MIPS_IDTCPU_H -#define _RTEMS_MIPS_IDTCPU_H - -/** - * @defgroup MipsSet_idtcpu CPU Related Definitions - * - * @ingroup MIPS - * - */ -/**@{*/ - -/* - * 950313: Ketan added Register definition for XContext reg. - * added define for WAIT instruction. - * 950421: Ketan added Register definition for Config reg (R3081) - */ - -/* -** memory configuration and mapping -*/ -#define K0BASE 0x80000000 -#define K0SIZE 0x20000000 -#define K1BASE 0xa0000000 -#define K1SIZE 0x20000000 -#define K2BASE 0xc0000000 -#define K2SIZE 0x20000000 -#if __mips == 3 -#define KSBASE 0xe0000000 -#define KSSIZE 0x20000000 -#endif - -#define KUBASE 0 -#define KUSIZE 0x80000000 - -/* -** Exception Vectors -*/ -#if __mips == 1 -#define UT_VEC K0BASE /* utlbmiss vector */ -#define DB_VEC (K0BASE+0x40) /* debug vector */ -#define E_VEC (K0BASE+0x80) /* exception vector */ -#elif __mips == 32 -#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ -#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ -#define C_VEC (K0BASE+0x100) /* cache error vector */ -#define E_VEC (K0BASE+0x180) /* exception vector */ -#elif __mips == 3 -#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ -#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ -#define C_VEC (K0BASE+0x100) /* cache error vector */ -#define E_VEC (K0BASE+0x180) /* exception vector */ -#else -#error "EXCEPTION VECTORS: unknown ISA level" -#endif -#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ - -/* -** Address conversion macros -*/ -#ifdef CLANGUAGE -#define CAST(as) (as) -#else -#define CAST(as) -#endif -#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ -#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ -#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ -#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ -#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ -#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ - -/* -** Cache size constants -*/ -#define MINCACHE 0x200 /* 512 For 3041. */ -#define MAXCACHE 0x40000 /* 256*1024 256k */ - -#if __mips == 32 -/* R4000 configuration register definitions */ -#define CFG_CM 0x80000000 /* Master-Checker mode */ -#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ -#define CFG_ECBY2 0x00000000 /* divide by 2 */ -#define CFG_ECBY3 0x10000000 /* divide by 3 */ -#define CFG_ECBY4 0x20000000 /* divide by 4 */ -#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ -#define CFG_EPD 0x00000000 /* D */ -#define CFG_EPDDX 0x01000000 /* DDX */ -#define CFG_EPDDXX 0x02000000 /* DDXX */ -#define CFG_EPDXDX 0x03000000 /* DXDX */ -#define CFG_EPDDXXX 0x04000000 /* DDXXX */ -#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ -#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ -#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ -#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ -#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ -#define CFG_SBSHIFT 22 -#define CFG_SB4 0x00000000 /* 4 words */ -#define CFG_SB8 0x00400000 /* 8 words */ -#define CFG_SB16 0x00800000 /* 16 words */ -#define CFG_SB32 0x00c00000 /* 32 words */ -#define CFG_SS 0x00200000 /* Split secondary cache */ -#define CFG_SW 0x00100000 /* Secondary cache port width */ -#define CFG_EWMASK 0x000c0000 /* System port width */ -#define CFG_EWSHIFT 18 -#define CFG_EW64 0x00000000 /* 64 bit */ -#define CFG_EW32 0x00010000 /* 32 bit */ -#define CFG_SC 0x00020000 /* Secondary cache absent */ -#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ -#define CFG_BE 0x00008000 /* Big Endian */ -#define CFG_EM 0x00004000 /* ECC mode enable */ -#define CFG_EB 0x00002000 /* Block ordering */ -#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ -#define CFG_ICSHIFT 9 -#define CFG_DCMASK 0x000001c0 /* Data cache size */ -#define CFG_DCSHIFT 6 -#define CFG_IB 0x00000020 /* Instruction cache block size */ -#define CFG_DB 0x00000010 /* Data cache block size */ -#define CFG_CU 0x00000008 /* Update on Store Conditional */ -#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ - -/* - * R4000 primary cache mode - */ -#define CFG_C_UNCACHED 2 -#define CFG_C_NONCOHERENT 3 -#define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 -#define CFG_C_COHERENTUPD 6 - -/* - * R4000 cache operations (should be in assembler...?) - */ -#define Index_Invalidate_I 0x0 /* 0 0 */ -#define Index_Writeback_Inv_D 0x1 /* 0 1 */ -#define Index_Invalidate_SI 0x2 /* 0 2 */ -#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ -#define Index_Load_Tag_I 0x4 /* 1 0 */ -#define Index_Load_Tag_D 0x5 /* 1 1 */ -#define Index_Load_Tag_SI 0x6 /* 1 2 */ -#define Index_Load_Tag_SD 0x7 /* 1 3 */ -#define Index_Store_Tag_I 0x8 /* 2 0 */ -#define Index_Store_Tag_D 0x9 /* 2 1 */ -#define Index_Store_Tag_SI 0xA /* 2 2 */ -#define Index_Store_Tag_SD 0xB /* 2 3 */ -#define Create_Dirty_Exc_D 0xD /* 3 1 */ -#define Create_Dirty_Exc_SD 0xF /* 3 3 */ -#define Hit_Invalidate_I 0x10 /* 4 0 */ -#define Hit_Invalidate_D 0x11 /* 4 1 */ -#define Hit_Invalidate_SI 0x12 /* 4 2 */ -#define Hit_Invalidate_SD 0x13 /* 4 3 */ -#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ -#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ -#define Fill_I 0x14 /* 5 0 */ -#define Hit_Writeback_D 0x19 /* 6 1 */ -#define Hit_Writeback_SD 0x1B /* 6 3 */ -#define Hit_Writeback_I 0x18 /* 6 0 */ -#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ -#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ - -/* Disabled by chris -- horrible overload of common word. -#ifndef WAIT -#define WAIT .word 0x42000020 -#endif -*/ -/* Disabled by joel -- horrible overload of common word. -#ifndef wait -#define wait .word 0x42000020 -#endif wait -*/ - -#endif - -#if __mips == 3 -/* R4000 configuration register definitions */ -#define CFG_CM 0x80000000 /* Master-Checker mode */ -#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ -#define CFG_ECBY2 0x00000000 /* divide by 2 */ -#define CFG_ECBY3 0x10000000 /* divide by 3 */ -#define CFG_ECBY4 0x20000000 /* divide by 4 */ -#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ -#define CFG_EPD 0x00000000 /* D */ -#define CFG_EPDDX 0x01000000 /* DDX */ -#define CFG_EPDDXX 0x02000000 /* DDXX */ -#define CFG_EPDXDX 0x03000000 /* DXDX */ -#define CFG_EPDDXXX 0x04000000 /* DDXXX */ -#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ -#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ -#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ -#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ -#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ -#define CFG_SBSHIFT 22 -#define CFG_SB4 0x00000000 /* 4 words */ -#define CFG_SB8 0x00400000 /* 8 words */ -#define CFG_SB16 0x00800000 /* 16 words */ -#define CFG_SB32 0x00c00000 /* 32 words */ -#define CFG_SS 0x00200000 /* Split secondary cache */ -#define CFG_SW 0x00100000 /* Secondary cache port width */ -#define CFG_EWMASK 0x000c0000 /* System port width */ -#define CFG_EWSHIFT 18 -#define CFG_EW64 0x00000000 /* 64 bit */ -#define CFG_EW32 0x00010000 /* 32 bit */ -#define CFG_SC 0x00020000 /* Secondary cache absent */ -#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ -#define CFG_BE 0x00008000 /* Big Endian */ -#define CFG_EM 0x00004000 /* ECC mode enable */ -#define CFG_EB 0x00002000 /* Block ordering */ -#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ -#define CFG_ICSHIFT 9 -#define CFG_DCMASK 0x000001c0 /* Data cache size */ -#define CFG_DCSHIFT 6 -#define CFG_IB 0x00000020 /* Instruction cache block size */ -#define CFG_DB 0x00000010 /* Data cache block size */ -#define CFG_CU 0x00000008 /* Update on Store Conditional */ -#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ - -/* - * R4000 primary cache mode - */ -#define CFG_C_UNCACHED 2 -#define CFG_C_NONCOHERENT 3 -#define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 -#define CFG_C_COHERENTUPD 6 - -/* - * R4000 cache operations (should be in assembler...?) - */ -#define Index_Invalidate_I 0x0 /* 0 0 */ -#define Index_Writeback_Inv_D 0x1 /* 0 1 */ -#define Index_Invalidate_SI 0x2 /* 0 2 */ -#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ -#define Index_Load_Tag_I 0x4 /* 1 0 */ -#define Index_Load_Tag_D 0x5 /* 1 1 */ -#define Index_Load_Tag_SI 0x6 /* 1 2 */ -#define Index_Load_Tag_SD 0x7 /* 1 3 */ -#define Index_Store_Tag_I 0x8 /* 2 0 */ -#define Index_Store_Tag_D 0x9 /* 2 1 */ -#define Index_Store_Tag_SI 0xA /* 2 2 */ -#define Index_Store_Tag_SD 0xB /* 2 3 */ -#define Create_Dirty_Exc_D 0xD /* 3 1 */ -#define Create_Dirty_Exc_SD 0xF /* 3 3 */ -#define Hit_Invalidate_I 0x10 /* 4 0 */ -#define Hit_Invalidate_D 0x11 /* 4 1 */ -#define Hit_Invalidate_SI 0x12 /* 4 2 */ -#define Hit_Invalidate_SD 0x13 /* 4 3 */ -#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ -#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ -#define Fill_I 0x14 /* 5 0 */ -#define Hit_Writeback_D 0x19 /* 6 1 */ -#define Hit_Writeback_SD 0x1B /* 6 3 */ -#define Hit_Writeback_I 0x18 /* 6 0 */ -#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ -#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ - -/* Disabled by chris -- horrible overload of common word. -#ifndef WAIT -#define WAIT .word 0x42000020 -#endif -*/ -/* Disabled by joel -- horrible overload of common word. -#ifndef wait -#define wait .word 0x42000020 -#endif wait -*/ - -#endif - -/* -** TLB resource defines -*/ -#if __mips == 1 -#define N_TLB_ENTRIES 64 -#define TLB_PGSIZE 0x1000 -#define RANDBASE 8 -#define TLBLO_PFNMASK 0xfffff000 -#define TLBLO_PFNSHIFT 12 -#define TLBLO_N 0x800 /* non-cacheable */ -#define TLBLO_D 0x400 /* writeable */ -#define TLBLO_V 0x200 /* valid bit */ -#define TLBLO_G 0x100 /* global access bit */ - -#define TLBHI_VPNMASK 0xfffff000 -#define TLBHI_VPNSHIFT 12 -#define TLBHI_PIDMASK 0xfc0 -#define TLBHI_PIDSHIFT 6 -#define TLBHI_NPID 64 - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x00003f00 -#define TLBINX_INXSHIFT 8 - -#define TLBRAND_RANDMASK 0x00003f00 -#define TLBRAND_RANDSHIFT 8 - -#define TLBCTXT_BASEMASK 0xffe00000 -#define TLBCTXT_BASESHIFT 21 - -#define TLBCTXT_VPNMASK 0x001ffffc -#define TLBCTXT_VPNSHIFT 2 -#endif -#if __mips == 3 -#define N_TLB_ENTRIES 48 - -#define TLBHI_VPN2MASK 0xffffe000 -#define TLBHI_PIDMASK 0x000000ff -#define TLBHI_NPID 256 - -#define TLBLO_PFNMASK 0x3fffffc0 -#define TLBLO_PFNSHIFT 6 -#define TLBLO_D 0x00000004 /* writeable */ -#define TLBLO_V 0x00000002 /* valid bit */ -#define TLBLO_G 0x00000001 /* global access bit */ -#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ -#define TLBLO_CSHIFT 3 - -#define TLBLO_UNCACHED (CFG_C_UNCACHED< k, 1 => u */ -#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ -#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ -#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ -#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ -#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ -#endif - -#if __mips == 3 -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_RP 0x08000000 /* Reduced power operation */ -#define SR_FR 0x04000000 /* Additional floating point registers */ -#define SR_RE 0x02000000 /* Reverse endian in user mode */ - -#define SR_BEV 0x00400000 /* Use boot exception vectors */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_SR 0x00100000 /* Soft reset */ -#define SR_CH 0x00040000 /* Cache hit */ -#define SR_CE 0x00020000 /* Use cache ECC */ -#define SR_DE 0x00010000 /* Disable cache exceptions */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KSMASK 0x00000018 /* Kernel mode mask */ -#define SR_KSUSER 0x00000010 /* User mode */ -#define SR_KSSUPER 0x00000008 /* Supervisor mode */ -#define SR_KSKERNEL 0x00000000 /* Kernel mode */ -#define SR_ERL 0x00000004 /* Error level */ -#define SR_EXL 0x00000002 /* Exception level */ -#define SR_IE 0x00000001 /* Interrupts enabled */ -#endif - -#if __mips == 32 -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_RP 0x08000000 /* Reduced power operation */ -#define SR_FR 0x04000000 /* Additional floating point registers */ -#define SR_RE 0x02000000 /* Reverse endian in user mode */ - -#define SR_BEV 0x00400000 /* Use boot exception vectors */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_SR 0x00100000 /* Soft reset */ -#define SR_CH 0x00040000 /* Cache hit */ -#define SR_CE 0x00020000 /* Use cache ECC */ -#define SR_DE 0x00010000 /* Disable cache exceptions */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KSMASK 0x00000018 /* Kernel mode mask */ -#define SR_KSUSER 0x00000010 /* User mode */ -#define SR_KSSUPER 0x00000008 /* Supervisor mode */ -#define SR_KSKERNEL 0x00000000 /* Kernel mode */ -#define SR_ERL 0x00000004 /* Error level */ -#define SR_EXL 0x00000002 /* Exception level */ -#define SR_IE 0x00000001 /* Interrupts enabled */ -#endif - -/* - * Cause Register - */ -#define CAUSE_BD 0x80000000 /* Branch delay slot */ -#define CAUSE_BT 0x40000000 /* Branch Taken */ -#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ -#define CAUSE_CESHIFT 28 - - -#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ -#define CAUSE_IPSHIFT 8 - -#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ -#define CAUSE_EXCSHIFT 2 - -#ifndef XDS -/* -** Coprocessor 0 registers -*/ -#define C0_INX $0 /* tlb index */ -#define C0_RAND $1 /* tlb random */ -#if __mips == 1 -#define C0_TLBLO $2 /* tlb entry low */ -#endif -#if __mips == 3 -#define C0_TLBLO0 $2 /* tlb entry low 0 */ -#define C0_TLBLO1 $3 /* tlb entry low 1 */ -#endif - -#if __mips == 32 -#define C0_TLBLO0 $2 /* tlb entry low 0 */ -#define C0_TLBLO1 $3 /* tlb entry low 1 */ -#endif - - -#define C0_CTXT $4 /* tlb context */ - -#if __mips == 3 -#define C0_PAGEMASK $5 /* tlb page mask */ -#define C0_WIRED $6 /* number of wired tlb entries */ -#endif - -#if __mips == 32 -#define C0_PAGEMASK $5 /* tlb page mask */ -#define C0_WIRED $6 /* number of wired tlb entries */ -#endif - -#if __mips == 1 -#define C0_TAR $6 -#endif - -#define C0_BADVADDR $8 /* bad virtual address */ - -#if __mips == 3 -#define C0_COUNT $9 /* cycle count */ -#endif -#if __mips == 32 -#define C0_COUNT $9 /* cycle count */ -#endif - -#define C0_TLBHI $10 /* tlb entry hi */ - -#if __mips == 3 -#define C0_COMPARE $11 /* cyccle count comparator */ -#endif - -#if __mips == 32 -#define C0_COMPARE $11 /* cyccle count comparator */ -#endif - -#define C0_SR $12 /* status register */ -#define C0_CAUSE $13 /* exception cause */ -#define C0_EPC $14 /* exception pc */ -#define C0_PRID $15 /* revision identifier */ - -#if __mips == 1 -#define C0_CONFIG $3 /* configuration register R3081*/ -#endif - -#if __mips == 3 -#define C0_CONFIG $16 /* configuration register */ -#define C0_LLADDR $17 /* linked load address */ -#define C0_WATCHLO $18 /* watchpoint trap register */ -#define C0_WATCHHI $19 /* watchpoint trap register */ -#define C0_XCTXT $20 /* extended tlb context */ -#define C0_ECC $26 /* secondary cache ECC control */ -#define C0_CACHEERR $27 /* cache error status */ -#define C0_TAGLO $28 /* cache tag lo */ -#define C0_TAGHI $29 /* cache tag hi */ -#define C0_ERRPC $30 /* cache error pc */ -#endif - -#if __mips == 32 -#define C0_CONFIG $16 /* configuration register */ -#define C0_LLADDR $17 /* linked load address */ -#define C0_WATCHLO $18 /* watchpoint trap register */ -#define C0_WATCHHI $19 /* watchpoint trap register */ -#define C0_XCTXT $20 /* extended tlb context */ -#define C0_ECC $26 /* secondary cache ECC control */ -#define C0_CACHEERR $27 /* cache error status */ -#define C0_TAGLO $28 /* cache tag lo */ -#define C0_TAGHI $29 /* cache tag hi */ -#define C0_ERRPC $30 /* cache error pc */ -#endif - - -#define C1_REVISION $0 -#define C1_STATUS $31 - -#endif /* XDS */ - -#ifdef R4650 -#define IWATCH $18 -#define DWATCH $19 -#define IBASE $0 -#define IBOUND $1 -#define DBASE $2 -#define DBOUND $3 -#define CALG $17 -#endif - -/**@}*/ -#endif /* _RTEMS_MIPS_IDTCPU_H */ diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h deleted file mode 100644 index 5d41074184..0000000000 --- a/cpukit/score/cpu/mips/rtems/mips/iregdef.h +++ /dev/null @@ -1,337 +0,0 @@ -/** - * @file iregdef.h - * - * @brief IDT R3000 Register Structure - * - * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves - * added Register definition for XContext reg. - * Look towards end of this file. - */ - -/* - * Copyright 1989 Integrated Device Technology, Inc - * All Rights Reserved - * - * Based upon IDT provided code with the following release: - * - * This source code has been made available to you by IDT on an AS-IS - * basis. Anyone receiving this source is licensed under IDT copyrights - * to use it in any way he or she deems fit, including copying it, - * modifying it, compiling it, and redistributing it either with or - * without modifications. No license under IDT patents or patent - * applications is to be implied by the copyright license. - * - * Any user of this software should understand that IDT cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work must - * include the IDT copyright notice, this paragraph, and the preceeding - * two paragraphs in the transferred software. - * - * COPYRIGHT IDT CORPORATION 1996 - * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - */ - -#ifndef _RTEMS_MIPS_IREGDEF_H -#define _RTEMS_MIPS_IREGDEF_H - -/** - * @defgroup MipsSet_iregdef Register Structure - * - * @ingroup MIPS - * - */ -/**@{*/ - -/* register names */ - -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 - -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 -#define r25 $25 -#define r26 $26 -#define r27 $27 -#define r28 $28 -#define r29 $29 -#define r30 $30 -#define r31 $31 - -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 - -#define fcr0 $0 -#define fcr30 $30 -#define fcr31 $31 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers a0-a3 */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved t0-t9 */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved s0-s8 */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 /* kernel usage */ -#define k1 $27 /* kernel usage */ -#define gp $28 /* sdata pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* yet another saved reg for the callee */ -#define fp $30 /* frame pointer - this is being phased out by MIPS */ -#define ra $31 /* return address */ - - -/* -** relative position of registers in interrupt/exception frame -*/ -#define R_R0 0 -#define R_R1 1 -#define R_R2 2 -#define R_R3 3 -#define R_R4 4 -#define R_R5 5 -#define R_R6 6 -#define R_R7 7 -#define R_R8 8 -#define R_R9 9 -#define R_R10 10 -#define R_R11 11 -#define R_R12 12 -#define R_R13 13 -#define R_R14 14 -#define R_R15 15 -#define R_R16 16 -#define R_R17 17 -#define R_R18 18 -#define R_R19 19 -#define R_R20 20 -#define R_R21 21 -#define R_R22 22 -#define R_R23 23 -#define R_R24 24 -#define R_R25 25 -#define R_R26 26 -#define R_R27 27 -#define R_R28 28 -#define R_R29 29 -#define R_R30 30 -#define R_R31 31 - -#define R_SR 32 -#define R_MDLO 33 -#define R_MDHI 34 -#define R_BADVADDR 35 -#define R_CAUSE 36 -#define R_EPC 37 - -#define R_F0 38 -#define R_F1 39 -#define R_F2 40 -#define R_F3 41 -#define R_F4 42 -#define R_F5 43 -#define R_F6 44 -#define R_F7 45 -#define R_F8 46 -#define R_F9 47 -#define R_F10 48 -#define R_F11 49 -#define R_F12 50 -#define R_F13 41 -#define R_F14 42 -#define R_F15 43 -#define R_F16 44 -#define R_F17 45 -#define R_F18 56 -#define R_F19 57 -#define R_F20 58 -#define R_F21 59 -#define R_F22 60 -#define R_F23 61 -#define R_F24 62 -#define R_F25 63 -#define R_F26 64 -#define R_F27 65 -#define R_F28 66 -#define R_F29 67 -#define R_F30 68 -#define R_F31 69 -#define R_FCSR 70 -#define R_FEIR 71 -#define R_TLBHI 72 - -#if __mips == 1 -#define R_TLBLO 73 -#endif -#if (__mips == 3 ) || ( __mips == 32) -#define R_TLBLO0 73 -#endif - -#define R_INX 74 -#define R_RAND 75 -#define R_CTXT 76 -#define R_EXCTYPE 77 -#define R_MODE 78 -#define R_PRID 79 -#define R_TAR 80 -#if __mips == 1 -#define NREGS 81 -#endif -#if (__mips == 3 ) || ( __mips == 32) -#define R_TLBLO1 81 -#define R_PAGEMASK 82 -#define R_WIRED 83 -#define R_COUNT 84 -#define R_COMPARE 85 -#define R_CONFIG 86 -#define R_LLADDR 87 -#define R_WATCHLO 88 -#define R_WATCHHI 89 -#define R_ECC 90 -#define R_CACHEERR 91 -#define R_TAGLO 92 -#define R_TAGHI 93 -#define R_ERRPC 94 -#define R_XCTXT 95 /* Ketan added from SIM64bit */ - -#define NREGS 96 -#endif - -/* -** For those who like to think in terms of the compiler names for the regs -*/ -#define R_ZERO R_R0 -#define R_AT R_R1 -#define R_V0 R_R2 -#define R_V1 R_R3 -#define R_A0 R_R4 -#define R_A1 R_R5 -#define R_A2 R_R6 -#define R_A3 R_R7 -#define R_T0 R_R8 -#define R_T1 R_R9 -#define R_T2 R_R10 -#define R_T3 R_R11 -#define R_T4 R_R12 -#define R_T5 R_R13 -#define R_T6 R_R14 -#define R_T7 R_R15 -#define R_S0 R_R16 -#define R_S1 R_R17 -#define R_S2 R_R18 -#define R_S3 R_R19 -#define R_S4 R_R20 -#define R_S5 R_R21 -#define R_S6 R_R22 -#define R_S7 R_R23 -#define R_T8 R_R24 -#define R_T9 R_R25 -#define R_K0 R_R26 -#define R_K1 R_R27 -#define R_GP R_R28 -#define R_SP R_R29 -#define R_FP R_R30 -#define R_RA R_R31 - -/* disabled for RTEMS */ -#if 0 -/* Ketan added the following */ -#if __mips == 1 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#endif /* __mips == 1 */ - -/* #ifdef __mips == 3 */ -#if __mips < 3 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#else -#define sreg sd -#define lreg ld -#define rmfc0 dmfc0 -#define rmtc0 dmtc0 -#define R_SZ 8 -#endif -/* #endif __mips == 3 */ -/* Ketan till here */ -#endif - -/**@}*/ -#endif /* _RTEMS_MIPS_IREGDEF_H */ diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h deleted file mode 100644 index 74afc800b9..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ /dev/null @@ -1,1010 +0,0 @@ -/** - * @file - * - * @brief Mips CPU Dependent Header File - */ - -/* - * Conversion to MIPS port by Alan Cudmore and - * Joel Sherrill . - * - * These changes made the code conditional on standard cpp predefines, - * merged the mips1 and mips3 code sequences as much as possible, - * and moved some of the assembly code to C. Alan did much of the - * initial analysis and rework. Joel took over from there and - * wrote the JMR3904 BSP so this could be tested. Joel also - * added the new interrupt vectoring support in libcpu and - * tried to better support the various interrupt controllers. - * - */ - -/* - * Original MIP64ORION port by Craig Lebakken - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -/** - * @defgroup ScoreCPU CPU CPU - * - * @ingroup Score - * - */ -/**@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * MIPS Specific Information: - * - * Up to and including RTEMS 4.10, the MIPS port used simple vectored - * interrupts. But this was changed to the PIC model after 4.10. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER TRUE - - - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MIPS_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( MIPS_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Mips Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -/* we can use the low power wait instruction for the IDLE thread */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -/* our stack grows down */ -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 16 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000ff - -#define CPU_SIZEOF_POINTER 4 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef ASM - -/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ -#if (__mips == 1) || (__mips == 32) -#define __MIPS_REGISTER_TYPE uint32_t -#define __MIPS_FPU_REGISTER_TYPE uint32_t -#elif __mips == 3 -#define __MIPS_REGISTER_TYPE uint64_t -#define __MIPS_FPU_REGISTER_TYPE uint64_t -#else -#error "mips register size: unknown architecture level!!" -#endif -typedef struct { - __MIPS_REGISTER_TYPE s0; - __MIPS_REGISTER_TYPE s1; - __MIPS_REGISTER_TYPE s2; - __MIPS_REGISTER_TYPE s3; - __MIPS_REGISTER_TYPE s4; - __MIPS_REGISTER_TYPE s5; - __MIPS_REGISTER_TYPE s6; - __MIPS_REGISTER_TYPE s7; - __MIPS_REGISTER_TYPE sp; - __MIPS_REGISTER_TYPE fp; - __MIPS_REGISTER_TYPE ra; - __MIPS_REGISTER_TYPE c0_sr; - __MIPS_REGISTER_TYPE c0_epc; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (uintptr_t) (_context)->sp - -/* WARNING: If this structure is modified, the constants in cpu.h - * must also be updated. - */ - -typedef struct { -#if ( CPU_HARDWARE_FP == TRUE ) - __MIPS_FPU_REGISTER_TYPE fp0; - __MIPS_FPU_REGISTER_TYPE fp1; - __MIPS_FPU_REGISTER_TYPE fp2; - __MIPS_FPU_REGISTER_TYPE fp3; - __MIPS_FPU_REGISTER_TYPE fp4; - __MIPS_FPU_REGISTER_TYPE fp5; - __MIPS_FPU_REGISTER_TYPE fp6; - __MIPS_FPU_REGISTER_TYPE fp7; - __MIPS_FPU_REGISTER_TYPE fp8; - __MIPS_FPU_REGISTER_TYPE fp9; - __MIPS_FPU_REGISTER_TYPE fp10; - __MIPS_FPU_REGISTER_TYPE fp11; - __MIPS_FPU_REGISTER_TYPE fp12; - __MIPS_FPU_REGISTER_TYPE fp13; - __MIPS_FPU_REGISTER_TYPE fp14; - __MIPS_FPU_REGISTER_TYPE fp15; - __MIPS_FPU_REGISTER_TYPE fp16; - __MIPS_FPU_REGISTER_TYPE fp17; - __MIPS_FPU_REGISTER_TYPE fp18; - __MIPS_FPU_REGISTER_TYPE fp19; - __MIPS_FPU_REGISTER_TYPE fp20; - __MIPS_FPU_REGISTER_TYPE fp21; - __MIPS_FPU_REGISTER_TYPE fp22; - __MIPS_FPU_REGISTER_TYPE fp23; - __MIPS_FPU_REGISTER_TYPE fp24; - __MIPS_FPU_REGISTER_TYPE fp25; - __MIPS_FPU_REGISTER_TYPE fp26; - __MIPS_FPU_REGISTER_TYPE fp27; - __MIPS_FPU_REGISTER_TYPE fp28; - __MIPS_FPU_REGISTER_TYPE fp29; - __MIPS_FPU_REGISTER_TYPE fp30; - __MIPS_FPU_REGISTER_TYPE fp31; - uint32_t fpcs; -#endif -} Context_Control_fp; - -/* - * This struct reflects the stack frame employed in ISR_Handler. Note - * that the ISR routine save some of the registers to this frame for - * all interrupts and exceptions. Other registers are saved only on - * exceptions, while others are not touched at all. The untouched - * registers are not normally disturbed by high-level language - * programs so they can be accessed when required. - * - * The registers and their ordering in this struct must directly - * correspond to the layout and ordering of * shown in iregdef.h, - * as cpu_asm.S uses those definitions to fill the stack frame. - * This struct provides access to the stack frame for C code. - * - * Similarly, this structure is used by debugger stubs and exception - * processing routines so be careful when changing the format. - * - * NOTE: The comments with this structure and cpu_asm.S should be kept - * in sync. When in doubt, look in the code to see if the - * registers you're interested in are actually treated as expected. - * The order of the first portion of this structure follows the - * order of registers expected by gdb. - */ - -typedef struct -{ - __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ - __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ - __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ - __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ - __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ - __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ - __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ - __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ - __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ - __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ - __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ - __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ - __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ - __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ - __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ - __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ - __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ - __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ - __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ - __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ - __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ - __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ - __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ - /* manipulated per-thread */ - __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ - __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ - __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ - __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ - __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ - /* but logically restored */ - __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ - __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - - /* GDB does not seem to care about anything past this point */ - - __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#if __mips == 1 - __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif -#if (__mips == 3) || (__mips == 32) - __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif - - __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ - __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ - /* end of __mips == 1 so NREGS == 81 */ -#if (__mips == 3) || (__mips == 32) - __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ - /* end of __mips == 3 so NREGS == 96 */ -#endif - -} CPU_Interrupt_frame; - -typedef CPU_Interrupt_frame CPU_Exception_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -extern Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (8 * 1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -void mips_vector_exceptions( CPU_Interrupt_frame *frame ); - -/* - * ISR handler macros - */ - -/* - * Declare the function that is present in the shared libcpu directory, - * that returns the processor dependent interrupt mask. - */ - -uint32_t mips_interrupt_mask( void ); - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ - _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ - } while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ - } while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _xlevel ) \ - do { \ - unsigned int _scratch2 = _xlevel; \ - _CPU_ISR_Enable( _scratch2 ); \ - _CPU_ISR_Disable( _scratch2 ); \ - _xlevel = _scratch2; \ - } while(0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * On the MIPS, 0 is all on. Non-zero is all off. This only - * manipulates the IEC. - */ - -uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ - -void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * The per-thread status register holds the interrupt enable, FP enable - * and global interrupt enable for that thread. It means each thread can - * enable its own set of interrupts. If interrupts are disabled, RTEMS - * can still dispatch via blocking calls. This is the function of the - * "Interrupt Level", and on the MIPS, it controls the IEC bit and all - * the hardware interrupts as defined in the SR. Software ints - * are automatically enabled for all threads, as they will only occur under - * program control anyhow. Besides, the interrupt level parm is only 8 bits, - * and controlling the software ints plus the others would require 9. - * - * If the Interrupt Level is 0, all ints are on. Otherwise, the - * Interrupt Level should supply a bit pattern to impose on the SR - * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 - * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of - * the Interrupt Level parameter is unused at this time. - * - * These are the only per-thread SR bits, the others are maintained - * globally & explicitly preserved by the Context Switch code in cpu_asm.s - */ - - -#if (__mips == 3) || (__mips == 32) -#define _INTON SR_IE -#if __mips_fpr==64 -#define _EXTRABITS SR_FR -#else -#define _EXTRABITS 0 -#endif /* __mips_fpr==64 */ -#endif /* __mips == 3 */ -#if __mips == 1 -#define _INTON SR_IEC -#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ -#endif /* __mips == 1 */ - - -void _CPU_Context_Initialize( - Context_Control *the_context, - uintptr_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - unsigned int _level; \ - _CPU_ISR_Disable(_level); \ - (void)_level; \ - loop: goto loop; \ - } while (0) - - -extern void mips_break( int error ); - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif - - - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/mips/rtems/score/cpuatomic.h b/cpukit/score/cpu/mips/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/mips/rtems/score/cpuimpl.h b/cpukit/score/cpu/mips/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h deleted file mode 100644 index 4c2c53fa6d..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ /dev/null @@ -1,299 +0,0 @@ -/** - * @file rtems/score/mips.h - * - * @brief Information to build RTEMS for a "no cpu" while in protected mode. - * - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -/* - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_MIPS_H -#define _RTEMS_SCORE_MIPS_H - -/** - * @defgroup ScoreMips RTEMS no cpu Build Information - * - * @ingroup Score - * - */ -/**@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ASM -#include -#endif - -/* - * SR bits that enable/disable interrupts - * - * NOTE: XXX what about SR_ERL? - */ - -#if (__mips == 3) || (__mips == 32) -#ifdef ASM -#define SR_INTERRUPT_ENABLE_BITS 0x01 -#else -#define SR_INTERRUPT_ENABLE_BITS SR_IE -#endif - -#elif __mips == 1 -#define SR_INTERRUPT_ENABLE_BITS SR_IEC - -#else -#error "mips interrupt enable bits: unknown architecture level!" -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(__mips_soft_float) -#define MIPS_HAS_FPU 0 -#else -#define MIPS_HAS_FPU 1 -#endif - - -#if (__mips == 1) -#define CPU_MODEL_NAME "ISA Level 1 or 2" -#elif (__mips == 3) || (__mips == 32) -#if defined(__mips64) -#define CPU_MODEL_NAME "ISA Level 4" -#else -#define CPU_MODEL_NAME "ISA Level 3" -#endif -#else -#error "Unknown MIPS ISA level" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "MIPS" - -/* - * RTEMS Vector numbers for exception conditions. This is a direct - * map to the causes. - */ - -#define MIPS_EXCEPTION_BASE 0 - -#define MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0 -#define MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1 -#define MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2 -#define MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3 -#define MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4 -#define MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5 -#define MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6 -#define MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7 -#define MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8 -#define MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9 -#define MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10 -#define MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11 -#define MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12 -#define MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13 -#define MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14 -/* FPE only on mips2 and higher */ -#define MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15 -#define MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16 -/* 17-22 reserved */ -#define MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23 -/* 24-30 reserved */ -#define MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31 - -#define MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32 - -/* - * Some macros to access registers - */ - -#define mips_get_sr( _x ) \ - do { \ - __asm__ volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ - } while (0) - -#define mips_set_sr( _x ) \ - do { \ - register unsigned int __x = (_x); \ - __asm__ volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ - } while (0) - - -/* - * Access the Cause register - */ - -#define mips_get_cause( _x ) \ - do { \ - __asm__ volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ - } while (0) - - -#define mips_set_cause( _x ) \ - do { \ - register unsigned int __x = (_x); \ - __asm__ volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ - } while (0) - - - - -/* - * Access the Debug Cache Invalidate Control register - */ - -#define mips_get_dcic( _x ) \ - do { \ - __asm__ volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ - } while (0) - - -#define mips_set_dcic( _x ) \ - do { \ - register unsigned int __x = (_x); \ - __asm__ volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ - } while (0) - - - - -/* - * Access the Breakpoint Program Counter & Mask registers - * (_x for BPC, _y for mask) - */ - -#define mips_get_bpcrm( _x, _y ) \ - do { \ - __asm__ volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ - __asm__ volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ - } while (0) - - -#define mips_set_bpcrm( _x, _y ) \ - do { \ - register unsigned int __x = (_x); \ - register unsigned int __y = (_y); \ - __asm__ volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ - __asm__ volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ - } while (0) - - - - - - -/* - * Access the Breakpoint Data Address & Mask registers - * (_x for BDA, _y for mask) - */ - -#define mips_get_bdarm( _x, _y ) \ - do { \ - __asm__ volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ - __asm__ volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ - } while (0) - - -#define mips_set_bdarm( _x, _y ) \ - do { \ - register unsigned int __x = (_x); \ - register unsigned int __y = (_y); \ - __asm__ volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ - __asm__ volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ - } while (0) - - - - - - - -/* - * Access FCR31 - */ - -#if ( MIPS_HAS_FPU == 1 ) - -#define mips_get_fcr31( _x ) \ - do { \ - __asm__ volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ - } while(0) - - -#define mips_set_fcr31( _x ) \ - do { \ - register unsigned int __x = (_x); \ - __asm__ volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ - } while(0) - -#else - -#define mips_get_fcr31( _x ) -#define mips_set_fcr31( _x ) - -#endif - -/* - * Manipulate interrupt mask - * - * mips_unmask_interrupt( _mask) - * enables interrupts - mask is positioned so it only needs to be or'ed - * into the status reg. This also does some other things !!!! Caution - * should be used if invoking this while in the middle of a debugging - * session where the client may have nested interrupts. - * - * mips_mask_interrupt( _mask ) - * disable the interrupt - mask is the complement of the bits to be - * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff - * - * - * NOTE: mips_mask_interrupt() used to be disable_int(). - * mips_unmask_interrupt() used to be enable_int(). - * - */ - -#define mips_enable_in_interrupt_mask( _mask ) \ - do { \ - unsigned int _sr; \ - mips_get_sr( _sr ); \ - _sr |= (_mask); \ - mips_set_sr( _sr ); \ - } while (0) - -#define mips_disable_in_interrupt_mask( _mask ) \ - do { \ - unsigned int _sr; \ - mips_get_sr( _sr ); \ - _sr &= ~(_mask); \ - mips_set_sr( _sr ); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* _RTEMS_SCORE_MIPS_H */ -/* end of include file */ diff --git a/cpukit/score/cpu/mips/rtems/score/types.h b/cpukit/score/cpu/mips/rtems/score/types.h deleted file mode 100644 index e3226a3bb4..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file rtems/score/types.h - * - * @brief Type Definitions Pertaining to the MIPS Processor Family - * - * This include file contains type definitions pertaining to the MIPS - * processor family. - */ - -/* - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -/* @(#)mipstypes.h 08/20/96 1.4 */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -/** - * @defgroup ScoreTypes MIPS Processor Family Type Definitions - * - * @ingroup Score - * - */ -/**@{*/ - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void mips_isr; -typedef void ( *mips_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/moxie/Makefile.am b/cpukit/score/cpu/moxie/Makefile.am index edd2bd4699..29c9a656c5 100644 --- a/cpukit/score/cpu/moxie/Makefile.am +++ b/cpukit/score/cpu/moxie/Makefile.am @@ -4,19 +4,10 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/moxie.h \ - rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c moxie-exception-frame-print.c cpu_asm.S libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/moxie/headers.am b/cpukit/score/cpu/moxie/headers.am new file mode 100644 index 0000000000..4f253a662b --- /dev/null +++ b/cpukit/score/cpu/moxie/headers.am @@ -0,0 +1,17 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/moxie.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/moxie/include/machine/elf_machdep.h b/cpukit/score/cpu/moxie/include/machine/elf_machdep.h new file mode 100644 index 0000000000..3f0df23cdc --- /dev/null +++ b/cpukit/score/cpu/moxie/include/machine/elf_machdep.h @@ -0,0 +1,15 @@ +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB + +#define ELF32_MACHDEP_ID_CASES \ + case EM_MOXIE: \ + break; + +#define ELF32_MACHDEP_ID EM_MOXIE + +#define ARCH_ELFSIZE 32 + +#define R_MOXIE_NONE 0 +#define R_MOXIE_32 1 +#define R_MOXIE_PCREL10 2 + +#define R_TYPE(name) __CONCAT(R_MOXIE_,name) diff --git a/cpukit/score/cpu/moxie/include/rtems/asm.h b/cpukit/score/cpu/moxie/include/rtems/asm.h new file mode 100644 index 0000000000..fdb182f32f --- /dev/null +++ b/cpukit/score/cpu/moxie/include/rtems/asm.h @@ -0,0 +1,116 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 2011 + * Anthony Green + * + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * $Id: asm.h,v 1.9 2010/06/29 00:31:09 joel Exp $ + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ "$" +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define fp REG(fp) +#define sp REG(sp) +#define r0 REG(r0) +#define r1 REG(r1) +#define r2 REG(r2) +#define r3 REG(r3) +#define r4 REG(r4) +#define r5 REG(r5) +#define r6 REG(r6) +#define r7 REG(r7) +#define r8 REG(r8) +#define r9 REG(r9) +#define r10 REG(r10) +#define r11 REG(r11) +#define r12 REG(r12) +#define r13 REG(r13) + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE asm ( ".text +#define END_CODE "); +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h new file mode 100644 index 0000000000..a3aac9ee41 --- /dev/null +++ b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h @@ -0,0 +1,852 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains information pertaining to the Moxie + * processor. + * + * Copyright (c) 2013 Anthony Green + * + * Based on code with the following copyright.. + * COPYRIGHT (c) 1989-2006, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include /* pick up machine definitions */ + +#include /* printk */ + +/* conditional compilation parameters */ + +/* + * Should this target use 16 or 32 bit object Ids? + * + */ +#define RTEMS_USE_32_BIT_OBJECT + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * MOXIE Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "MOXIE_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_HARDWARE_FP FALSE + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body + * must be provided and is the default IDLE thread body instead of + * _Internal_threads_Idle_thread_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + * + * MOXIE Specific Information: + * + * XXX + * The port initially called a BSP dependent routine called + * IDLE_Monitor. The idle task body can be overridden by + * the BSP in newer versions of RTEMS. + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + * + * MOXIE Specific Information: + * + * XXX + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * MOXIE Specific Information: + * + * XXX + */ + +#define nogap __attribute__ ((packed)) + +typedef struct { + void *fp nogap; + void *sp nogap; + uint32_t r0 nogap; + uint32_t r1 nogap; + uint32_t r2 nogap; + uint32_t r3 nogap; + uint32_t r4 nogap; + uint32_t r5 nogap; + uint32_t r6 nogap; + uint32_t r7 nogap; + uint32_t r8 nogap; + uint32_t r9 nogap; + uint32_t r10 nogap; + uint32_t r11 nogap; + uint32_t r12 nogap; + uint32_t r13 nogap; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->sp + +typedef struct { + double some_float_register[2]; +} Context_Control_fp; + +typedef struct { + uint32_t special_interrupt_register; +} CPU_Interrupt_frame; + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + * + * MOXIE Specific Information: + * + * XXX + */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * system initialization thread. Remember that in a multiprocessor + * system the system intialization thread becomes the MP server thread. + * + * MOXIE Specific Information: + * + * It is highly unlikely the MOXIE will get used in a multiprocessor system. + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \ + (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_STACK_MINIMUM_SIZE (1536) + +/** + * Size of a pointer. + * + * This must be an integer literal that can be used by the assembler. This + * value will be used to calculate offsets of structure members. These + * offsets will be used in assembler code. + */ +#define CPU_SIZEOF_POINTER 4 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_ALIGNMENT 8 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + * MOXIE Specific Information: + * + * XXX + */ +#define CPU_STACK_ALIGNMENT 0 + +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + * + * MOXIE Specific Information: + * + * TODO: As of 7 October 2014, this method is not implemented. + */ +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + (_isr_cookie) = 0; \ + } while (0) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + * + * MOXIE Specific Information: + * + * TODO: As of 7 October 2014, this method is not implemented. + */ +#define _CPU_ISR_Enable( _isr_cookie ) \ + do { \ + (_isr_cookie) = (_isr_cookie); \ + } while (0) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + * + * MOXIE Specific Information: + * + * TODO: As of 7 October 2014, this method is not implemented. + */ +#define _CPU_ISR_Flash( _isr_cookie ) \ + do { \ + _CPU_ISR_Enable( _isr_cookie ); \ + _CPU_ISR_Disable( _isr_cookie ); \ + } while (0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return true; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * MOXIE Specific Information: + * + * TODO: As of 7 October 2014, this method is not implemented. + */ +#define _CPU_ISR_Set_level( _new_level ) \ + { \ + if (_new_level) asm volatile ( "nop\n" ); \ + else asm volatile ( "nop\n" ); \ + } + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + * MOXIE Specific Information: + * + * TODO: As of 7 October 2014, this method does not ensure that the context + * is set up with interrupts disabled/enabled as requested. + */ +#define CPU_CCR_INTERRUPTS_ON 0x80 +#define CPU_CCR_INTERRUPTS_OFF 0x00 + +#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ + _isr, _entry_point, _is_fp, _tls_area ) \ + /* Locate Me */ \ + do { \ + uintptr_t _stack; \ + \ + (void) _is_fp; /* avoid warning for being unused */ \ + (void) _isr; /* avoid warning for being unused */ \ + _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ + *((proc_ptr *)(_stack)) = (_entry_point); \ + _stack -= 4; \ + (_the_context)->fp = (void *)_stack; \ + (_the_context)->sp = (void *)_stack; \ + } while (0) + + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * MOXIE Specific Information: + * + * XXX + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Initialize_fp( _destination ) \ + memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * MOXIE Specific Information: + * + * XXX + */ +#define _CPU_Fatal_halt( _source, _error ) \ + printk("Fatal Error %d.%lu Halted\n",_source,_error); \ + for(;;) + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Internal_threads_Idle_thread_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + * MOXIE Specific Information: + * + * XXX + */ +void *_CPU_Thread_Idle_body( uint32_t ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generallu used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + * + * MOXIE Specific Information: + * + * XXX + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/** + * @brief The set of registers that specifies the complete processor state. + * + * The CPU exception frame may be available in fatal error conditions like for + * example illegal opcodes, instruction fetch errors, or data access errors. + * + * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and + * rtems_exception_frame_print(). + */ +typedef struct { + uint32_t integer_registers [16]; +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * MOXIE Specific Information: + * + * This is the generic implementation. + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/moxie/include/rtems/score/moxie.h b/cpukit/score/cpu/moxie/include/rtems/score/moxie.h new file mode 100644 index 0000000000..66f771aadf --- /dev/null +++ b/cpukit/score/cpu/moxie/include/rtems/score/moxie.h @@ -0,0 +1,43 @@ +/** + * @file rtems/score/moxie.h + */ + +/* + * This file contains information pertaining to the Moxie processor. + * + * COPYRIGHT (c) 2011, 2013 + * Anthony Green + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_MOXIE_H +#define _RTEMS_SCORE_MOXIE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "moxie" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +#define CPU_NAME "Moxie" +#define CPU_MODEL_NAME "MoxieLite" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/moxie/include/rtems/score/types.h b/cpukit/score/cpu/moxie/include/rtems/score/types.h new file mode 100644 index 0000000000..99402b0208 --- /dev/null +++ b/cpukit/score/cpu/moxie/include/rtems/score/types.h @@ -0,0 +1,56 @@ +/** + * @file rtems/score/types.h + */ + +/* + * This file contains information pertaining to the Moxie processor. + * + * COPYRIGHT (c) 2011 + * Anthony Green + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void moxie_isr; +typedef void ( *moxie_isr_entry )( void ); + +#ifdef RTEMS_DEPRECATED_TYPES +typedef bool boolean; /* Boolean value */ +typedef float single_precision; /* single precision float */ +typedef double double_precision; /* double precision float */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/moxie/preinstall.am b/cpukit/score/cpu/moxie/preinstall.am deleted file mode 100644 index 9753489081..0000000000 --- a/cpukit/score/cpu/moxie/preinstall.am +++ /dev/null @@ -1,49 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/moxie.h: rtems/score/moxie.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/moxie.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/moxie.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/moxie/rtems/asm.h b/cpukit/score/cpu/moxie/rtems/asm.h deleted file mode 100644 index fdb182f32f..0000000000 --- a/cpukit/score/cpu/moxie/rtems/asm.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2011 - * Anthony Green - * - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * $Id: asm.h,v 1.9 2010/06/29 00:31:09 joel Exp $ - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ "$" -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define fp REG(fp) -#define sp REG(sp) -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE asm ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/cpu.h b/cpukit/score/cpu/moxie/rtems/score/cpu.h deleted file mode 100644 index a3aac9ee41..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/cpu.h +++ /dev/null @@ -1,852 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the Moxie - * processor. - * - * Copyright (c) 2013 Anthony Green - * - * Based on code with the following copyright.. - * COPYRIGHT (c) 1989-2006, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include /* pick up machine definitions */ - -#include /* printk */ - -/* conditional compilation parameters */ - -/* - * Should this target use 16 or 32 bit object Ids? - * - */ -#define RTEMS_USE_32_BIT_OBJECT - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * MOXIE Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MOXIE_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * MOXIE Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - * - * MOXIE Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * MOXIE Specific Information: - * - * XXX - */ - -#define nogap __attribute__ ((packed)) - -typedef struct { - void *fp nogap; - void *sp nogap; - uint32_t r0 nogap; - uint32_t r1 nogap; - uint32_t r2 nogap; - uint32_t r3 nogap; - uint32_t r4 nogap; - uint32_t r5 nogap; - uint32_t r6 nogap; - uint32_t r7 nogap; - uint32_t r8 nogap; - uint32_t r9 nogap; - uint32_t r10 nogap; - uint32_t r11 nogap; - uint32_t r12 nogap; - uint32_t r13 nogap; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * MOXIE Specific Information: - * - * XXX - */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * MOXIE Specific Information: - * - * It is highly unlikely the MOXIE will get used in a multiprocessor system. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \ - (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_MINIMUM_SIZE (1536) - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return true; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if (_new_level) asm volatile ( "nop\n" ); \ - else asm volatile ( "nop\n" ); \ - } - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method does not ensure that the context - * is set up with interrupts disabled/enabled as requested. - */ -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - /* Locate Me */ \ - do { \ - uintptr_t _stack; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - (void) _isr; /* avoid warning for being unused */ \ - _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - _stack -= 4; \ - (_the_context)->fp = (void *)_stack; \ - (_the_context)->sp = (void *)_stack; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Fatal_halt( _source, _error ) \ - printk("Fatal Error %d.%lu Halted\n",_source,_error); \ - for(;;) - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -void *_CPU_Thread_Idle_body( uint32_t ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** - * @brief The set of registers that specifies the complete processor state. - * - * The CPU exception frame may be available in fatal error conditions like for - * example illegal opcodes, instruction fetch errors, or data access errors. - * - * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and - * rtems_exception_frame_print(). - */ -typedef struct { - uint32_t integer_registers [16]; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * MOXIE Specific Information: - * - * This is the generic implementation. - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/cpuatomic.h b/cpukit/score/cpu/moxie/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/moxie/rtems/score/cpuimpl.h b/cpukit/score/cpu/moxie/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/moxie/rtems/score/moxie.h b/cpukit/score/cpu/moxie/rtems/score/moxie.h deleted file mode 100644 index 66f771aadf..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/moxie.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file rtems/score/moxie.h - */ - -/* - * This file contains information pertaining to the Moxie processor. - * - * COPYRIGHT (c) 2011, 2013 - * Anthony Green - * - * Based on code with the following copyright... - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_MOXIE_H -#define _RTEMS_SCORE_MOXIE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "moxie" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#define CPU_NAME "Moxie" -#define CPU_MODEL_NAME "MoxieLite" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/types.h b/cpukit/score/cpu/moxie/rtems/score/types.h deleted file mode 100644 index 99402b0208..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file rtems/score/types.h - */ - -/* - * This file contains information pertaining to the Moxie processor. - * - * COPYRIGHT (c) 2011 - * Anthony Green - * - * Based on code with the following copyright... - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void moxie_isr; -typedef void ( *moxie_isr_entry )( void ); - -#ifdef RTEMS_DEPRECATED_TYPES -typedef bool boolean; /* Boolean value */ -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/nios2/Makefile.am b/cpukit/score/cpu/nios2/Makefile.am index b3e9d28c01..243f937e51 100644 --- a/cpukit/score/cpu/nios2/Makefile.am +++ b/cpukit/score/cpu/nios2/Makefile.am @@ -3,22 +3,6 @@ include $(top_srcdir)/automake/compile.am CLEANFILES = DISTCLEANFILES = -include_rtemsdir = $(includedir)/rtems - -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score - -include_rtems_score_HEADERS = -include_rtems_score_HEADERS += rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/nios2.h -include_rtems_score_HEADERS += rtems/score/nios2-utility.h -include_rtems_score_HEADERS += rtems/score/nios2-count-zeros.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = @@ -50,6 +34,6 @@ libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) all-local: $(PREINSTALL_FILES) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/nios2/headers.am b/cpukit/score/cpu/nios2/headers.am new file mode 100644 index 0000000000..8cf15f1242 --- /dev/null +++ b/cpukit/score/cpu/nios2/headers.am @@ -0,0 +1,20 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/nios2-count-zeros.h +include_rtems_score_HEADERS += include/rtems/score/nios2-utility.h +include_rtems_score_HEADERS += include/rtems/score/nios2.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/nios2/include/machine/elf_machdep.h b/cpukit/score/cpu/nios2/include/machine/elf_machdep.h new file mode 100644 index 0000000000..3f3c108bf5 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/machine/elf_machdep.h @@ -0,0 +1,46 @@ +/* $NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $ */ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF32_MACHDEP_ID_CASES \ + case EM_ALTERA_NIOS2: \ + break; + +#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ +#define ELF64_MACHDEP_ID_CASES \ + /* no 64-bit ELF machine types supported */ + +#define ELF32_MACHDEP_ID EM_ALTERA_NIOS2 + +/* + * Machine-dependent ELF flags. These are defined by the GNU tools. + */ +#define EF_NIOS2 0x00810000 + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +/* NIOS2 relocation types */ +#define R_NIOS2_NONE 0 +#define R_NIOS2_32 1 +#define R_NIOS2_16 2 +#define R_NIOS2_8 3 +#define R_NIOS2_PC32 4 +#define R_NIOS2_PC16 5 +#define R_NIOS2_PC8 6 +#define R_NIOS2_GOT32 7 +#define R_NIOS2_GOT16 8 +#define R_NIOS2_GOT8 9 +#define R_NIOS2_GOT32O 10 +#define R_NIOS2_GOT16O 11 +#define R_NIOS2_GOT8O 12 +#define R_NIOS2_PLT32 13 +#define R_NIOS2_PLT16 14 +#define R_NIOS2_PLT8 15 +#define R_NIOS2_PLT32O 16 +#define R_NIOS2_PLT16O 17 +#define R_NIOS2_PLT8O 18 +#define R_NIOS2_COPY 19 +#define R_NIOS2_GLOB_DAT 20 +#define R_NIOS2_JMP_SLOT 21 +#define R_NIOS2_RELATIVE 22 + +#define R_TYPE(name) __CONCAT(R_NIOS2_,name) diff --git a/cpukit/score/cpu/nios2/include/rtems/asm.h b/cpukit/score/cpu/nios2/include/rtems/asm.h new file mode 100644 index 0000000000..45ccd8b050 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/asm.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * @note The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpu.h b/cpukit/score/cpu/nios2/include/rtems/score/cpu.h new file mode 100644 index 0000000000..a3f2f03d36 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/cpu.h @@ -0,0 +1,372 @@ +/** + * @file + * + * @brief Altera Nios II CPU Department Source + */ + +/* + * Copyright (c) 2011 embedded brains GmbH + * + * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) + * + * COPYRIGHT (c) 1989-2004. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +#define CPU_HARDWARE_FP FALSE + +#define CPU_SOFTWARE_FP FALSE + +#define CPU_CONTEXT_FP_SIZE 0 + +#define CPU_ALL_TASKS_ARE_FP FALSE + +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT \ + RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +#define CPU_STACK_MINIMUM_SIZE (4 * 1024) + +#define CPU_SIZEOF_POINTER 4 + +/* + * Alignment value according to "Nios II Processor Reference" chapter 7 + * "Application Binary Interface" section "Memory Alignment". + */ +#define CPU_ALIGNMENT 4 + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * Alignment value according to "Nios II Processor Reference" chapter 7 + * "Application Binary Interface" section "Stacks". + */ +#define CPU_STACK_ALIGNMENT 4 + +/* + * A Nios II configuration with an external interrupt controller (EIC) supports + * up to 64 interrupt levels. A Nios II configuration with an internal + * interrupt controller (IIC) has only two interrupt levels (enabled and + * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will + * take care about configuration specific mappings. + */ +#define CPU_MODES_INTERRUPT_MASK 0x3f + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +#define CPU_MAXIMUM_PROCESSORS 32 + +#ifndef ASM + +/** + * @brief Thread register context. + * + * The thread register context covers the non-volatile registers, the thread + * stack pointer, the return address, and the processor status. + * + * There is no need to save the global pointer (gp) since it is a system wide + * constant and set-up with the C runtime environment. + * + * The @a thread_dispatch_disabled field is used for the external interrupt + * controller (EIC) support. + * + * @see _Nios2_Thread_dispatch_disabled + */ +typedef struct { + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t fp; + uint32_t status; + uint32_t sp; + uint32_t ra; + uint32_t thread_dispatch_disabled; + uint32_t stack_mpubase; + uint32_t stack_mpuacc; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->sp + +typedef void CPU_Interrupt_frame; + +typedef struct { + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t gp; + uint32_t fp; + uint32_t sp; + uint32_t ra; + uint32_t et; + uint32_t ea; + uint32_t status; + uint32_t ienable; + uint32_t ipending; +} CPU_Exception_frame; + +#define _CPU_Initialize_vectors() + +/** + * @brief Macro to disable interrupts. + * + * The processor status before disabling the interrupts will be stored in + * @a _isr_cookie. This value will be used in _CPU_ISR_Flash() and + * _CPU_ISR_Enable(). + * + * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in + * the status register representing the interrupt level. The global symbol + * _Nios2_ISR_Status_bits will be used to set the bits representing an + * interrupt level that disables interrupts. Both global symbols must be + * provided by the board support package. + * + * In case the Nios II uses the internal interrupt controller (IIC), then only + * the PIE status bit is used. + * + * In case the Nios II uses the external interrupt controller (EIC), then the + * RSIE status bit or the IL status field is used depending on the interrupt + * handling variant and the shadow register usage. + */ +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + int _tmp; \ + __asm__ volatile ( \ + "rdctl %0, status\n" \ + "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ + "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ + "and %1, %0, %1\n" \ + "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ + "wrctl status, %1" \ + : "=&r" (_isr_cookie), "=&r" (_tmp) \ + ); \ + } while ( 0 ) + +/** + * @brief Macro to restore the processor status. + * + * The @a _isr_cookie must contain the processor status returned by + * _CPU_ISR_Disable(). The value is not modified. + */ +#define _CPU_ISR_Enable( _isr_cookie ) \ + __builtin_wrctl( 0, (int) _isr_cookie ) + +/** + * @brief Macro to restore the processor status and disable the interrupts + * again. + * + * The @a _isr_cookie must contain the processor status returned by + * _CPU_ISR_Disable(). The value is not modified. + * + * This flash code is optimal for all Nios II configurations. The rdctl does + * not flush the pipeline and has only a late result penalty. The wrctl on + * the other hand leads to a pipeline flush. + */ +#define _CPU_ISR_Flash( _isr_cookie ) \ + do { \ + int _status = __builtin_rdctl( 0 ); \ + __builtin_wrctl( 0, (int) _isr_cookie ); \ + __builtin_wrctl( 0, _status ); \ + } while ( 0 ) + +bool _CPU_ISR_Is_enabled( uint32_t level ); + +/** + * @brief Sets the interrupt level for the executing thread. + * + * The valid values of @a new_level depend on the Nios II configuration. A + * value of zero represents enabled interrupts in all configurations. + * + * @see _CPU_ISR_Get_level() + */ +void _CPU_ISR_Set_level( uint32_t new_level ); + +/** + * @brief Returns the interrupt level of the executing thread. + * + * @retval 0 Interrupts are enabled. + * @retval otherwise The value depends on the Nios II configuration. In case + * of an internal interrupt controller (IIC) the only valid value is one which + * indicates disabled interrupts. In case of an external interrupt controller + * (EIC) there are two possibilities. Firstly if the RSIE status bit is used + * to disable interrupts, then one is the only valid value indicating disabled + * interrupts. Secondly if the IL status field is used to disable interrupts, + * then this value will be returned. Interrupts are disabled at the maximum + * level specified by the _Nios2_ISR_Status_bits. + */ +uint32_t _CPU_ISR_Get_level( void ); + +/** + * @brief Initializes the CPU context. + * + * The following steps are performed: + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * + * @param[in] context points to the context area + * @param[in] stack_area_begin is the low address of the allocated stack area + * @param[in] stack_area_size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to @c true if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + */ +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +void _CPU_Fatal_halt( uint32_t _source, uint32_t _error ) + RTEMS_NO_RETURN; + +/** + * @brief CPU initialization. + */ +void _CPU_Initialize( void ); + +/** + * @brief CPU ISR install raw handler. + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @brief CPU ISR install vector. + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +static inline uint32_t CPU_swap_u32( uint32_t value ) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + + return swapped; +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..81a19c8d69 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief Altera Nios II Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h b/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h new file mode 100644 index 0000000000..bf2390a51f --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/nios2-count-zeros.h @@ -0,0 +1,70 @@ +/* + * Author: Jeffrey O. Hill + * + * Copyright 2012. Los Alamos National Security, LLC. + * This material was produced under U.S. Government contract + * DE-AC52-06NA25396 for Los Alamos National Laboratory (LANL), + * which is operated by Los Alamos National Security, LLC for + * the U.S. Department of Energy. The U.S. Government has rights + * to use, reproduce, and distribute this software. NEITHER THE + * GOVERNMENT NOR LOS ALAMOS NATIONAL SECURITY, LLC MAKES ANY + * WARRANTY, EXPRESS OR IMPLIED, OR ASSUMES ANY LIABILITY FOR + * THE USE OF THIS SOFTWARE. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _NIOS2_COUNT_ZEROS_H +#define _NIOS2_COUNT_ZEROS_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * This implementation is currently much more efficient than + * the GCC provided __builtin_clz + */ +static inline unsigned _Nios2_Count_leading_zeros( uint32_t p ) +{ + unsigned bitIdx; + + if ( p <= 0xffffu ) { + if ( p < 0x100u ) { + bitIdx = _Bitfield_Leading_zeros[ p ] + 24u; + } else { + bitIdx = _Bitfield_Leading_zeros[ p >> 8u ] + 16u; + } + } else { + p >>= 16u; + + if ( p < 0x100u ) { + bitIdx = _Bitfield_Leading_zeros[ p ] + 8u; + } else { + bitIdx = _Bitfield_Leading_zeros[ p >> 8u ]; + } + } + + return bitIdx; +} + +/* + * This implementation is currently much more efficient than + * the GCC provided __builtin_ctz + */ +static inline unsigned _Nios2_Count_trailing_zeros( uint32_t p ) +{ + return 31u - _Nios2_Count_leading_zeros( p & ( -p ) ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _NIOS2_COUNT_ZEROS_H */ diff --git a/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h b/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h new file mode 100644 index 0000000000..d5eb4b3597 --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h @@ -0,0 +1,516 @@ +/** + * @file + * + * @brief NIOS II Utility + */ +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_NIOS2_UTILITY_H +#define _RTEMS_SCORE_NIOS2_UTILITY_H + +#define NIOS2_CTLREG_INDEX_STATUS 0 +#define NIOS2_CTLREG_INDEX_ESTATUS 1 +#define NIOS2_CTLREG_INDEX_BSTATUS 2 +#define NIOS2_CTLREG_INDEX_IENABLE 3 +#define NIOS2_CTLREG_INDEX_IPENDING 4 +#define NIOS2_CTLREG_INDEX_CPUID 5 +#define NIOS2_CTLREG_INDEX_EXCEPTION 7 +#define NIOS2_CTLREG_INDEX_PTEADDR 8 +#define NIOS2_CTLREG_INDEX_TLBACC 9 +#define NIOS2_CTLREG_INDEX_TLBMISC 10 +#define NIOS2_CTLREG_INDEX_BADADDR 12 +#define NIOS2_CTLREG_INDEX_CONFIG 13 +#define NIOS2_CTLREG_INDEX_MPUBASE 14 +#define NIOS2_CTLREG_INDEX_MPUACC 15 + +#define NIOS2_CONTEXT_OFFSET_R16 0 +#define NIOS2_CONTEXT_OFFSET_R17 4 +#define NIOS2_CONTEXT_OFFSET_R18 8 +#define NIOS2_CONTEXT_OFFSET_R19 12 +#define NIOS2_CONTEXT_OFFSET_R20 16 +#define NIOS2_CONTEXT_OFFSET_R21 20 +#define NIOS2_CONTEXT_OFFSET_R22 24 +#define NIOS2_CONTEXT_OFFSET_R23 28 +#define NIOS2_CONTEXT_OFFSET_FP 32 +#define NIOS2_CONTEXT_OFFSET_STATUS 36 +#define NIOS2_CONTEXT_OFFSET_SP 40 +#define NIOS2_CONTEXT_OFFSET_RA 44 +#define NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED 48 +#define NIOS2_CONTEXT_OFFSET_STACK_MPUBASE 52 +#define NIOS2_CONTEXT_OFFSET_STACK_MPUACC 56 + +#define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe +#define NIOS2_ISR_STATUS_BITS_IIC 0x00000000 + +#define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f +#define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0 + +#define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff +#define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000 + +#define NIOS2_STATUS_RSIE (1 << 23) +#define NIOS2_STATUS_NMI (1 << 22) +#define NIOS2_STATUS_PRS_OFFSET 16 +#define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET) +#define NIOS2_STATUS_CRS_OFFSET 10 +#define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET) +#define NIOS2_STATUS_IL_OFFSET 4 +#define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET) +#define NIOS2_STATUS_IH (1 << 3) +#define NIOS2_STATUS_EH (1 << 2) +#define NIOS2_STATUS_U (1 << 1) +#define NIOS2_STATUS_PIE (1 << 0) + +#define NIOS2_EXCEPTION_CAUSE_OFFSET 2 +#define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET) + +#define NIOS2_PTEADDR_PTBASE_OFFSET 22 +#define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET) +#define NIOS2_PTEADDR_VPN_OFFSET 2 +#define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET) + +#define NIOS2_TLBACC_IG_OFFSET 25 +#define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET) +#define NIOS2_TLBACC_C (1 << 24) +#define NIOS2_TLBACC_R (1 << 23) +#define NIOS2_TLBACC_W (1 << 22) +#define NIOS2_TLBACC_X (1 << 21) +#define NIOS2_TLBACC_G (1 << 20) +#define NIOS2_TLBACC_PFN_OFFSET 2 +#define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET) + +#define NIOS2_TLBMISC_WAY_OFFSET 20 +#define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET) +#define NIOS2_TLBMISC_RD (1 << 19) +#define NIOS2_TLBMISC_WE (1 << 18) +#define NIOS2_TLBMISC_PID_OFFSET 5 +#define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET) +#define NIOS2_TLBMISC_DBL (1 << 3) +#define NIOS2_TLBMISC_BAD (1 << 2) +#define NIOS2_TLBMISC_PERM (1 << 1) +#define NIOS2_TLBMISC_D (1 << 0) + +#define NIOS2_CONFIG_ANI (1 << 1) +#define NIOS2_CONFIG_PE (1 << 0) + +#define NIOS2_MPUBASE_BASE_OFFSET 6 +#define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET) +#define NIOS2_MPUBASE_INDEX_OFFSET 1 + +/* Avoid redefines with Altera HAL */ +#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) + +#define NIOS2_MPUBASE_D (1 << 0) + +#define NIOS2_MPUACC_MASK_OFFSET 6 + +/* Avoid redefines with Altera HAL */ +#define NIOS2_MPUACC_MASK_MASK (0x7fffffc0) + +#define NIOS2_MPUACC_LIMIT_OFFSET 6 + +/* Avoid redefines with Altera HAL */ +#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) + +#define NIOS2_MPUACC_C (1 << 5) +#define NIOS2_MPUACC_PERM_OFFSET 2 + +/* Avoid redefines with Altera HAL */ +#define NIOS2_MPUACC_PERM_MASK (0x0000001c) + +#define NIOS2_MPUACC_RD (1 << 1) +#define NIOS2_MPUACC_WR (1 << 0) + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Nios II specific thread dispatch disabled indicator. + * + * This global variable is used by the interrupt dispatch support for the + * external interrupt controller (EIC) with shadow registers. This makes it + * possible to do the thread dispatch after an interrupt without disabled + * interrupts and thus probably reduce the maximum interrupt latency. Its + * purpose is to prevent unbounded stack usage of the interrupted thread. + */ +extern uint32_t _Nios2_Thread_dispatch_disabled; + +/** + * @brief This global symbol specifies the status register mask used to disable + * interrupts. + * + * The board support package must provide a global symbol with this name to + * specify the status register mask used in _CPU_ISR_Disable(). + */ +extern char _Nios2_ISR_Status_mask []; + +/** + * @brief This symbol specifies the status register bits used to disable + * interrupts. + * + * The board support package must provide a global symbol with this name to + * specify the status register bits used in _CPU_ISR_Disable(). + */ +extern char _Nios2_ISR_Status_bits []; + +static inline void _Nios2_Flush_pipeline( void ) +{ + __asm__ volatile ("flushp"); +} + +static inline uint32_t _Nios2_Get_ctlreg_status( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS ); +} + +static inline void _Nios2_Set_ctlreg_status( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_estatus( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS ); +} + +static inline void _Nios2_Set_ctlreg_estatus( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_bstatus( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS ); +} + +static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_ienable( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE ); +} + +static inline void _Nios2_Set_ctlreg_ienable( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_ipending( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING ); +} + +static inline uint32_t _Nios2_Get_ctlreg_cpuid( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID ); +} + +static inline uint32_t _Nios2_Get_ctlreg_exception( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION ); +} + +static inline uint32_t _Nios2_Get_ctlreg_pteaddr( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR ); +} + +static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_tlbacc( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC ); +} + +static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_tlbmisc( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC ); +} + +static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_badaddr( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR ); +} + +static inline uint32_t _Nios2_Get_ctlreg_config( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG ); +} + +static inline void _Nios2_Set_ctlreg_config( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_mpubase( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE ); +} + +static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (int) value ); +} + +static inline uint32_t _Nios2_Get_ctlreg_mpuacc( void ) +{ + return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC ); +} + +static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value ) +{ + __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (int) value ); +} + +static inline uint32_t _Nios2_ISR_Get_status_mask( void ) +{ + return (uint32_t) &_Nios2_ISR_Status_mask [0]; +} + +static inline uint32_t _Nios2_ISR_Get_status_bits( void ) +{ + return (uint32_t) &_Nios2_ISR_Status_bits [0]; +} + +static inline bool _Nios2_Has_internal_interrupt_controller( void ) +{ + return _Nios2_ISR_Get_status_mask() == NIOS2_ISR_STATUS_MASK_IIC; +} + +uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status ); + +typedef struct { + int data_address_width; + int instruction_address_width; + int data_region_size_log2; + int instruction_region_size_log2; + int data_region_count; + int instruction_region_count; + int data_index_for_stack_protection; + bool region_uses_limit; + bool enable_data_cache_for_stack; +} Nios2_MPU_Configuration; + +void _Nios2_MPU_Set_configuration( const Nios2_MPU_Configuration *config ); + +const Nios2_MPU_Configuration *_Nios2_MPU_Get_configuration( void ); + +typedef enum { + NIOS2_MPU_INST_PERM_SVR_NONE_USER_NONE = 0, + NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, + NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_EXECUTE, + NIOS2_MPU_DATA_PERM_SVR_NONE_USER_NONE = 0, + NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, + NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_READONLY, + NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE = 4, + NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READONLY, + NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READWRITE +} Nios2_MPU_Region_permissions; + +typedef struct { + int index; + const void *base; + const void *end; + Nios2_MPU_Region_permissions perm; + bool data; + bool cacheable; + bool read; + bool write; +} Nios2_MPU_Region_descriptor; + +#define NIOS2_MPU_REGION_DESC_INST( index, base, end ) \ + { \ + (index), (base), (end), NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, \ + false, false, false, true \ + } + +#define NIOS2_MPU_REGION_DESC_DATA_RO( index, base, end ) \ + { \ + (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, \ + true, true, false, true \ + } + +#define NIOS2_MPU_REGION_DESC_DATA_RW( index, base, end ) \ + { \ + (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ + true, true, false, true \ + } + +#define NIOS2_MPU_REGION_DESC_DATA_IO( index, base, end ) \ + { \ + (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ + true, false, false, true \ + } + +static inline int _Nios2_MPU_Get_region_count( + const Nios2_MPU_Configuration *config, + bool data +) +{ + return data ? + config->data_region_count + : config->instruction_region_count; +} + +static inline bool _Nios2_MPU_Is_valid_index( + const Nios2_MPU_Configuration *config, + int index, + bool data +) +{ + return 0 <= index + && index < _Nios2_MPU_Get_region_count( config, data ); +} + +bool _Nios2_MPU_Setup_region_registers( + const Nios2_MPU_Configuration *config, + const Nios2_MPU_Region_descriptor *desc, + uint32_t *mpubase, + uint32_t *mpuacc +); + +bool _Nios2_MPU_Get_region_descriptor( + const Nios2_MPU_Configuration *config, + int index, + bool data, + Nios2_MPU_Region_descriptor *desc +); + +/** + * @brief Searches the region table part for a disabled region. + * + * The table will be searched between indices @a begin and @a end. The @a end + * index is not part of the search range. If @a end is negative, then the + * region count will be used. Thus a @a begin of 0 and a @a end of -1 will + * specify the complete table. + * + * @retval -1 No disabled region is available. + * @retval other Index of disabled region. + */ +int _Nios2_MPU_Get_disabled_region_index( + const Nios2_MPU_Configuration *config, + bool data, + int begin, + int end +); + +/** + * @brief Adds a region according to region descriptor @a desc. + * + * If @a force is true, then an enabled region will be overwritten. + * + * @retval true Successful operation. + * @retval false Invalid region descriptor or region already in use. + */ +bool _Nios2_MPU_Add_region( + const Nios2_MPU_Configuration *config, + const Nios2_MPU_Region_descriptor *desc, + bool force +); + +static inline void _Nios2_MPU_Get_region_registers( + int index, + bool data, + uint32_t *mpubase, + uint32_t *mpuacc +) +{ + uint32_t base = (uint32_t) + (((index << NIOS2_MPUBASE_INDEX_OFFSET) & NIOS2_MPUBASE_INDEX_MASK) + | (data ? NIOS2_MPUBASE_D : 0)); + + _Nios2_Set_ctlreg_mpubase( base ); + _Nios2_Set_ctlreg_mpuacc( NIOS2_MPUACC_RD ); + _Nios2_Flush_pipeline(); + *mpubase = _Nios2_Get_ctlreg_mpubase() | base; + *mpuacc = _Nios2_Get_ctlreg_mpuacc(); +} + +static inline void _Nios2_MPU_Set_region_registers( + uint32_t mpubase, + uint32_t mpuacc +) +{ + _Nios2_Set_ctlreg_mpubase( mpubase ); + _Nios2_Set_ctlreg_mpuacc( mpuacc ); + _Nios2_Flush_pipeline(); +} + +static inline void _Nios2_MPU_Enable( void ) +{ + uint32_t config = _Nios2_Get_ctlreg_config(); + + _Nios2_Set_ctlreg_config( config | NIOS2_CONFIG_PE ); +} + +static inline uint32_t _Nios2_MPU_Disable( void ) +{ + uint32_t config = _Nios2_Get_ctlreg_config(); + uint32_t config_pe = NIOS2_CONFIG_PE; + + _Nios2_Set_ctlreg_config( config & ~config_pe ); + + return config; +} + +static inline void _Nios2_MPU_Restore( uint32_t config ) +{ + _Nios2_Set_ctlreg_config( config ); +} + +uint32_t _Nios2_MPU_Disable_protected( void ); + +void _Nios2_MPU_Reset( const Nios2_MPU_Configuration *config ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#else /* ASM */ + + .macro NIOS2_ASM_DISABLE_INTERRUPTS new_status, current_status + movhi \new_status, %hiadj(_Nios2_ISR_Status_mask) + addi \new_status, \new_status, %lo(_Nios2_ISR_Status_mask) + and \new_status, \current_status, \new_status + ori \new_status, \new_status, %lo(_Nios2_ISR_Status_bits) + wrctl status, \new_status + .endm + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_NIOS2_UTILITY_H */ diff --git a/cpukit/score/cpu/nios2/include/rtems/score/nios2.h b/cpukit/score/cpu/nios2/include/rtems/score/nios2.h new file mode 100644 index 0000000000..26d76bcbfa --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/nios2.h @@ -0,0 +1,65 @@ +/** + * @file + * + * @brief NIOS II Set up Basic CPU Dependency Settings Based on + * Compiler Settings + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specific to the NIOS2 port. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_NIOS2_H +#define _RTEMS_SCORE_NIOS2_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the NIOS2 family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +/* + * Define the name of the CPU family and specific model. + */ + +#define CPU_NAME "NIOS2" +#define CPU_MODEL_NAME "nios2" + +/* + * See also nios2-rtems-gcc -print-multi-lib for all valid combinations of + * + * -mno-hw-mul + * -mhw-mulx + * -mstack-check + * -pg + * -EB + * -mcustom-fpu-cfg=60-1 + * -mcustom-fpu-cfg=60-2 + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_NIOS2_H */ diff --git a/cpukit/score/cpu/nios2/include/rtems/score/types.h b/cpukit/score/cpu/nios2/include/rtems/score/types.h new file mode 100644 index 0000000000..23cf39419b --- /dev/null +++ b/cpukit/score/cpu/nios2/include/rtems/score/types.h @@ -0,0 +1,46 @@ +/** + * @file + * + * @brief Altera Nios II CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * Altera Nios II processor family. + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void nios2_isr; +typedef void ( *nios2_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/nios2/preinstall.am b/cpukit/score/cpu/nios2/preinstall.am deleted file mode 100644 index fa07df865d..0000000000 --- a/cpukit/score/cpu/nios2/preinstall.am +++ /dev/null @@ -1,61 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/nios2.h: rtems/score/nios2.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2.h - -$(PROJECT_INCLUDE)/rtems/score/nios2-utility.h: rtems/score/nios2-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2-utility.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2-utility.h - -$(PROJECT_INCLUDE)/rtems/score/nios2-count-zeros.h: rtems/score/nios2-count-zeros.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2-count-zeros.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2-count-zeros.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/nios2/rtems/asm.h b/cpukit/score/cpu/nios2/rtems/asm.h deleted file mode 100644 index 45ccd8b050..0000000000 --- a/cpukit/score/cpu/nios2/rtems/asm.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h deleted file mode 100644 index a3f2f03d36..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ /dev/null @@ -1,372 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II CPU Department Source - */ - -/* - * Copyright (c) 2011 embedded brains GmbH - * - * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) - * - * COPYRIGHT (c) 1989-2004. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_CONTEXT_FP_SIZE 0 - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT \ - RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -#define CPU_STACK_MINIMUM_SIZE (4 * 1024) - -#define CPU_SIZEOF_POINTER 4 - -/* - * Alignment value according to "Nios II Processor Reference" chapter 7 - * "Application Binary Interface" section "Memory Alignment". - */ -#define CPU_ALIGNMENT 4 - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * Alignment value according to "Nios II Processor Reference" chapter 7 - * "Application Binary Interface" section "Stacks". - */ -#define CPU_STACK_ALIGNMENT 4 - -/* - * A Nios II configuration with an external interrupt controller (EIC) supports - * up to 64 interrupt levels. A Nios II configuration with an internal - * interrupt controller (IIC) has only two interrupt levels (enabled and - * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will - * take care about configuration specific mappings. - */ -#define CPU_MODES_INTERRUPT_MASK 0x3f - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -#define CPU_MAXIMUM_PROCESSORS 32 - -#ifndef ASM - -/** - * @brief Thread register context. - * - * The thread register context covers the non-volatile registers, the thread - * stack pointer, the return address, and the processor status. - * - * There is no need to save the global pointer (gp) since it is a system wide - * constant and set-up with the C runtime environment. - * - * The @a thread_dispatch_disabled field is used for the external interrupt - * controller (EIC) support. - * - * @see _Nios2_Thread_dispatch_disabled - */ -typedef struct { - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t fp; - uint32_t status; - uint32_t sp; - uint32_t ra; - uint32_t thread_dispatch_disabled; - uint32_t stack_mpubase; - uint32_t stack_mpuacc; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef void CPU_Interrupt_frame; - -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t et; - uint32_t ea; - uint32_t status; - uint32_t ienable; - uint32_t ipending; -} CPU_Exception_frame; - -#define _CPU_Initialize_vectors() - -/** - * @brief Macro to disable interrupts. - * - * The processor status before disabling the interrupts will be stored in - * @a _isr_cookie. This value will be used in _CPU_ISR_Flash() and - * _CPU_ISR_Enable(). - * - * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in - * the status register representing the interrupt level. The global symbol - * _Nios2_ISR_Status_bits will be used to set the bits representing an - * interrupt level that disables interrupts. Both global symbols must be - * provided by the board support package. - * - * In case the Nios II uses the internal interrupt controller (IIC), then only - * the PIE status bit is used. - * - * In case the Nios II uses the external interrupt controller (EIC), then the - * RSIE status bit or the IL status field is used depending on the interrupt - * handling variant and the shadow register usage. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - int _tmp; \ - __asm__ volatile ( \ - "rdctl %0, status\n" \ - "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ - "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ - "and %1, %0, %1\n" \ - "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ - "wrctl status, %1" \ - : "=&r" (_isr_cookie), "=&r" (_tmp) \ - ); \ - } while ( 0 ) - -/** - * @brief Macro to restore the processor status. - * - * The @a _isr_cookie must contain the processor status returned by - * _CPU_ISR_Disable(). The value is not modified. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - __builtin_wrctl( 0, (int) _isr_cookie ) - -/** - * @brief Macro to restore the processor status and disable the interrupts - * again. - * - * The @a _isr_cookie must contain the processor status returned by - * _CPU_ISR_Disable(). The value is not modified. - * - * This flash code is optimal for all Nios II configurations. The rdctl does - * not flush the pipeline and has only a late result penalty. The wrctl on - * the other hand leads to a pipeline flush. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - int _status = __builtin_rdctl( 0 ); \ - __builtin_wrctl( 0, (int) _isr_cookie ); \ - __builtin_wrctl( 0, _status ); \ - } while ( 0 ) - -bool _CPU_ISR_Is_enabled( uint32_t level ); - -/** - * @brief Sets the interrupt level for the executing thread. - * - * The valid values of @a new_level depend on the Nios II configuration. A - * value of zero represents enabled interrupts in all configurations. - * - * @see _CPU_ISR_Get_level() - */ -void _CPU_ISR_Set_level( uint32_t new_level ); - -/** - * @brief Returns the interrupt level of the executing thread. - * - * @retval 0 Interrupts are enabled. - * @retval otherwise The value depends on the Nios II configuration. In case - * of an internal interrupt controller (IIC) the only valid value is one which - * indicates disabled interrupts. In case of an external interrupt controller - * (EIC) there are two possibilities. Firstly if the RSIE status bit is used - * to disable interrupts, then one is the only valid value indicating disabled - * interrupts. Secondly if the IL status field is used to disable interrupts, - * then this value will be returned. Interrupts are disabled at the maximum - * level specified by the _Nios2_ISR_Status_bits. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -void _CPU_Fatal_halt( uint32_t _source, uint32_t _error ) - RTEMS_NO_RETURN; - -/** - * @brief CPU initialization. - */ -void _CPU_Initialize( void ); - -/** - * @brief CPU ISR install raw handler. - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief CPU ISR install vector. - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -static inline uint32_t CPU_swap_u32( uint32_t value ) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - - return swapped; -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h deleted file mode 100644 index 81a19c8d69..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/nios2/rtems/score/cpuatomic.h b/cpukit/score/cpu/nios2/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/nios2/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2-count-zeros.h b/cpukit/score/cpu/nios2/rtems/score/nios2-count-zeros.h deleted file mode 100644 index bf2390a51f..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/nios2-count-zeros.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Author: Jeffrey O. Hill - * - * Copyright 2012. Los Alamos National Security, LLC. - * This material was produced under U.S. Government contract - * DE-AC52-06NA25396 for Los Alamos National Laboratory (LANL), - * which is operated by Los Alamos National Security, LLC for - * the U.S. Department of Energy. The U.S. Government has rights - * to use, reproduce, and distribute this software. NEITHER THE - * GOVERNMENT NOR LOS ALAMOS NATIONAL SECURITY, LLC MAKES ANY - * WARRANTY, EXPRESS OR IMPLIED, OR ASSUMES ANY LIABILITY FOR - * THE USE OF THIS SOFTWARE. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _NIOS2_COUNT_ZEROS_H -#define _NIOS2_COUNT_ZEROS_H - -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* - * This implementation is currently much more efficient than - * the GCC provided __builtin_clz - */ -static inline unsigned _Nios2_Count_leading_zeros( uint32_t p ) -{ - unsigned bitIdx; - - if ( p <= 0xffffu ) { - if ( p < 0x100u ) { - bitIdx = _Bitfield_Leading_zeros[ p ] + 24u; - } else { - bitIdx = _Bitfield_Leading_zeros[ p >> 8u ] + 16u; - } - } else { - p >>= 16u; - - if ( p < 0x100u ) { - bitIdx = _Bitfield_Leading_zeros[ p ] + 8u; - } else { - bitIdx = _Bitfield_Leading_zeros[ p >> 8u ]; - } - } - - return bitIdx; -} - -/* - * This implementation is currently much more efficient than - * the GCC provided __builtin_ctz - */ -static inline unsigned _Nios2_Count_trailing_zeros( uint32_t p ) -{ - return 31u - _Nios2_Count_leading_zeros( p & ( -p ) ); -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _NIOS2_COUNT_ZEROS_H */ diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h b/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h deleted file mode 100644 index d5eb4b3597..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h +++ /dev/null @@ -1,516 +0,0 @@ -/** - * @file - * - * @brief NIOS II Utility - */ -/* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_NIOS2_UTILITY_H -#define _RTEMS_SCORE_NIOS2_UTILITY_H - -#define NIOS2_CTLREG_INDEX_STATUS 0 -#define NIOS2_CTLREG_INDEX_ESTATUS 1 -#define NIOS2_CTLREG_INDEX_BSTATUS 2 -#define NIOS2_CTLREG_INDEX_IENABLE 3 -#define NIOS2_CTLREG_INDEX_IPENDING 4 -#define NIOS2_CTLREG_INDEX_CPUID 5 -#define NIOS2_CTLREG_INDEX_EXCEPTION 7 -#define NIOS2_CTLREG_INDEX_PTEADDR 8 -#define NIOS2_CTLREG_INDEX_TLBACC 9 -#define NIOS2_CTLREG_INDEX_TLBMISC 10 -#define NIOS2_CTLREG_INDEX_BADADDR 12 -#define NIOS2_CTLREG_INDEX_CONFIG 13 -#define NIOS2_CTLREG_INDEX_MPUBASE 14 -#define NIOS2_CTLREG_INDEX_MPUACC 15 - -#define NIOS2_CONTEXT_OFFSET_R16 0 -#define NIOS2_CONTEXT_OFFSET_R17 4 -#define NIOS2_CONTEXT_OFFSET_R18 8 -#define NIOS2_CONTEXT_OFFSET_R19 12 -#define NIOS2_CONTEXT_OFFSET_R20 16 -#define NIOS2_CONTEXT_OFFSET_R21 20 -#define NIOS2_CONTEXT_OFFSET_R22 24 -#define NIOS2_CONTEXT_OFFSET_R23 28 -#define NIOS2_CONTEXT_OFFSET_FP 32 -#define NIOS2_CONTEXT_OFFSET_STATUS 36 -#define NIOS2_CONTEXT_OFFSET_SP 40 -#define NIOS2_CONTEXT_OFFSET_RA 44 -#define NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED 48 -#define NIOS2_CONTEXT_OFFSET_STACK_MPUBASE 52 -#define NIOS2_CONTEXT_OFFSET_STACK_MPUACC 56 - -#define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe -#define NIOS2_ISR_STATUS_BITS_IIC 0x00000000 - -#define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f -#define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0 - -#define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff -#define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000 - -#define NIOS2_STATUS_RSIE (1 << 23) -#define NIOS2_STATUS_NMI (1 << 22) -#define NIOS2_STATUS_PRS_OFFSET 16 -#define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET) -#define NIOS2_STATUS_CRS_OFFSET 10 -#define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET) -#define NIOS2_STATUS_IL_OFFSET 4 -#define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET) -#define NIOS2_STATUS_IH (1 << 3) -#define NIOS2_STATUS_EH (1 << 2) -#define NIOS2_STATUS_U (1 << 1) -#define NIOS2_STATUS_PIE (1 << 0) - -#define NIOS2_EXCEPTION_CAUSE_OFFSET 2 -#define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET) - -#define NIOS2_PTEADDR_PTBASE_OFFSET 22 -#define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET) -#define NIOS2_PTEADDR_VPN_OFFSET 2 -#define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET) - -#define NIOS2_TLBACC_IG_OFFSET 25 -#define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET) -#define NIOS2_TLBACC_C (1 << 24) -#define NIOS2_TLBACC_R (1 << 23) -#define NIOS2_TLBACC_W (1 << 22) -#define NIOS2_TLBACC_X (1 << 21) -#define NIOS2_TLBACC_G (1 << 20) -#define NIOS2_TLBACC_PFN_OFFSET 2 -#define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET) - -#define NIOS2_TLBMISC_WAY_OFFSET 20 -#define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET) -#define NIOS2_TLBMISC_RD (1 << 19) -#define NIOS2_TLBMISC_WE (1 << 18) -#define NIOS2_TLBMISC_PID_OFFSET 5 -#define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET) -#define NIOS2_TLBMISC_DBL (1 << 3) -#define NIOS2_TLBMISC_BAD (1 << 2) -#define NIOS2_TLBMISC_PERM (1 << 1) -#define NIOS2_TLBMISC_D (1 << 0) - -#define NIOS2_CONFIG_ANI (1 << 1) -#define NIOS2_CONFIG_PE (1 << 0) - -#define NIOS2_MPUBASE_BASE_OFFSET 6 -#define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET) -#define NIOS2_MPUBASE_INDEX_OFFSET 1 - -/* Avoid redefines with Altera HAL */ -#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) - -#define NIOS2_MPUBASE_D (1 << 0) - -#define NIOS2_MPUACC_MASK_OFFSET 6 - -/* Avoid redefines with Altera HAL */ -#define NIOS2_MPUACC_MASK_MASK (0x7fffffc0) - -#define NIOS2_MPUACC_LIMIT_OFFSET 6 - -/* Avoid redefines with Altera HAL */ -#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) - -#define NIOS2_MPUACC_C (1 << 5) -#define NIOS2_MPUACC_PERM_OFFSET 2 - -/* Avoid redefines with Altera HAL */ -#define NIOS2_MPUACC_PERM_MASK (0x0000001c) - -#define NIOS2_MPUACC_RD (1 << 1) -#define NIOS2_MPUACC_WR (1 << 0) - -#ifndef ASM - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Nios II specific thread dispatch disabled indicator. - * - * This global variable is used by the interrupt dispatch support for the - * external interrupt controller (EIC) with shadow registers. This makes it - * possible to do the thread dispatch after an interrupt without disabled - * interrupts and thus probably reduce the maximum interrupt latency. Its - * purpose is to prevent unbounded stack usage of the interrupted thread. - */ -extern uint32_t _Nios2_Thread_dispatch_disabled; - -/** - * @brief This global symbol specifies the status register mask used to disable - * interrupts. - * - * The board support package must provide a global symbol with this name to - * specify the status register mask used in _CPU_ISR_Disable(). - */ -extern char _Nios2_ISR_Status_mask []; - -/** - * @brief This symbol specifies the status register bits used to disable - * interrupts. - * - * The board support package must provide a global symbol with this name to - * specify the status register bits used in _CPU_ISR_Disable(). - */ -extern char _Nios2_ISR_Status_bits []; - -static inline void _Nios2_Flush_pipeline( void ) -{ - __asm__ volatile ("flushp"); -} - -static inline uint32_t _Nios2_Get_ctlreg_status( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS ); -} - -static inline void _Nios2_Set_ctlreg_status( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_estatus( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS ); -} - -static inline void _Nios2_Set_ctlreg_estatus( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_bstatus( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS ); -} - -static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_ienable( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE ); -} - -static inline void _Nios2_Set_ctlreg_ienable( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_ipending( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING ); -} - -static inline uint32_t _Nios2_Get_ctlreg_cpuid( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID ); -} - -static inline uint32_t _Nios2_Get_ctlreg_exception( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION ); -} - -static inline uint32_t _Nios2_Get_ctlreg_pteaddr( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR ); -} - -static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_tlbacc( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC ); -} - -static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_tlbmisc( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC ); -} - -static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_badaddr( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR ); -} - -static inline uint32_t _Nios2_Get_ctlreg_config( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG ); -} - -static inline void _Nios2_Set_ctlreg_config( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_mpubase( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE ); -} - -static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (int) value ); -} - -static inline uint32_t _Nios2_Get_ctlreg_mpuacc( void ) -{ - return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC ); -} - -static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value ) -{ - __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (int) value ); -} - -static inline uint32_t _Nios2_ISR_Get_status_mask( void ) -{ - return (uint32_t) &_Nios2_ISR_Status_mask [0]; -} - -static inline uint32_t _Nios2_ISR_Get_status_bits( void ) -{ - return (uint32_t) &_Nios2_ISR_Status_bits [0]; -} - -static inline bool _Nios2_Has_internal_interrupt_controller( void ) -{ - return _Nios2_ISR_Get_status_mask() == NIOS2_ISR_STATUS_MASK_IIC; -} - -uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status ); - -typedef struct { - int data_address_width; - int instruction_address_width; - int data_region_size_log2; - int instruction_region_size_log2; - int data_region_count; - int instruction_region_count; - int data_index_for_stack_protection; - bool region_uses_limit; - bool enable_data_cache_for_stack; -} Nios2_MPU_Configuration; - -void _Nios2_MPU_Set_configuration( const Nios2_MPU_Configuration *config ); - -const Nios2_MPU_Configuration *_Nios2_MPU_Get_configuration( void ); - -typedef enum { - NIOS2_MPU_INST_PERM_SVR_NONE_USER_NONE = 0, - NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, - NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_EXECUTE, - NIOS2_MPU_DATA_PERM_SVR_NONE_USER_NONE = 0, - NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, - NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_READONLY, - NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE = 4, - NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READONLY, - NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READWRITE -} Nios2_MPU_Region_permissions; - -typedef struct { - int index; - const void *base; - const void *end; - Nios2_MPU_Region_permissions perm; - bool data; - bool cacheable; - bool read; - bool write; -} Nios2_MPU_Region_descriptor; - -#define NIOS2_MPU_REGION_DESC_INST( index, base, end ) \ - { \ - (index), (base), (end), NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, \ - false, false, false, true \ - } - -#define NIOS2_MPU_REGION_DESC_DATA_RO( index, base, end ) \ - { \ - (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, \ - true, true, false, true \ - } - -#define NIOS2_MPU_REGION_DESC_DATA_RW( index, base, end ) \ - { \ - (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ - true, true, false, true \ - } - -#define NIOS2_MPU_REGION_DESC_DATA_IO( index, base, end ) \ - { \ - (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ - true, false, false, true \ - } - -static inline int _Nios2_MPU_Get_region_count( - const Nios2_MPU_Configuration *config, - bool data -) -{ - return data ? - config->data_region_count - : config->instruction_region_count; -} - -static inline bool _Nios2_MPU_Is_valid_index( - const Nios2_MPU_Configuration *config, - int index, - bool data -) -{ - return 0 <= index - && index < _Nios2_MPU_Get_region_count( config, data ); -} - -bool _Nios2_MPU_Setup_region_registers( - const Nios2_MPU_Configuration *config, - const Nios2_MPU_Region_descriptor *desc, - uint32_t *mpubase, - uint32_t *mpuacc -); - -bool _Nios2_MPU_Get_region_descriptor( - const Nios2_MPU_Configuration *config, - int index, - bool data, - Nios2_MPU_Region_descriptor *desc -); - -/** - * @brief Searches the region table part for a disabled region. - * - * The table will be searched between indices @a begin and @a end. The @a end - * index is not part of the search range. If @a end is negative, then the - * region count will be used. Thus a @a begin of 0 and a @a end of -1 will - * specify the complete table. - * - * @retval -1 No disabled region is available. - * @retval other Index of disabled region. - */ -int _Nios2_MPU_Get_disabled_region_index( - const Nios2_MPU_Configuration *config, - bool data, - int begin, - int end -); - -/** - * @brief Adds a region according to region descriptor @a desc. - * - * If @a force is true, then an enabled region will be overwritten. - * - * @retval true Successful operation. - * @retval false Invalid region descriptor or region already in use. - */ -bool _Nios2_MPU_Add_region( - const Nios2_MPU_Configuration *config, - const Nios2_MPU_Region_descriptor *desc, - bool force -); - -static inline void _Nios2_MPU_Get_region_registers( - int index, - bool data, - uint32_t *mpubase, - uint32_t *mpuacc -) -{ - uint32_t base = (uint32_t) - (((index << NIOS2_MPUBASE_INDEX_OFFSET) & NIOS2_MPUBASE_INDEX_MASK) - | (data ? NIOS2_MPUBASE_D : 0)); - - _Nios2_Set_ctlreg_mpubase( base ); - _Nios2_Set_ctlreg_mpuacc( NIOS2_MPUACC_RD ); - _Nios2_Flush_pipeline(); - *mpubase = _Nios2_Get_ctlreg_mpubase() | base; - *mpuacc = _Nios2_Get_ctlreg_mpuacc(); -} - -static inline void _Nios2_MPU_Set_region_registers( - uint32_t mpubase, - uint32_t mpuacc -) -{ - _Nios2_Set_ctlreg_mpubase( mpubase ); - _Nios2_Set_ctlreg_mpuacc( mpuacc ); - _Nios2_Flush_pipeline(); -} - -static inline void _Nios2_MPU_Enable( void ) -{ - uint32_t config = _Nios2_Get_ctlreg_config(); - - _Nios2_Set_ctlreg_config( config | NIOS2_CONFIG_PE ); -} - -static inline uint32_t _Nios2_MPU_Disable( void ) -{ - uint32_t config = _Nios2_Get_ctlreg_config(); - uint32_t config_pe = NIOS2_CONFIG_PE; - - _Nios2_Set_ctlreg_config( config & ~config_pe ); - - return config; -} - -static inline void _Nios2_MPU_Restore( uint32_t config ) -{ - _Nios2_Set_ctlreg_config( config ); -} - -uint32_t _Nios2_MPU_Disable_protected( void ); - -void _Nios2_MPU_Reset( const Nios2_MPU_Configuration *config ); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#else /* ASM */ - - .macro NIOS2_ASM_DISABLE_INTERRUPTS new_status, current_status - movhi \new_status, %hiadj(_Nios2_ISR_Status_mask) - addi \new_status, \new_status, %lo(_Nios2_ISR_Status_mask) - and \new_status, \current_status, \new_status - ori \new_status, \new_status, %lo(_Nios2_ISR_Status_bits) - wrctl status, \new_status - .endm - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_NIOS2_UTILITY_H */ diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2.h b/cpukit/score/cpu/nios2/rtems/score/nios2.h deleted file mode 100644 index 26d76bcbfa..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/nios2.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * @file - * - * @brief NIOS II Set up Basic CPU Dependency Settings Based on - * Compiler Settings - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specific to the NIOS2 port. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_NIOS2_H -#define _RTEMS_SCORE_NIOS2_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NIOS2 family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -/* - * Define the name of the CPU family and specific model. - */ - -#define CPU_NAME "NIOS2" -#define CPU_MODEL_NAME "nios2" - -/* - * See also nios2-rtems-gcc -print-multi-lib for all valid combinations of - * - * -mno-hw-mul - * -mhw-mulx - * -mstack-check - * -pg - * -EB - * -mcustom-fpu-cfg=60-1 - * -mcustom-fpu-cfg=60-2 - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_NIOS2_H */ diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h deleted file mode 100644 index 23cf39419b..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Altera Nios II processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void nios2_isr; -typedef void ( *nios2_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/no_cpu/Makefile.am b/cpukit/score/cpu/no_cpu/Makefile.am index 3134c01da8..556d3dea34 100644 --- a/cpukit/score/cpu/no_cpu/Makefile.am +++ b/cpukit/score/cpu/no_cpu/Makefile.am @@ -1,19 +1,9 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/no_cpu.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c cpu_asm.c libscorecpu_a_SOURCES += cpucounterread.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/no_cpu/headers.am b/cpukit/score/cpu/no_cpu/headers.am new file mode 100644 index 0000000000..faf934fb1e --- /dev/null +++ b/cpukit/score/cpu/no_cpu/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/no_cpu.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/no_cpu/include/rtems/asm.h b/cpukit/score/cpu/no_cpu/include/rtems/asm.h new file mode 100644 index 0000000000..926e3964e5 --- /dev/null +++ b/cpukit/score/cpu/no_cpu/include/rtems/asm.h @@ -0,0 +1,133 @@ +/** + * @file rtems/asm.h + * + * @brief Addresses Incompatible Flavors Problems + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-2006. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/** + * @defgroup no_cpuAsm Address Incompatible Flavors Problems + * + * @ingroup no_cpu + */ +/**@{*/ + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all register names. + */ +#define __REGISTER_PREFIX__ +#endif + +#include + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** This macro is used to denote the beginning of a data declaration section. */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define EXTERN(sym) .globl SYM (sym) + +/**@}*/ +#endif diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h new file mode 100644 index 0000000000..c16adc7327 --- /dev/null +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h @@ -0,0 +1,1501 @@ +/** + * @file rtems/score/cpu.h + * + * @brief NO_CPU Department Source + * + * This include file contains information pertaining to the NO_CPU + * processor. + */ + +/* + * This include file contains information pertaining to the XXX + * processor. + * + * @note This file is part of a porting template that is intended + * to be used as the starting point when porting RTEMS to a new + * CPU family. The following needs to be done when using this as + * the starting point for a new port: + * + * + Anywhere there is an XXX, it should be replaced + * with information about the CPU family being ported to. + * + * + At the end of each comment section, there is a heading which + * says "Port Specific Information:". When porting to RTEMS, + * add CPU family specific information in this section + */ + +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/** + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +/** + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE + +/** + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/** + * @def CPU_HARDWARE_FP + * + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? + * + * This feature conditional is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if ( NO_CPU_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPUs in which this option has been used are the + * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and + * gcc both implicitly used the floating point registers to perform + * integer multiplies. Similarly, the PowerPC port of gcc has been + * seen to allocate floating point local variables and touch the FPU + * even when the flow through a subroutine (like vfprintf()) might + * not use floating point formats. + * + * If a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALL_TASKS_ARE_FP TRUE + +/** + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/** + * @brief Enables a robust thread dispatch if set to TRUE. + * + * In general, it is an application bug to call blocking operating system + * services with interrupts disabled. In most situations this only increases + * the interrupt latency. However, on SMP configurations or on some CPU port + * like ARM Cortex-M it leads to undefined system behaviour. It order to ease + * the application development, this error condition is checked at run-time in + * case this CPU port option is defined to TRUE. + */ +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine @ref _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * @ref _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_GROWS_UP TRUE + +/** + * The maximum cache line size in bytes. + * + * The actual processor may use no cache or a smaller cache line size. + */ +#define CPU_CACHE_LINE_BYTES 32 + +/** + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/** + * @ingroup CPUInterrupt + * + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/** + * @brief Maximum number of processors of all systems supported by this CPU + * port. + */ +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* may need to put some structures here. */ + +/** + * @defgroup CPUContext Processor Dependent Context Management + * + * From the highest level viewpoint, there are 2 types of context to save. + * + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + * + */ +/**@{**/ + +/** + * @ingroup Management + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ +typedef struct { + /** + * This field is a hint that a port will have a number of integer + * registers that need to be saved at a context switch. + */ + uint32_t some_integer_register; + /** + * This field is a hint that a port will have a number of system + * registers that need to be saved at a context switch. + */ + uint32_t some_system_register; + + /** + * This field is a hint that a port will have a register that + * is the stack pointer. + */ + uint32_t stack_pointer; + +#ifdef RTEMS_SMP + /** + * @brief On SMP configurations the thread context must contain a boolean + * indicator to signal if this context is executing on a processor. + * + * This field must be updated during a context switch. The context switch + * to the heir must wait until the heir context indicates that it is no + * longer executing on a processor. This indicator must be updated using + * an atomic test and set operation to ensure that at most one processor + * uses the heir context at the same time. The context switch must also + * check for a potential new heir thread for this processor in case the + * heir context is not immediately available. Update the executing thread + * for this processor only if necessary to avoid a cache line + * monopolization. + * + * @code + * void _CPU_Context_switch( + * Context_Control *executing_context, + * Context_Control *heir_context + * ) + * { + * save( executing_context ); + * + * executing_context->is_executing = false; + * memory_barrier(); + * + * if ( test_and_set( &heir_context->is_executing ) ) { + * do { + * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); + * Thread_Control *executing = cpu_self->executing; + * Thread_Control *heir = cpu_self->heir; + * + * if ( heir != executing ) { + * cpu_self->executing = heir; + * heir_context = (Context_Control *) + * ((uintptr_t) heir + (uintptr_t) executing_context + * - (uintptr_t) executing) + * } + * } while ( test_and_set( &heir_context->is_executing ) ); + * } + * + * restore( heir_context ); + * } + * @endcode + */ + volatile bool is_executing; +#endif +} Context_Control; + +/** + * @ingroup Management + * + * This macro returns the stack pointer associated with @a _context. + * + * @param[in] _context is the thread context area to access + * + * @return This method returns the stack pointer. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->stack_pointer + +/** + * @ingroup Management + * + * This defines the complete set of floating point registers that must + * be saved during any context switch from one thread to another. + */ +typedef struct { + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +/** + * @ingroup Management + * + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ +typedef struct { + /** + * This field is a hint that a port will have a number of integer + * registers that need to be saved when an interrupt occurs or + * when a context switch occurs at the end of an ISR. + */ + uint32_t special_interrupt_register; +} CPU_Interrupt_frame; + +/** + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * @ref _CPU_Initialize and copied into the task's FP context area during + * @ref _CPU_Context_Initialize. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +extern Context_Control_fp _CPU_Null_fp_context; + +/** @} */ + +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in @ref _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * NOTE: These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* XXX: if needed, put more variables here */ + +/** + * @ingroup CPUContext + * + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/** + * @ingroup CPUInterrupt + * + * This defines the number of entries in the _ISR_Vector_table managed by RTEMS + * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be a + * compile-time constant. + * + * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to + * FALSE. + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +/** + * @ingroup CPUInterrupt + * + * This defines the highest interrupt vector number for this port in case + * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be less than + * CPU_INTERRUPT_NUMBER_OF_VECTORS. It may be not a compile-time constant. + * + * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to + * FALSE. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/** + * @ingroup CPUInterrupt + * + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable @a _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * @ingroup CPUContext + * + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +/** + * Size of a pointer. + * + * This must be an integer literal that can be used by the assembler. This + * value will be used to calculate offsets of structure members. These + * offsets will be used in assembler code. + */ +#define CPU_SIZEOF_POINTER 4 + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. It + * must be a power of two greater than or equal to two. The power of two + * requirement makes it possible to align values easily using simple bit + * operations. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALIGNMENT 8 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. + * + * NOTE: It must be a power of two greater than or equal to two. The + * requirement to be a multiple of two is because the heap uses the + * least significant field of the front and back flags to indicate that + * a block is in use or free. So you do not want any odd length blocks + * really putting length data in that bit. + * + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by @ref CPU_ALIGNMENT. If the + * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be + * set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_ALIGNMENT 0 + +/* + * ISR handler macros + */ + +/** + * @ingroup CPUInterrupt + * + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Initialize_vectors() + +/** + * @ingroup CPUInterrupt + * + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in @a _isr_cookie. + * + * @param[out] _isr_cookie will contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Disable( _isr_cookie ) \ + { \ + (_isr_cookie) = 0; /* do something to prevent warnings */ \ + } + +/** + * @ingroup CPUInterrupt + * + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * @a _isr_cookie is not modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Enable( _isr_cookie ) \ + { \ + } + +/** + * @ingroup CPUInterrupt + * + * This temporarily restores the interrupt to @a _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Flash( _isr_cookie ) \ + { \ + } + +/** + * @brief Returns true if interrupts are enabled in the specified ISR level, + * otherwise returns false. + * + * @param[in] level The ISR level. + * + * @retval true Interrupts are enabled in the ISR level. + * @retval false Otherwise. + */ +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return false; +} + +/** + * @ingroup CPUInterrupt + * + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Set_level( new_level ) \ + { \ + } + +/** + * @ingroup CPUInterrupt + * + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * NOTE: This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/** + * @ingroup CPUContext + * + * @brief Destroys the context of the thread. + * + * It must be implemented as a macro and an implementation is optional. The + * default implementation does nothing. + * + * @param[in] _the_thread The corresponding thread. + * @param[in] _the_context The context to destroy. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Destroy( _the_thread, _the_context ) \ + { \ + } + +/** + * @ingroup CPUContext + * + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * The ISR dispatch disable field of the context must be cleared to zero if it + * is used by the CPU port. Otherwise, a thread restart results in + * unpredictable behaviour. + * + * @param[in] _the_context is the context structure to be initialized + * @param[in] _stack_base is the lowest physical address of this task's stack + * @param[in] _size is the size of this task's stack + * @param[in] _isr is the interrupt disable level + * @param[in] _entry_point is the thread's entry point. This is + * always @a _Thread_Handler + * @param[in] _is_fp is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * @param[in] _tls_area The thread-local storage (TLS) area. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ + _isr, _entry_point, _is_fp, _tls_area ) \ + { \ + } + +/** + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. For many ports, simply adding a label to the restore path + * of @ref _CPU_Context_switch will work. On other ports, it may be + * possibly to load a few arguments and jump to the restore path. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/** + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * @a _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other floating point context save/restore models include: + * -# not doing anything, and + * -# putting a "null FP status word" in the correct place in the FP context. + * + * @param[in] _destination is the floating point context area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Fatal_halt( _source, _error ) \ + { \ + } + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/** + * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation + * + * This set of routines are used to implement fast searches for + * the most important ready task. + * + */ +/**@{**/ + +/** + * This definition is set to TRUE if the port uses the generic bitfield + * manipulation implementation. + */ +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/** + * This routine sets @a _output to the bit number of the first bit + * set in @a _value. @a _value is of CPU dependent type + * @a Priority_bit_map_Word. This type may be either 16 or 32 bits + * wide although only the 16 least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * -# What happens when run on a value of zero? + * -# Bits may be numbered from MSB to LSB or vice-versa. + * -# The numbering may be zero or one based. + * -# The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and + * @ref _CPU_Priority_bits_index. These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by @ref _CPU_Priority_Mask. + * The basic major and minor values calculated by @ref _Priority_Major + * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for @ref _Priority_Get_highest to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * +@verbatim + - a series of 16 bit test instructions + - a "binary search using if's" + - _number = 0 + if _value > 0x00ff + _value >>=8 + _number = 8; + + if _value > 0x0000f + _value >=8 + _number += 4 + + _number += bit_set_table[ _value ] +@endverbatim + + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + * + * @param[in] _value is the value to be scanned + * @param[in] _output is the first bit set + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + (_output) = 0; /* do something to prevent warnings */ \ + } +#endif + +/** @} */ + +/* end of Bitfield handler macros */ + +/** + * This routine builds the mask which corresponds to the bit fields + * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion + * for that routine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) + +#endif + +/** + * @ingroup CPUBitfield + * + * This routine translates the bit numbers returned by + * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + * + * @param[in] _priority is the major or minor number to translate + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +/* end of Priority handler macros */ + +/* functions */ + +/** + * This routine performs CPU dependent initialization. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Initialize(void); + +/** + * @ingroup CPUInterrupt + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the raw ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the RTEMS ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Install_interrupt_stack( void ); + +/** + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/** + * @ingroup CPUContext + * + * This routine switches from the run context to the heir context. + * + * @param[in] run points to the context of the currently executing task + * @param[in] heir points to the context of the heir task + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * @ingroup CPUContext + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. + * + * @param[in] new_context points to the context to be restored. + * + * NOTE: May be unnecessary to reload some registers. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/** + * @ingroup CPUContext + * + * This routine saves the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_restore_fp to restore this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * @ingroup CPUContext + * + * This routine restores the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area to restore + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_save_fp to save this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * @ingroup CPUContext + * + * @brief Clobbers all volatile registers with values derived from the pattern + * parameter. + * + * This function is used only in test sptests/spcontext01. + * + * @param[in] pattern Pattern used to generate distinct register values. + * + * @see _CPU_Context_validate(). + */ +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +/** + * @ingroup CPUContext + * + * @brief Initializes and validates the CPU context with values derived from + * the pattern parameter. + * + * This function will not return if the CPU context remains consistent. In + * case this function returns the CPU port is broken. + * + * This function is used only in test sptests/spcontext01. + * + * @param[in] pattern Pattern used to generate distinct register values. + * + * @see _CPU_Context_volatile_clobber(). + */ +void _CPU_Context_validate( uintptr_t pattern ); + +/** + * @brief The set of registers that specifies the complete processor state. + * + * The CPU exception frame may be available in fatal error conditions like for + * example illegal opcodes, instruction fetch errors, or data access errors. + * + * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and + * rtems_exception_frame_print(). + */ +typedef struct { + uint32_t processor_state_register; + uint32_t integer_registers [1]; + double float_registers [1]; +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @ingroup CPUEndian + * + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +} + +/** + * @ingroup CPUEndian + * + * This routine swaps a 16 bir quantity. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + */ +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +/** + * @brief Unsigned integer type for CPU counter values. + */ +typedef uint32_t CPU_Counter_ticks; + +/** + * @brief Returns the current CPU counter value. + * + * A CPU counter is some free-running counter. It ticks usually with a + * frequency close to the CPU or system bus clock. The board support package + * must ensure that this function works before the RTEMS initialization. + * Otherwise invalid profiling statistics will be gathered. + * + * @return The current CPU counter value. + */ +CPU_Counter_ticks _CPU_Counter_read( void ); + +/** + * @brief Returns the difference between the second and first CPU counter + * value. + * + * This operation may be carried out as a modulo operation depending on the + * range of the CPU counter device. + * + * @param[in] second The second CPU counter value. + * @param[in] first The first CPU counter value. + * + * @return Returns second minus first modulo counter period. + */ +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +#ifdef RTEMS_SMP + /** + * @brief Performs CPU specific SMP initialization in the context of the boot + * processor. + * + * This function is invoked on the boot processor during system + * initialization. All interrupt stacks are allocated at this point in case + * the CPU port allocates the interrupt stacks. This function is called + * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is + * used. + * + * @return The count of physically or virtually available processors. + * Depending on the configuration the application may use not all processors. + */ + uint32_t _CPU_SMP_Initialize( void ); + + /** + * @brief Starts a processor specified by its index. + * + * This function is invoked on the boot processor during system + * initialization. + * + * This function will be called after _CPU_SMP_Initialize(). + * + * @param[in] cpu_index The processor index. + * + * @retval true Successful operation. + * @retval false Unable to start this processor. + */ + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + /** + * @brief Performs final steps of CPU specific SMP initialization in the + * context of the boot processor. + * + * This function is invoked on the boot processor during system + * initialization. + * + * This function will be called after all processors requested by the + * application have been started. + * + * @param[in] cpu_count The minimum value of the count of processors + * requested by the application configuration and the count of physically or + * virtually available processors. + */ + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + /** + * @brief Prepares a CPU to start multitasking in terms of SMP. + * + * This function is invoked on all processors requested by the application + * during system initialization. + * + * This function will be called after all processors requested by the + * application have been started right before the context switch to the first + * thread takes place. + */ + void _CPU_SMP_Prepare_start_multitasking( void ); + + /** + * @brief Returns the index of the current processor. + * + * An architecture specific method must be used to obtain the index of the + * current processor in the system. The set of processor indices is the + * range of integers starting with zero up to the processor count minus one. + */ + static inline uint32_t _CPU_SMP_Get_current_processor( void ) + { + return 123; + } + + /** + * @brief Sends an inter-processor interrupt to the specified target + * processor. + * + * This operation is undefined for target processor indices out of range. + * + * @param[in] target_processor_index The target processor index. + */ + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + /** + * @brief Broadcasts a processor event. + * + * Some architectures provide a low-level synchronization primitive for + * processors in a multi-processor environment. Processors waiting for this + * event may go into a low-power state and stop generating system bus + * transactions. This function must ensure that preceding store operations + * can be observed by other processors. + * + * @see _CPU_SMP_Processor_event_receive(). + */ + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + /** + * @brief Receives a processor event. + * + * This function will wait for the processor event and may wait forever if no + * such event arrives. + * + * @see _CPU_SMP_Processor_event_broadcast(). + */ + static inline void _CPU_SMP_Processor_event_receive( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + /** + * @brief Gets the is executing indicator of the thread context. + * + * @param[in] context The context. + */ + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + { + return context->is_executing; + } + + /** + * @brief Sets the is executing indicator of the thread context. + * + * @param[in] context The context. + * @param[in] is_executing The new value for the is executing indicator. + */ + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + context->is_executing = is_executing; + } +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..747fd3a1c1 --- /dev/null +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief No-CPU Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +#include + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..85214d7f6c --- /dev/null +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h @@ -0,0 +1,82 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013, 2016 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +/** + * @brief The size of the CPU specific per-CPU control. + * + * This define must be visible to assember files since it is used to derive + * structure offsets. + */ +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The CPU specific per-CPU control. + * + * The CPU port can place here all state information that must be available and + * maintained for each processor in the system. This structure must contain at + * least one field for C/C++ compatibility. In GNU C empty structures have a + * size of zero. In C++ structures have a non-zero size. In case + * CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not + * used. + */ +typedef struct { + /* CPU specific per-CPU state */ +} CPU_Per_CPU_control; + +/** + * @brief Special register pointing to the per-CPU control of the current + * processor. + * + * This is optional. Not every CPU port needs this. It is only an optional + * optimization variant. + */ +register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" ); + +/** + * @brief Optional method to obtain the per-CPU control of the current processor. + * + * This is optional. Not every CPU port needs this. It is only an optional + * optimization variant. In case this macro is undefined, the default + * implementation using the current processor index will be used. + */ +#define _CPU_Get_current_per_CPU_control() ( _CPU_Per_CPU_current ) + +/** + * @brief Optional method to get the executing thread. + * + * This is optional. Not every CPU port needs this. It is only an optional + * optimization variant. In case this macro is undefined, the default + * implementation uses the per-CPU information and the current processor index + * to get the executing thread. + */ +#define _CPU_Get_thread_executing() ( _CPU_Per_CPU_current->executing ) + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h new file mode 100644 index 0000000000..d1bbceccc0 --- /dev/null +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/no_cpu.h @@ -0,0 +1,67 @@ +/* no_cpu.h + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specified to the NO CPU port. + * + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_NO_CPU_H +#define _RTEMS_SCORE_NO_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the NO CPU family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +#if defined(rtems_multilib) +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#define CPU_MODEL_NAME "rtems_multilib" +#define NOCPU_HAS_FPU 1 + +#elif defined(no_cpu) + +#define CPU_MODEL_NAME "no_cpu_model" +#define NOCPU_HAS_FPU 1 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "NO CPU" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_NO_CPU_H */ diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/types.h b/cpukit/score/cpu/no_cpu/include/rtems/score/types.h new file mode 100644 index 0000000000..b330c33904 --- /dev/null +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/types.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @brief No-CPU Type Definitions + * + * This include file contains type definitions pertaining to the Intel + * no_cpu processor family. + */ + +/* + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/no_cpu/preinstall.am b/cpukit/score/cpu/no_cpu/preinstall.am deleted file mode 100644 index fa63e6a812..0000000000 --- a/cpukit/score/cpu/no_cpu/preinstall.am +++ /dev/null @@ -1,49 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/no_cpu.h: rtems/score/no_cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/no_cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/no_cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - diff --git a/cpukit/score/cpu/no_cpu/rtems/asm.h b/cpukit/score/cpu/no_cpu/rtems/asm.h deleted file mode 100644 index 926e3964e5..0000000000 --- a/cpukit/score/cpu/no_cpu/rtems/asm.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * @file rtems/asm.h - * - * @brief Addresses Incompatible Flavors Problems - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/** - * @defgroup no_cpuAsm Address Incompatible Flavors Problems - * - * @ingroup no_cpu - */ -/**@{*/ - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h deleted file mode 100644 index c16adc7327..0000000000 --- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h +++ /dev/null @@ -1,1501 +0,0 @@ -/** - * @file rtems/score/cpu.h - * - * @brief NO_CPU Department Source - * - * This include file contains information pertaining to the NO_CPU - * processor. - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( NO_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * @brief Enables a robust thread dispatch if set to TRUE. - * - * In general, it is an application bug to call blocking operating system - * services with interrupts disabled. In most situations this only increases - * the interrupt latency. However, on SMP configurations or on some CPU port - * like ARM Cortex-M it leads to undefined system behaviour. It order to ease - * the application development, this error condition is checked at run-time in - * case this CPU port option is defined to TRUE. - */ -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The maximum cache line size in bytes. - * - * The actual processor may use no cache or a smaller cache line size. - */ -#define CPU_CACHE_LINE_BYTES 32 - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/** - * @ingroup CPUInterrupt - * - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/** - * @brief Maximum number of processors of all systems supported by this CPU - * port. - */ -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - * - */ -/**@{**/ - -/** - * @ingroup Management - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - /** - * This field is a hint that a port will have a number of integer - * registers that need to be saved at a context switch. - */ - uint32_t some_integer_register; - /** - * This field is a hint that a port will have a number of system - * registers that need to be saved at a context switch. - */ - uint32_t some_system_register; - - /** - * This field is a hint that a port will have a register that - * is the stack pointer. - */ - uint32_t stack_pointer; - -#ifdef RTEMS_SMP - /** - * @brief On SMP configurations the thread context must contain a boolean - * indicator to signal if this context is executing on a processor. - * - * This field must be updated during a context switch. The context switch - * to the heir must wait until the heir context indicates that it is no - * longer executing on a processor. This indicator must be updated using - * an atomic test and set operation to ensure that at most one processor - * uses the heir context at the same time. The context switch must also - * check for a potential new heir thread for this processor in case the - * heir context is not immediately available. Update the executing thread - * for this processor only if necessary to avoid a cache line - * monopolization. - * - * @code - * void _CPU_Context_switch( - * Context_Control *executing_context, - * Context_Control *heir_context - * ) - * { - * save( executing_context ); - * - * executing_context->is_executing = false; - * memory_barrier(); - * - * if ( test_and_set( &heir_context->is_executing ) ) { - * do { - * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); - * Thread_Control *executing = cpu_self->executing; - * Thread_Control *heir = cpu_self->heir; - * - * if ( heir != executing ) { - * cpu_self->executing = heir; - * heir_context = (Context_Control *) - * ((uintptr_t) heir + (uintptr_t) executing_context - * - (uintptr_t) executing) - * } - * } while ( test_and_set( &heir_context->is_executing ) ); - * } - * - * restore( heir_context ); - * } - * @endcode - */ - volatile bool is_executing; -#endif -} Context_Control; - -/** - * @ingroup Management - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->stack_pointer - -/** - * @ingroup Management - * - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * @ingroup Management - * - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** - * This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -extern Context_Control_fp _CPU_Null_fp_context; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * - * This defines the number of entries in the _ISR_Vector_table managed by RTEMS - * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be a - * compile-time constant. - * - * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to - * FALSE. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * @ingroup CPUInterrupt - * - * This defines the highest interrupt vector number for this port in case - * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be less than - * CPU_INTERRUPT_NUMBER_OF_VECTORS. It may be not a compile-time constant. - * - * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to - * FALSE. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * @ingroup CPUContext - * - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. It - * must be a power of two greater than or equal to two. The power of two - * requirement makes it possible to align values easily using simple bit - * operations. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: It must be a power of two greater than or equal to two. The - * requirement to be a multiple of two is because the heap uses the - * least significant field of the front and back flags to indicate that - * a block is in use or free. So you do not want any odd length blocks - * really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - (_isr_cookie) = 0; /* do something to prevent warnings */ \ - } - -/** - * @ingroup CPUInterrupt - * - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - } - -/** - * @ingroup CPUInterrupt - * - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - } - -/** - * @brief Returns true if interrupts are enabled in the specified ISR level, - * otherwise returns false. - * - * @param[in] level The ISR level. - * - * @retval true Interrupts are enabled in the ISR level. - * @retval false Otherwise. - */ -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return false; -} - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - } - -/** - * @ingroup CPUInterrupt - * - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * - * @brief Destroys the context of the thread. - * - * It must be implemented as a macro and an implementation is optional. The - * default implementation does nothing. - * - * @param[in] _the_thread The corresponding thread. - * @param[in] _the_context The context to destroy. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Destroy( _the_thread, _the_context ) \ - { \ - } - -/** - * @ingroup CPUContext - * - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * The ISR dispatch disable field of the context must be cleared to zero if it - * is used by the CPU port. Otherwise, a thread restart results in - * unpredictable behaviour. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] _tls_area The thread-local storage (TLS) area. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - { \ - } - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - * - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/** @} */ - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * @ingroup CPUContext - * - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUContext - * - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUContext - * - * @brief Clobbers all volatile registers with values derived from the pattern - * parameter. - * - * This function is used only in test sptests/spcontext01. - * - * @param[in] pattern Pattern used to generate distinct register values. - * - * @see _CPU_Context_validate(). - */ -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -/** - * @ingroup CPUContext - * - * @brief Initializes and validates the CPU context with values derived from - * the pattern parameter. - * - * This function will not return if the CPU context remains consistent. In - * case this function returns the CPU port is broken. - * - * This function is used only in test sptests/spcontext01. - * - * @param[in] pattern Pattern used to generate distinct register values. - * - * @see _CPU_Context_volatile_clobber(). - */ -void _CPU_Context_validate( uintptr_t pattern ); - -/** - * @brief The set of registers that specifies the complete processor state. - * - * The CPU exception frame may be available in fatal error conditions like for - * example illegal opcodes, instruction fetch errors, or data access errors. - * - * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and - * rtems_exception_frame_print(). - */ -typedef struct { - uint32_t processor_state_register; - uint32_t integer_registers [1]; - double float_registers [1]; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -/** - * @brief Unsigned integer type for CPU counter values. - */ -typedef uint32_t CPU_Counter_ticks; - -/** - * @brief Returns the current CPU counter value. - * - * A CPU counter is some free-running counter. It ticks usually with a - * frequency close to the CPU or system bus clock. The board support package - * must ensure that this function works before the RTEMS initialization. - * Otherwise invalid profiling statistics will be gathered. - * - * @return The current CPU counter value. - */ -CPU_Counter_ticks _CPU_Counter_read( void ); - -/** - * @brief Returns the difference between the second and first CPU counter - * value. - * - * This operation may be carried out as a modulo operation depending on the - * range of the CPU counter device. - * - * @param[in] second The second CPU counter value. - * @param[in] first The first CPU counter value. - * - * @return Returns second minus first modulo counter period. - */ -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#ifdef RTEMS_SMP - /** - * @brief Performs CPU specific SMP initialization in the context of the boot - * processor. - * - * This function is invoked on the boot processor during system - * initialization. All interrupt stacks are allocated at this point in case - * the CPU port allocates the interrupt stacks. This function is called - * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is - * used. - * - * @return The count of physically or virtually available processors. - * Depending on the configuration the application may use not all processors. - */ - uint32_t _CPU_SMP_Initialize( void ); - - /** - * @brief Starts a processor specified by its index. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after _CPU_SMP_Initialize(). - * - * @param[in] cpu_index The processor index. - * - * @retval true Successful operation. - * @retval false Unable to start this processor. - */ - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - /** - * @brief Performs final steps of CPU specific SMP initialization in the - * context of the boot processor. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after all processors requested by the - * application have been started. - * - * @param[in] cpu_count The minimum value of the count of processors - * requested by the application configuration and the count of physically or - * virtually available processors. - */ - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - /** - * @brief Prepares a CPU to start multitasking in terms of SMP. - * - * This function is invoked on all processors requested by the application - * during system initialization. - * - * This function will be called after all processors requested by the - * application have been started right before the context switch to the first - * thread takes place. - */ - void _CPU_SMP_Prepare_start_multitasking( void ); - - /** - * @brief Returns the index of the current processor. - * - * An architecture specific method must be used to obtain the index of the - * current processor in the system. The set of processor indices is the - * range of integers starting with zero up to the processor count minus one. - */ - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - return 123; - } - - /** - * @brief Sends an inter-processor interrupt to the specified target - * processor. - * - * This operation is undefined for target processor indices out of range. - * - * @param[in] target_processor_index The target processor index. - */ - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - /** - * @brief Broadcasts a processor event. - * - * Some architectures provide a low-level synchronization primitive for - * processors in a multi-processor environment. Processors waiting for this - * event may go into a low-power state and stop generating system bus - * transactions. This function must ensure that preceding store operations - * can be observed by other processors. - * - * @see _CPU_SMP_Processor_event_receive(). - */ - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - /** - * @brief Receives a processor event. - * - * This function will wait for the processor event and may wait forever if no - * such event arrives. - * - * @see _CPU_SMP_Processor_event_broadcast(). - */ - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - /** - * @brief Gets the is executing indicator of the thread context. - * - * @param[in] context The context. - */ - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - /** - * @brief Sets the is executing indicator of the thread context. - * - * @param[in] context The context. - * @param[in] is_executing The new value for the is executing indicator. - */ - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h deleted file mode 100644 index 747fd3a1c1..0000000000 --- a/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief No-CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/rtems/score/cpuimpl.h deleted file mode 100644 index 85214d7f6c..0000000000 --- a/cpukit/score/cpu/no_cpu/rtems/score/cpuimpl.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013, 2016 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -/** - * @brief The size of the CPU specific per-CPU control. - * - * This define must be visible to assember files since it is used to derive - * structure offsets. - */ -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief The CPU specific per-CPU control. - * - * The CPU port can place here all state information that must be available and - * maintained for each processor in the system. This structure must contain at - * least one field for C/C++ compatibility. In GNU C empty structures have a - * size of zero. In C++ structures have a non-zero size. In case - * CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not - * used. - */ -typedef struct { - /* CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @brief Special register pointing to the per-CPU control of the current - * processor. - * - * This is optional. Not every CPU port needs this. It is only an optional - * optimization variant. - */ -register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" ); - -/** - * @brief Optional method to obtain the per-CPU control of the current processor. - * - * This is optional. Not every CPU port needs this. It is only an optional - * optimization variant. In case this macro is undefined, the default - * implementation using the current processor index will be used. - */ -#define _CPU_Get_current_per_CPU_control() ( _CPU_Per_CPU_current ) - -/** - * @brief Optional method to get the executing thread. - * - * This is optional. Not every CPU port needs this. It is only an optional - * optimization variant. In case this macro is undefined, the default - * implementation uses the per-CPU information and the current processor index - * to get the executing thread. - */ -#define _CPU_Get_thread_executing() ( _CPU_Per_CPU_current->executing ) - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h deleted file mode 100644 index d1bbceccc0..0000000000 --- a/cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h +++ /dev/null @@ -1,67 +0,0 @@ -/* no_cpu.h - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the NO CPU port. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_NO_CPU_H -#define _RTEMS_SCORE_NO_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define NOCPU_HAS_FPU 1 - -#elif defined(no_cpu) - -#define CPU_MODEL_NAME "no_cpu_model" -#define NOCPU_HAS_FPU 1 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "NO CPU" - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_NO_CPU_H */ diff --git a/cpukit/score/cpu/no_cpu/rtems/score/types.h b/cpukit/score/cpu/no_cpu/rtems/score/types.h deleted file mode 100644 index b330c33904..0000000000 --- a/cpukit/score/cpu/no_cpu/rtems/score/types.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * - * @brief No-CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * no_cpu processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/or1k/Makefile.am b/cpukit/score/cpu/or1k/Makefile.am index c9f28595f8..e4c5b7cdd2 100644 --- a/cpukit/score/cpu/or1k/Makefile.am +++ b/cpukit/score/cpu/or1k/Makefile.am @@ -3,21 +3,6 @@ include $(top_srcdir)/automake/compile.am CLEANFILES = DISTCLEANFILES = -include_rtemsdir = $(includedir)/rtems - -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score - -include_rtems_score_HEADERS = -include_rtems_score_HEADERS += rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/or1k.h -include_rtems_score_HEADERS += rtems/score/or1k-utility.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = @@ -34,5 +19,5 @@ libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) all-local: $(PREINSTALL_FILES) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/or1k/headers.am b/cpukit/score/cpu/or1k/headers.am new file mode 100644 index 0000000000..1ddc654793 --- /dev/null +++ b/cpukit/score/cpu/or1k/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/or1k-utility.h +include_rtems_score_HEADERS += include/rtems/score/or1k.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/or1k/include/rtems/asm.h b/cpukit/score/cpu/or1k/include/rtems/asm.h new file mode 100644 index 0000000000..4d2c22698b --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/asm.h @@ -0,0 +1,99 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + * + */ + +#ifndef __OR1K_ASM_h +#define __OR1K_ASM_h + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .global SYM (sym) + +#endif diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h new file mode 100644 index 0000000000..6daca10f9c --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h @@ -0,0 +1,872 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains macros pertaining to the Opencores + * or1k processor family. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * This file adapted from no_cpu example of the RTEMS distribution. + * The body has been modified for the Opencores OR1k implementation by + * Chris Ziomkowski. + * + */ + +#ifndef _OR1K_CPU_H +#define _OR1K_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include /* pick up machine definitions */ +#include +#include +#ifndef ASM +#include +#include +#include /* for printk */ +#endif + +/* conditional compilation parameters */ + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Currently, for or1k port, _ISR_Handler is responsible for switching to + * RTEMS dedicated interrupt task. + * + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE + * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + */ + +#define CPU_ISR_PASSES_FRAME_POINTER TRUE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "OR1K_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + * + * The CPU_SOFTWARE_FP is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Or1k Specific Information: + * + * At this time there are no implementations of Or1k that are + * expected to implement floating point. More importantly, the + * floating point architecture is expected to change significantly + * before such chips are fabricated. + */ + +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + * + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/* + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * Or1k Specific Information: + * + * This version of RTEMS is designed specifically to run with + * big endian architectures. If you want little endian, you'll + * have to make the appropriate adjustments here and write + * efficient routines for byte swapping. The Or1k architecture + * doesn't do this very well. + */ + +#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + */ + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/* + * Processor defined structures required for cpukit/score. + */ + + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * + */ +#ifndef ASM +#ifdef OR1K_64BIT_ARCH +#define or1kreg uint64_t +#else +#define or1kreg uint32_t +#endif + +typedef struct { + uint32_t r1; /* Stack pointer */ + uint32_t r2; /* Frame pointer */ + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t r26; + uint32_t r27; + uint32_t r28; + uint32_t r29; + uint32_t r30; + uint32_t r31; + + uint32_t sr; /* Current supervision register non persistent values */ + uint32_t epcr; + uint32_t eear; + uint32_t esr; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r1 + +typedef struct { + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +typedef Context_Control CPU_Interrupt_frame; + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Or1k Specific Information: + * + */ + +#define CPU_CONTEXT_FP_SIZE 0 + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * Should be large enough to run all RTEMS tests. This insures + * that a "reasonable" small application should not have any problems. + * + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + */ + +#define CPU_ALIGNMENT 8 + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * Size of a pointer. + * + * This must be an integer literal that can be used by the assembler. This + * value will be used to calculate offsets of structure members. These + * offsets will be used in assembler code. + */ +#define CPU_SIZEOF_POINTER 4 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + * + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + */ + +#define CPU_STACK_ALIGNMENT 0 + +/* ISR handler macros */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + * + */ + +static inline uint32_t or1k_interrupt_disable( void ) +{ + uint32_t sr; + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); + + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); + + return sr; +} + +static inline void or1k_interrupt_enable(uint32_t level) +{ + uint32_t sr; + + /* Enable interrupts and restore rs */ + sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); + +} + +#define _CPU_ISR_Disable( _level ) \ + _level = or1k_interrupt_disable() + + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + * + */ + +#define _CPU_ISR_Enable( _level ) \ + or1k_interrupt_enable( _level ) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + * + */ + +#define _CPU_ISR_Flash( _level ) \ + do{ \ + _CPU_ISR_Enable( _level ); \ + _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ + } while(0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & CPU_OR1K_SPR_SR ) != 0; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * The get routine usually must be implemented as a subroutine. + * + */ + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + */ + +/** + * @brief Initializes the CPU context. + * + * The following steps are performed: + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * + * @param[in] context points to the context area + * @param[in] stack_area_begin is the low address of the allocated stack area + * @param[in] stack_area_size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to @c true if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + */ +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * This routine is responsible to initialize the FP context. + * + * The FP area pointer is passed by reference to allow the initial pointer + * into a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + */ +#define _CPU_Context_Initialize_fp( _fp_area_p ) \ + memset( *( _fp_area_p ), 0, CPU_CONTEXT_FP_SIZE ) + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + */ + +#include + +#define _CPU_Fatal_halt(_source, _error ) \ + printk("Fatal Error %d.%" PRId32 " Halted\n",_source, _error); \ + _OR1KSIM_CPU_Halt(); \ + for(;;) + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#endif /* ASM */ + +#define CPU_SIZEOF_POINTER 4 + +#define CPU_MAXIMUM_PROCESSORS 32 + +#ifndef ASM +typedef uint32_t CPU_Counter_ticks; + +typedef struct { + uint32_t r[32]; + + /* The following registers must be saved if we have + fast context switch disabled and nested interrupt + levels are enabled. + */ +#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED + uint32_t epcr; /* exception PC register */ + uint32_t eear; /* exception effective address register */ + uint32_t esr; /* exception supervision register */ +#endif + +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + * + */ + +void _CPU_Initialize( + void +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + * + * Or1k Specific Information: + * + * Please see the comments in the .c file for a description of how + * this function works. There are several things to be aware of. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + * + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + * + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to insure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + */ + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +static inline unsigned int CPU_swap_u32( + unsigned int value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..a5659f35ce --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu_asm.h @@ -0,0 +1,74 @@ +/** + * @file + * + * @brief OR1K Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h new file mode 100644 index 0000000000..98bbe41b00 --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h @@ -0,0 +1,396 @@ +/** + * @file + * + * @brief OR1K utility + */ +/* + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_OR1K_UTILITY_H +#define _RTEMS_SCORE_OR1K_UTILITY_H + +/* SPR groups definitions */ +#define SPR_GRP_SHAMT 11 +#define SPR_GRP0_SYS_CTRL (0 << SPR_GRP_SHAMT) +#define SPR_GRP1_DMMU (1 << SPR_GRP_SHAMT) +#define SPR_GRP2_IMMU (2 << SPR_GRP_SHAMT) +#define SPR_GRP3_DC (3 << SPR_GRP_SHAMT) +#define SPR_GRP4_IC (4 << SPR_GRP_SHAMT) +#define SPR_GRP5_MAC (5 << SPR_GRP_SHAMT) +#define SPR_GRP6_DEBUG (6 << SPR_GRP_SHAMT) +#define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT) +#define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT) +#define SPR_GRP9_PIC (9 << SPR_GRP_SHAMT) +#define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT) +#define SPR_GPR11_FPU (11 << SPR_GRP_SHAMT) + +/* SPR registers definitions */ + +/* Group 0: System control registers */ +#define CPU_OR1K_SPR_VR (SPR_GRP0_SYS_CTRL + 0) +#define CPU_OR1K_SPR_UPR (SPR_GRP0_SYS_CTRL + 1) +#define CPU_OR1K_SPR_CPUCFGR (SPR_GRP0_SYS_CTRL + 2) +#define CPU_OR1K_SPR_DMMUCFGR (SPR_GRP0_SYS_CTRL + 3) +#define CPU_OR1K_SPR_IMMUCFGR (SPR_GRP0_SYS_CTRL + 4) +#define CPU_OR1K_SPR_DCCFGR (SPR_GRP0_SYS_CTRL + 5) +#define CPU_OR1K_SPR_ICCFGR (SPR_GRP0_SYS_CTRL + 6) +#define CPU_OR1K_SPR_DCFGR (SPR_GRP0_SYS_CTRL + 7) +#define CPU_OR1K_SPR_PCCFGR (SPR_GRP0_SYS_CTRL + 8) +#define CPU_OR1K_SPR_VR2 (SPR_GRP0_SYS_CTRL + 9) +#define CPU_OR1K_SPR_AVR (SPR_GRP0_SYS_CTRL + 10) +#define CPU_OR1K_SPR_EVBAR (SPR_GRP0_SYS_CTRL + 11) +#define CPU_OR1K_SPR_AECR (SPR_GRP0_SYS_CTRL + 12) +#define CPU_OR1K_SPR_AESR (SPR_GRP0_SYS_CTRL + 13) +#define CPU_OR1K_SPR_NPC (SPR_GRP0_SYS_CTRL + 16) +#define CPU_OR1K_SPR_SR (SPR_GRP0_SYS_CTRL + 17) +#define CPU_OR1K_SPR_PPC (SPR_GRP0_SYS_CTRL + 18) +#define CPU_OR1K_SPR_FPCSR (SPR_GRP0_SYS_CTRL + 20) +#define CPU_OR1K_SPR_EPCR0 (SPR_GRP0_SYS_CTRL + 32) +#define CPU_OR1K_SPR_EPCR1 (SPR_GRP0_SYS_CTRL + 33) +#define CPU_OR1K_SPR_EPCR2 (SPR_GRP0_SYS_CTRL + 34) +#define CPU_OR1K_SPR_EPCR3 (SPR_GRP0_SYS_CTRL + 35) +#define CPU_OR1K_SPR_EPCR4 (SPR_GRP0_SYS_CTRL + 36) +#define CPU_OR1K_SPR_EPCR5 (SPR_GRP0_SYS_CTRL + 37) +#define CPU_OR1K_SPR_EPCR6 (SPR_GRP0_SYS_CTRL + 38) +#define CPU_OR1K_SPR_EPCR7 (SPR_GRP0_SYS_CTRL + 39) +#define CPU_OR1K_SPR_EPCR8 (SPR_GRP0_SYS_CTRL + 40) +#define CPU_OR1K_SPR_EPCR9 (SPR_GRP0_SYS_CTRL + 41) +#define CPU_OR1K_SPR_EPCR10 (SPR_GRP0_SYS_CTRL + 42) +#define CPU_OR1K_SPR_EPCR11 (SPR_GRP0_SYS_CTRL + 43) +#define CPU_OR1K_SPR_EPCR12 (SPR_GRP0_SYS_CTRL + 44) +#define CPU_OR1K_SPR_EPCR13 (SPR_GRP0_SYS_CTRL + 45) +#define CPU_OR1K_SPR_EPCR14 (SPR_GRP0_SYS_CTRL + 46) +#define CPU_OR1K_SPR_EPCR15 (SPR_GRP0_SYS_CTRL + 47) +#define CPU_OR1K_SPR_EEAR0 (SPR_GRP0_SYS_CTRL + 48) +#define CPU_OR1K_SPR_EEAR1 (SPR_GRP0_SYS_CTRL + 49) +#define CPU_OR1K_SPR_EEAR2 (SPR_GRP0_SYS_CTRL + 50) +#define CPU_OR1K_SPR_EEAR3 (SPR_GRP0_SYS_CTRL + 51) +#define CPU_OR1K_SPR_EEAR4 (SPR_GRP0_SYS_CTRL + 52) +#define CPU_OR1K_SPR_EEAR5 (SPR_GRP0_SYS_CTRL + 53) +#define CPU_OR1K_SPR_EEAR6 (SPR_GRP0_SYS_CTRL + 54) +#define CPU_OR1K_SPR_EEAR7 (SPR_GRP0_SYS_CTRL + 55) +#define CPU_OR1K_SPR_EEAR8 (SPR_GRP0_SYS_CTRL + 56) +#define CPU_OR1K_SPR_EEAR9 (SPR_GRP0_SYS_CTRL + 57) +#define CPU_OR1K_SPR_EEAR10 (SPR_GRP0_SYS_CTRL + 58) +#define CPU_OR1K_SPR_EEAR11 (SPR_GRP0_SYS_CTRL + 59) +#define CPU_OR1K_SPR_EEAR12 (SPR_GRP0_SYS_CTRL + 60) +#define CPU_OR1K_SPR_EEAR13 (SPR_GRP0_SYS_CTRL + 61) +#define CPU_OR1K_SPR_EEAR14 (SPR_GRP0_SYS_CTRL + 62) +#define CPU_OR1K_SPR_EEAR15 (SPR_GRP0_SYS_CTRL + 63) +#define CPU_OR1K_SPR_ESR0 (SPR_GRP0_SYS_CTRL + 64) +#define CPU_OR1K_SPR_ESR1 (SPR_GRP0_SYS_CTRL + 65) +#define CPU_OR1K_SPR_ESR2 (SPR_GRP0_SYS_CTRL + 66) +#define CPU_OR1K_SPR_ESR3 (SPR_GRP0_SYS_CTRL + 67) +#define CPU_OR1K_SPR_ESR4 (SPR_GRP0_SYS_CTRL + 68) +#define CPU_OR1K_SPR_ESR5 (SPR_GRP0_SYS_CTRL + 69) +#define CPU_OR1K_SPR_ESR6 (SPR_GRP0_SYS_CTRL + 70) +#define CPU_OR1K_SPR_ESR7 (SPR_GRP0_SYS_CTRL + 71) +#define CPU_OR1K_SPR_ESR8 (SPR_GRP0_SYS_CTRL + 72) +#define CPU_OR1K_SPR_ESR9 (SPR_GRP0_SYS_CTRL + 73) +#define CPU_OR1K_SPR_ESR10 (SPR_GRP0_SYS_CTRL + 74) +#define CPU_OR1K_SPR_ESR11 (SPR_GRP0_SYS_CTRL + 75) +#define CPU_OR1K_SPR_ESR12 (SPR_GRP0_SYS_CTRL + 76) +#define CPU_OR1K_SPR_ESR13 (SPR_GRP0_SYS_CTRL + 77) +#define CPU_OR1K_SPR_ESR14 (SPR_GRP0_SYS_CTRL + 78) +#define CPU_OR1K_SPR_ESR15 (SPR_GRP0_SYS_CTRL + 79) + +/* Shadow registers base */ +#define CPU_OR1K_SPR_GPR32 (SPR_GRP0_SYS_CTRL + 1024) + +/* Group1: Data MMU registers */ +#define CPU_OR1K_SPR_DMMUCR (SPR_GRP1_DMMU + 0) +#define CPU_OR1K_SPR_DMMUPR (SPR_GRP1_DMMU + 1) +#define CPU_OR1K_SPR_DTLBEIR (SPR_GRP1_DMMU + 2) +#define CPU_OR1K_SPR_DATBMR0 (SPR_GRP1_DMMU + 4) +#define CPU_OR1K_SPR_DATBMR1 (SPR_GRP1_DMMU + 5) +#define CPU_OR1K_SPR_DATBMR2 (SPR_GRP1_DMMU + 6) +#define CPU_OR1K_SPR_DATBMR3 (SPR_GRP1_DMMU + 7) +#define CPU_OR1K_SPR_DATBTR0 (SPR_GRP1_DMMU + 8) +#define CPU_OR1K_SPR_DATBTR1 (SPR_GRP1_DMMU + 9) +#define CPU_OR1K_SPR_DATBTR2 (SPR_GRP1_DMMU + 10) +#define CPU_OR1K_SPR_DATBTR3 (SPR_GRP1_DMMU + 11) + +/* Group2: Instruction MMU registers */ +#define CPU_OR1K_SPR_IMMUCR (SPR_GRP2_IMMU + 0) +#define CPU_OR1K_SPR_IMMUPR (SPR_GRP2_IMMU + 1) +#define CPU_OR1K_SPR_ITLBEIR (SPR_GRP2_IMMU + 2) +#define CPU_OR1K_SPR_IATBMR0 (SPR_GRP2_IMMU + 4) +#define CPU_OR1K_SPR_IATBMR1 (SPR_GRP2_IMMU + 5) +#define CPU_OR1K_SPR_IATBMR2 (SPR_GRP2_IMMU + 6) +#define CPU_OR1K_SPR_IATBMR3 (SPR_GRP2_IMMU + 7) +#define CPU_OR1K_SPR_IATBTR0 (SPR_GRP2_IMMU + 8) +#define CPU_OR1K_SPR_IATBTR1 (SPR_GRP2_IMMU + 9) +#define CPU_OR1K_SPR_IATBTR2 (SPR_GRP2_IMMU + 10) +#define CPU_OR1K_SPR_IATBTR3 (SPR_GRP2_IMMU + 11) + +/* Group3: Data Cache registers */ +#define CPU_OR1K_SPR_DCCR (SPR_GRP3_DC + 0) +#define CPU_OR1K_SPR_DCBPR (SPR_GRP3_DC + 1) +#define CPU_OR1K_SPR_DCBFR (SPR_GRP3_DC + 2) +#define CPU_OR1K_SPR_DCBIR (SPR_GRP3_DC + 3) +#define CPU_OR1K_SPR_DCBWR (SPR_GRP3_DC + 4) +#define CPU_OR1K_SPR_DCBLR (SPR_GRP3_DC + 5) + +/* Group4: Instruction Cache registers */ +#define CPU_OR1K_SPR_ICCR (SPR_GRP4_IC + 0) +#define CPU_OR1K_SPR_ICBPR (SPR_GRP4_IC + 1) +#define CPU_OR1K_SPR_ICBIR (SPR_GRP4_IC + 2) +#define CPU_OR1K_SPR_ICBLR (SPR_GRP4_IC + 3) + +/* Group5: MAC registers */ +#define CPU_OR1K_SPR_MACLO (SPR_GRP5_MAC + 1) +#define CPU_OR1K_SPR_MACHI (SPR_GRP5_MAC + 2) + +/* Group6: Debug registers */ +#define CPU_OR1K_SPR_DVR0 (SPR_GRP6_DEBUG + 0) +#define CPU_OR1K_SPR_DVR1 (SPR_GRP6_DEBUG + 1) +#define CPU_OR1K_SPR_DVR2 (SPR_GRP6_DEBUG + 2) +#define CPU_OR1K_SPR_DVR3 (SPR_GRP6_DEBUG + 3) +#define CPU_OR1K_SPR_DVR4 (SPR_GRP6_DEBUG + 4) +#define CPU_OR1K_SPR_DVR5 (SPR_GRP6_DEBUG + 5) +#define CPU_OR1K_SPR_DVR6 (SPR_GRP6_DEBUG + 6) +#define CPU_OR1K_SPR_DVR7 (SPR_GRP6_DEBUG + 7) +#define CPU_OR1K_SPR_DCR0 (SPR_GRP6_DEBUG + 8) +#define CPU_OR1K_SPR_DCR1 (SPR_GRP6_DEBUG + 9) +#define CPU_OR1K_SPR_DCR2 (SPR_GRP6_DEBUG + 10) +#define CPU_OR1K_SPR_DCR3 (SPR_GRP6_DEBUG + 11) +#define CPU_OR1K_SPR_DCR4 (SPR_GRP6_DEBUG + 12) +#define CPU_OR1K_SPR_DCR5 (SPR_GRP6_DEBUG + 13) +#define CPU_OR1K_SPR_DCR6 (SPR_GRP6_DEBUG + 14) +#define CPU_OR1K_SPR_DCR7 (SPR_GRP6_DEBUG + 15) +#define CPU_OR1K_SPR_DMR1 (SPR_GRP6_DEBUG + 16) +#define CPU_OR1K_SPR_DMR2 (SPR_GRP6_DEBUG + 17) +#define CPU_OR1K_SPR_DCWR0 (SPR_GRP6_DEBUG + 18) +#define CPU_OR1K_SPR_DCWR1 (SPR_GRP6_DEBUG + 19) +#define CPU_OR1K_SPR_DSR (SPR_GRP6_DEBUG + 20) +#define CPU_OR1K_SPR_DRR (SPR_GRP6_DEBUG + 21) + +/* Group7: Performance counters registers */ +#define CPU_OR1K_SPR_PCCR0 (SPR_GRP7_PERF_CTR + 0) +#define CPU_OR1K_SPR_PCCR1 (SPR_GRP7_PERF_CTR + 1) +#define CPU_OR1K_SPR_PCCR2 (SPR_GRP7_PERF_CTR + 2) +#define CPU_OR1K_SPR_PCCR3 (SPR_GRP7_PERF_CTR + 3) +#define CPU_OR1K_SPR_PCCR4 (SPR_GRP7_PERF_CTR + 4) +#define CPU_OR1K_SPR_PCCR5 (SPR_GRP7_PERF_CTR + 5) +#define CPU_OR1K_SPR_PCCR6 (SPR_GRP7_PERF_CTR + 6) +#define CPU_OR1K_SPR_PCCR7 (SPR_GRP7_PERF_CTR + 7) +#define CPU_OR1K_SPR_PCMR0 (SPR_GRP7_PERF_CTR + 8) +#define CPU_OR1K_SPR_PCMR1 (SPR_GRP7_PERF_CTR + 9) +#define CPU_OR1K_SPR_PCMR2 (SPR_GRP7_PERF_CTR + 10) +#define CPU_OR1K_SPR_PCMR3 (SPR_GRP7_PERF_CTR + 11) +#define CPU_OR1K_SPR_PCMR4 (SPR_GRP7_PERF_CTR + 12) +#define CPU_OR1K_SPR_PCMR5 (SPR_GRP7_PERF_CTR + 13) +#define CPU_OR1K_SPR_PCMR6 (SPR_GRP7_PERF_CTR + 14) +#define CPU_OR1K_SPR_PCMR7 (SPR_GRP7_PERF_CTR + 15) + +/* Group8: Power management register */ +#define CPU_OR1K_SPR_PMR (SPR_GRP8_PWR_MNG + 0) + +/* Group9: PIC registers */ +#define CPU_OR1K_SPR_PICMR (SPR_GRP9_PIC + 0) +#define CPU_OR1K_SPR_PICSR (SPR_GRP9_PIC + 2) + +/* Group10: Tick Timer registers */ +#define CPU_OR1K_SPR_TTMR (SPR_GPR10_TICK_TMR + 0) +#define CPU_OR1K_SPR_TTCR (SPR_GPR10_TICK_TMR + 1) + + /* Shift amount macros for bits position in Supervision Register */ +#define CPU_OR1K_SPR_SR_SHAMT_SM (0) +#define CPU_OR1K_SPR_SR_SHAMT_TEE (1) +#define CPU_OR1K_SPR_SR_SHAMT_IEE (2) +#define CPU_OR1K_SPR_SR_SHAMT_DCE (3) +#define CPU_OR1K_SPR_SR_SHAMT_ICE (4) +#define CPU_OR1K_SPR_SR_SHAMT_DME (5) +#define CPU_OR1K_SPR_SR_SHAMT_IME (6) +#define CPU_OR1K_SPR_SR_SHAMT_LEE (7) +#define CPU_OR1K_SPR_SR_SHAMT_CE (8) +#define CPU_OR1K_SPR_SR_SHAMT_F (9) +#define CPU_OR1K_SPR_SR_SHAMT_CY (10) +#define CPU_OR1K_SPR_SR_SHAMT_OV (11) +#define CPU_OR1K_SPR_SR_SHAMT_OVE (12) +#define CPU_OR1K_SPR_SR_SHAMT_DSX (13) +#define CPU_OR1K_SPR_SR_SHAMT_EPH (14) +#define CPU_OR1K_SPR_SR_SHAMT_FO (15) +#define CPU_OR1K_SPR_SR_SHAMT_SUMRA (16) +#define CPU_OR1K_SPR_SR_SHAMT_CID (28) + +/* Supervision Mode Register. @see OpenRISC architecture manual*/ + + /* Supervisor Mode */ +#define CPU_OR1K_SPR_SR_SM (1 << CPU_OR1K_SPR_SR_SHAMT_SM) +/* Tick Timer Exception Enabled */ +#define CPU_OR1K_SPR_SR_TEE (1 << CPU_OR1K_SPR_SR_SHAMT_TEE) +/* Interrupt Exception Enabled */ +#define CPU_OR1K_SPR_SR_IEE (1 << CPU_OR1K_SPR_SR_SHAMT_IEE) +/* Data Cache Enable */ +#define CPU_OR1K_SPR_SR_DCE (1 << CPU_OR1K_SPR_SR_SHAMT_DCE) +/* Instruction Cache Enable */ +#define CPU_OR1K_SPR_SR_ICE (1 << CPU_OR1K_SPR_SR_SHAMT_ICE) +/* Data MMU Enable */ +#define CPU_OR1K_SPR_SR_DME (1 << CPU_OR1K_SPR_SR_SHAMT_DME) +/* Instruction MMU Enable */ +#define CPU_OR1K_SPR_SR_IME (1 << CPU_OR1K_SPR_SR_SHAMT_IME) +/* Little Endian Enable */ +#define CPU_OR1K_SPR_SR_LEE (1 << CPU_OR1K_SPR_SR_SHAMT_LEE) +/* CID Enable */ +#define CPU_OR1K_SPR_SR_CE (1 << CPU_OR1K_SPR_SR_SHAMT_CE) +/* Conditional branch flag */ +#define CPU_OR1K_SPR_SR_F (1 << CPU_OR1K_SPR_SR_SHAMT_F) +/* Carry flag */ +#define CPU_OR1K_SPR_SR_CY (1 << CPU_OR1K_SPR_SR_SHAMT_CY) +/* Overflow flag */ +#define CPU_OR1K_SPR_SR_OV (1 << CPU_OR1K_SPR_SR_SHAMT_OV) +/* Overflow flag Exception */ +#define CPU_OR1K_SPR_SR_OVE (1 << CPU_OR1K_SPR_SR_SHAMT_OVE) +/* Delay Slot Exception */ +#define CPU_OR1K_SPR_SR_DSX (1 << CPU_OR1K_SPR_SR_SHAMT_DSX) + /* Exception Prefix High */ +#define CPU_OR1K_SPR_SR_EPH (1 << CPU_OR1K_SPR_SR_SHAMT_EPH) +/* Fixed One */ +#define CPU_OR1K_SPR_SR_FO (1 << CPU_OR1K_SPR_SR_SHAMT_FO) +/* SPRs User Mode Read Access */ +#define CPU_OR1K_SPR_SR_SUMRA (1 << CPU_OR1K_SPR_SR_SHAMT_SUMRA) +/*Context ID (Fast Context Switching) */ +#define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) + +/* Tick timer configuration bits */ +#define CPU_OR1K_SPR_TTMR_SHAMT_IP 28 +#define CPU_OR1K_SPR_TTMR_SHAMT_IE 29 +#define CPU_OR1K_SPR_TTMR_SHAMT_MODE 30 + +#define CPU_OR1K_SPR_TTMR_TP_MASK (0x0FFFFFFF) +#define CPU_OR1K_SPR_TTMR_IP (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP) +#define CPU_OR1K_SPR_TTMR_IE (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE) +#define CPU_OR1K_SPR_TTMR_MODE_RESTART (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_CONT (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) + +/* Power management register bits */ + +/* Shift amount macros for bit positions in Power Management register */ +#define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 +#define CPU_OR1K_SPR_PMR_SHAMT_DME 4 +#define CPU_OR1K_SPR_PMR_SHAMT_SME 5 +#define CPU_OR1K_SPR_PMR_SHAMT_DCGE 6 +#define CPU_OR1K_SPR_PMR_SHAMT_SUME 7 + +#define CPU_OR1K_SPR_PMR_SDF (0xF << CPU_OR1K_SPR_PMR_SHAMT_SDF) +#define CPU_OR1K_SPR_PMR_DME (1 << CPU_OR1K_SPR_PMR_SHAMT_DME) +#define CPU_OR1K_SPR_PMR_SME (1 << CPU_OR1K_SPR_PMR_SHAMT_SME) +#define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) +#define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) + +#ifndef ASM + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Supervision Mode registers definitions. + * + * @see OpenRISC architecture manual - revision 0. + */ +typedef enum { + OR1K_EXCEPTION_RESET = 1, + OR1K_EXCEPTION_BUS_ERR = 2, + OR1K_EXCEPTION_D_PF = 3, /* Data Page Fault */ + OR1K_EXCEPTION_I_PF = 4, /* Instruction Page Fault */ + OR1K_EXCEPTION_TICK_TIMER = 5, + OR1K_EXCEPTION_ALIGNMENT = 6, + OR1K_EXCEPTION_I_UNDEF= 7, /* Undefiend instruction */ + OR1K_EXCEPTION_IRQ = 8, /* External interrupt */ + OR1K_EXCPETION_D_TLB = 9, /* Data TLB miss */ + OR1K_EXCPETION_I_TLB = 10, /* Instruction TLB miss */ + OR1K_EXCPETION_RANGE = 11, /* Range exception */ + OR1K_EXCPETION_SYS_CALL = 12, + OR1K_EXCPETION_FP = 13, /* Floating point exception */ + OR1K_EXCPETION_TRAP = 14, /* Caused by l.trap instruction or by debug unit */ + OR1K_EXCPETION_RESERVED1 = 15, + OR1K_EXCPETION_RESERVED2 = 16, + OR1K_EXCPETION_RESERVED3 = 17, + MAX_EXCEPTIONS = 17, + OR1K_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff +} OR1K_Symbolic_exception_name; + +static inline uint32_t _OR1K_mfspr(uint32_t reg) +{ + uint32_t spr_value; + + asm volatile ( + "l.mfspr %0, %1, 0;\n\t" + : "=r" (spr_value) : "r" (reg)); + + return spr_value; +} + +static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) +{ + asm volatile ( + "l.mtspr %1, %0, 0;\n\t" + :: "r" (value), "r" (reg) + ); +} + +/** + * @brief The slow down feature takes advantage of the low-power + * dividers in external clock generation circuitry to enable full + * functionality, but at a lower frequency so that power consumption + * is reduced. @see OpenRISC architecture manual, power management section. + * + * @param[in] value is 4 bit value to be written in PMR[SDF]. + * A lower value specifies higher expected performance from the processor core. + * + */ +#define _OR1K_CPU_SlowDown(value) \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, (value & CPU_OR1K_SPR_PMR_SDF)) + + +#define _OR1K_CPU_Doze() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_DME) + + +#define _OR1K_CPU_Sleep() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) + +#define _OR1K_CPU_Suspend() \ + _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) + +static inline void _OR1K_Sync_mem( void ) +{ + asm volatile("l.msync"); +} + +static inline void _OR1K_Sync_pipeline( void ) +{ + asm volatile("l.psync"); +} + +/** + * @brief or1ksim simulator can be sent a halt signal from RTEMS to tell + * the running or1ksim process on the host machine to exit. The following + * implementation has no effect on QEMU or hardware implementation and will + * be treated as normal l.nop. + * + */ +#define _OR1KSIM_CPU_Halt() \ + asm volatile ("l.nop 0xc") + +#ifdef __cplusplus +} +#endif + +#else /* ASM */ + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_OR1K_UTILITY_H */ diff --git a/cpukit/score/cpu/or1k/include/rtems/score/or1k.h b/cpukit/score/cpu/or1k/include/rtems/score/or1k.h new file mode 100644 index 0000000000..e1a3ddce42 --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/or1k.h @@ -0,0 +1,49 @@ +/** + * @file rtems/score/or1k.h + */ + +/* + * This file contains information pertaining to the OR1K processor. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_OR1K_H +#define _RTEMS_SCORE_OR1K_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the OR1K family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + + /* + * Define the name of the CPU family and specific model. + */ + +#define CPU_NAME "OR1K" +#define CPU_MODEL_NAME "OR1200" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_OR1K_H */ diff --git a/cpukit/score/cpu/or1k/include/rtems/score/types.h b/cpukit/score/cpu/or1k/include/rtems/score/types.h new file mode 100644 index 0000000000..09790feb29 --- /dev/null +++ b/cpukit/score/cpu/or1k/include/rtems/score/types.h @@ -0,0 +1,53 @@ +/** + * @file + * + * @brief OR1K Architecture Types API + */ + +/* + * This include file contains type definitions pertaining to the + * arm processor family. + * + * COPYRIGHT (c) 2014 Hesham ALMatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + + #ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void or1k_isr; +typedef void ( *or1k_isr_entry )( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/or1k/preinstall.am b/cpukit/score/cpu/or1k/preinstall.am deleted file mode 100644 index eae1e46d14..0000000000 --- a/cpukit/score/cpu/or1k/preinstall.am +++ /dev/null @@ -1,57 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES += $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/or1k.h: rtems/score/or1k.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or1k.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or1k.h - -$(PROJECT_INCLUDE)/rtems/score/or1k-utility.h: rtems/score/or1k-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or1k-utility.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or1k-utility.h - diff --git a/cpukit/score/cpu/or1k/rtems/asm.h b/cpukit/score/cpu/or1k/rtems/asm.h deleted file mode 100644 index 4d2c22698b..0000000000 --- a/cpukit/score/cpu/or1k/rtems/asm.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - */ - -#ifndef __OR1K_ASM_h -#define __OR1K_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h b/cpukit/score/cpu/or1k/rtems/score/cpu.h deleted file mode 100644 index 6daca10f9c..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpu.h +++ /dev/null @@ -1,872 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains macros pertaining to the Opencores - * or1k processor family. - * - * COPYRIGHT (c) 2014 Hesham ALMatary - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file adapted from no_cpu example of the RTEMS distribution. - * The body has been modified for the Opencores OR1k implementation by - * Chris Ziomkowski. - * - */ - -#ifndef _OR1K_CPU_H -#define _OR1K_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#include /* pick up machine definitions */ -#include -#include -#ifndef ASM -#include -#include -#include /* for printk */ -#endif - -/* conditional compilation parameters */ - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Currently, for or1k port, _ISR_Handler is responsible for switching to - * RTEMS dedicated interrupt task. - * - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "OR1K_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Or1k Specific Information: - * - * At this time there are no implementations of Or1k that are - * expected to implement floating point. More importantly, the - * floating point architecture is expected to change significantly - * before such chips are fabricated. - */ - -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * Or1k Specific Information: - * - * This version of RTEMS is designed specifically to run with - * big endian architectures. If you want little endian, you'll - * have to make the appropriate adjustments here and write - * efficient routines for byte swapping. The Or1k architecture - * doesn't do this very well. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - */ - - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * - */ -#ifndef ASM -#ifdef OR1K_64BIT_ARCH -#define or1kreg uint64_t -#else -#define or1kreg uint32_t -#endif - -typedef struct { - uint32_t r1; /* Stack pointer */ - uint32_t r2; /* Frame pointer */ - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t r28; - uint32_t r29; - uint32_t r30; - uint32_t r31; - - uint32_t sr; /* Current supervision register non persistent values */ - uint32_t epcr; - uint32_t eear; - uint32_t esr; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r1 - -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Or1k Specific Information: - * - */ - -#define CPU_CONTEXT_FP_SIZE 0 - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - */ - -#define CPU_ALIGNMENT 8 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline uint32_t or1k_interrupt_disable( void ) -{ - uint32_t sr; - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - - _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); - - return sr; -} - -static inline void or1k_interrupt_enable(uint32_t level) -{ - uint32_t sr; - - /* Enable interrupts and restore rs */ - sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; - _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); - -} - -#define _CPU_ISR_Disable( _level ) \ - _level = or1k_interrupt_disable() - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - */ - -#define _CPU_ISR_Enable( _level ) \ - or1k_interrupt_enable( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - */ - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - _CPU_ISR_Enable( _level ); \ - _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ - } while(0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & CPU_OR1K_SPR_SR ) != 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - */ - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - */ - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine is responsible to initialize the FP context. - * - * The FP area pointer is passed by reference to allow the initial pointer - * into a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ -#define _CPU_Context_Initialize_fp( _fp_area_p ) \ - memset( *( _fp_area_p ), 0, CPU_CONTEXT_FP_SIZE ) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - */ - -#include - -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%" PRId32 " Halted\n",_source, _error); \ - _OR1KSIM_CPU_Halt(); \ - for(;;) - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#endif /* ASM */ - -#define CPU_SIZEOF_POINTER 4 - -#define CPU_MAXIMUM_PROCESSORS 32 - -#ifndef ASM -typedef uint32_t CPU_Counter_ticks; - -typedef struct { - uint32_t r[32]; - - /* The following registers must be saved if we have - fast context switch disabled and nested interrupt - levels are enabled. - */ -#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED - uint32_t epcr; /* exception PC register */ - uint32_t eear; /* exception effective address register */ - uint32_t esr; /* exception supervision register */ -#endif - -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * Or1k Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h deleted file mode 100644 index a5659f35ce..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief OR1K Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/or1k/rtems/score/cpuatomic.h b/cpukit/score/cpu/or1k/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h deleted file mode 100644 index 98bbe41b00..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h +++ /dev/null @@ -1,396 +0,0 @@ -/** - * @file - * - * @brief OR1K utility - */ -/* - * COPYRIGHT (c) 2014 Hesham ALMatary - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_OR1K_UTILITY_H -#define _RTEMS_SCORE_OR1K_UTILITY_H - -/* SPR groups definitions */ -#define SPR_GRP_SHAMT 11 -#define SPR_GRP0_SYS_CTRL (0 << SPR_GRP_SHAMT) -#define SPR_GRP1_DMMU (1 << SPR_GRP_SHAMT) -#define SPR_GRP2_IMMU (2 << SPR_GRP_SHAMT) -#define SPR_GRP3_DC (3 << SPR_GRP_SHAMT) -#define SPR_GRP4_IC (4 << SPR_GRP_SHAMT) -#define SPR_GRP5_MAC (5 << SPR_GRP_SHAMT) -#define SPR_GRP6_DEBUG (6 << SPR_GRP_SHAMT) -#define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT) -#define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT) -#define SPR_GRP9_PIC (9 << SPR_GRP_SHAMT) -#define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT) -#define SPR_GPR11_FPU (11 << SPR_GRP_SHAMT) - -/* SPR registers definitions */ - -/* Group 0: System control registers */ -#define CPU_OR1K_SPR_VR (SPR_GRP0_SYS_CTRL + 0) -#define CPU_OR1K_SPR_UPR (SPR_GRP0_SYS_CTRL + 1) -#define CPU_OR1K_SPR_CPUCFGR (SPR_GRP0_SYS_CTRL + 2) -#define CPU_OR1K_SPR_DMMUCFGR (SPR_GRP0_SYS_CTRL + 3) -#define CPU_OR1K_SPR_IMMUCFGR (SPR_GRP0_SYS_CTRL + 4) -#define CPU_OR1K_SPR_DCCFGR (SPR_GRP0_SYS_CTRL + 5) -#define CPU_OR1K_SPR_ICCFGR (SPR_GRP0_SYS_CTRL + 6) -#define CPU_OR1K_SPR_DCFGR (SPR_GRP0_SYS_CTRL + 7) -#define CPU_OR1K_SPR_PCCFGR (SPR_GRP0_SYS_CTRL + 8) -#define CPU_OR1K_SPR_VR2 (SPR_GRP0_SYS_CTRL + 9) -#define CPU_OR1K_SPR_AVR (SPR_GRP0_SYS_CTRL + 10) -#define CPU_OR1K_SPR_EVBAR (SPR_GRP0_SYS_CTRL + 11) -#define CPU_OR1K_SPR_AECR (SPR_GRP0_SYS_CTRL + 12) -#define CPU_OR1K_SPR_AESR (SPR_GRP0_SYS_CTRL + 13) -#define CPU_OR1K_SPR_NPC (SPR_GRP0_SYS_CTRL + 16) -#define CPU_OR1K_SPR_SR (SPR_GRP0_SYS_CTRL + 17) -#define CPU_OR1K_SPR_PPC (SPR_GRP0_SYS_CTRL + 18) -#define CPU_OR1K_SPR_FPCSR (SPR_GRP0_SYS_CTRL + 20) -#define CPU_OR1K_SPR_EPCR0 (SPR_GRP0_SYS_CTRL + 32) -#define CPU_OR1K_SPR_EPCR1 (SPR_GRP0_SYS_CTRL + 33) -#define CPU_OR1K_SPR_EPCR2 (SPR_GRP0_SYS_CTRL + 34) -#define CPU_OR1K_SPR_EPCR3 (SPR_GRP0_SYS_CTRL + 35) -#define CPU_OR1K_SPR_EPCR4 (SPR_GRP0_SYS_CTRL + 36) -#define CPU_OR1K_SPR_EPCR5 (SPR_GRP0_SYS_CTRL + 37) -#define CPU_OR1K_SPR_EPCR6 (SPR_GRP0_SYS_CTRL + 38) -#define CPU_OR1K_SPR_EPCR7 (SPR_GRP0_SYS_CTRL + 39) -#define CPU_OR1K_SPR_EPCR8 (SPR_GRP0_SYS_CTRL + 40) -#define CPU_OR1K_SPR_EPCR9 (SPR_GRP0_SYS_CTRL + 41) -#define CPU_OR1K_SPR_EPCR10 (SPR_GRP0_SYS_CTRL + 42) -#define CPU_OR1K_SPR_EPCR11 (SPR_GRP0_SYS_CTRL + 43) -#define CPU_OR1K_SPR_EPCR12 (SPR_GRP0_SYS_CTRL + 44) -#define CPU_OR1K_SPR_EPCR13 (SPR_GRP0_SYS_CTRL + 45) -#define CPU_OR1K_SPR_EPCR14 (SPR_GRP0_SYS_CTRL + 46) -#define CPU_OR1K_SPR_EPCR15 (SPR_GRP0_SYS_CTRL + 47) -#define CPU_OR1K_SPR_EEAR0 (SPR_GRP0_SYS_CTRL + 48) -#define CPU_OR1K_SPR_EEAR1 (SPR_GRP0_SYS_CTRL + 49) -#define CPU_OR1K_SPR_EEAR2 (SPR_GRP0_SYS_CTRL + 50) -#define CPU_OR1K_SPR_EEAR3 (SPR_GRP0_SYS_CTRL + 51) -#define CPU_OR1K_SPR_EEAR4 (SPR_GRP0_SYS_CTRL + 52) -#define CPU_OR1K_SPR_EEAR5 (SPR_GRP0_SYS_CTRL + 53) -#define CPU_OR1K_SPR_EEAR6 (SPR_GRP0_SYS_CTRL + 54) -#define CPU_OR1K_SPR_EEAR7 (SPR_GRP0_SYS_CTRL + 55) -#define CPU_OR1K_SPR_EEAR8 (SPR_GRP0_SYS_CTRL + 56) -#define CPU_OR1K_SPR_EEAR9 (SPR_GRP0_SYS_CTRL + 57) -#define CPU_OR1K_SPR_EEAR10 (SPR_GRP0_SYS_CTRL + 58) -#define CPU_OR1K_SPR_EEAR11 (SPR_GRP0_SYS_CTRL + 59) -#define CPU_OR1K_SPR_EEAR12 (SPR_GRP0_SYS_CTRL + 60) -#define CPU_OR1K_SPR_EEAR13 (SPR_GRP0_SYS_CTRL + 61) -#define CPU_OR1K_SPR_EEAR14 (SPR_GRP0_SYS_CTRL + 62) -#define CPU_OR1K_SPR_EEAR15 (SPR_GRP0_SYS_CTRL + 63) -#define CPU_OR1K_SPR_ESR0 (SPR_GRP0_SYS_CTRL + 64) -#define CPU_OR1K_SPR_ESR1 (SPR_GRP0_SYS_CTRL + 65) -#define CPU_OR1K_SPR_ESR2 (SPR_GRP0_SYS_CTRL + 66) -#define CPU_OR1K_SPR_ESR3 (SPR_GRP0_SYS_CTRL + 67) -#define CPU_OR1K_SPR_ESR4 (SPR_GRP0_SYS_CTRL + 68) -#define CPU_OR1K_SPR_ESR5 (SPR_GRP0_SYS_CTRL + 69) -#define CPU_OR1K_SPR_ESR6 (SPR_GRP0_SYS_CTRL + 70) -#define CPU_OR1K_SPR_ESR7 (SPR_GRP0_SYS_CTRL + 71) -#define CPU_OR1K_SPR_ESR8 (SPR_GRP0_SYS_CTRL + 72) -#define CPU_OR1K_SPR_ESR9 (SPR_GRP0_SYS_CTRL + 73) -#define CPU_OR1K_SPR_ESR10 (SPR_GRP0_SYS_CTRL + 74) -#define CPU_OR1K_SPR_ESR11 (SPR_GRP0_SYS_CTRL + 75) -#define CPU_OR1K_SPR_ESR12 (SPR_GRP0_SYS_CTRL + 76) -#define CPU_OR1K_SPR_ESR13 (SPR_GRP0_SYS_CTRL + 77) -#define CPU_OR1K_SPR_ESR14 (SPR_GRP0_SYS_CTRL + 78) -#define CPU_OR1K_SPR_ESR15 (SPR_GRP0_SYS_CTRL + 79) - -/* Shadow registers base */ -#define CPU_OR1K_SPR_GPR32 (SPR_GRP0_SYS_CTRL + 1024) - -/* Group1: Data MMU registers */ -#define CPU_OR1K_SPR_DMMUCR (SPR_GRP1_DMMU + 0) -#define CPU_OR1K_SPR_DMMUPR (SPR_GRP1_DMMU + 1) -#define CPU_OR1K_SPR_DTLBEIR (SPR_GRP1_DMMU + 2) -#define CPU_OR1K_SPR_DATBMR0 (SPR_GRP1_DMMU + 4) -#define CPU_OR1K_SPR_DATBMR1 (SPR_GRP1_DMMU + 5) -#define CPU_OR1K_SPR_DATBMR2 (SPR_GRP1_DMMU + 6) -#define CPU_OR1K_SPR_DATBMR3 (SPR_GRP1_DMMU + 7) -#define CPU_OR1K_SPR_DATBTR0 (SPR_GRP1_DMMU + 8) -#define CPU_OR1K_SPR_DATBTR1 (SPR_GRP1_DMMU + 9) -#define CPU_OR1K_SPR_DATBTR2 (SPR_GRP1_DMMU + 10) -#define CPU_OR1K_SPR_DATBTR3 (SPR_GRP1_DMMU + 11) - -/* Group2: Instruction MMU registers */ -#define CPU_OR1K_SPR_IMMUCR (SPR_GRP2_IMMU + 0) -#define CPU_OR1K_SPR_IMMUPR (SPR_GRP2_IMMU + 1) -#define CPU_OR1K_SPR_ITLBEIR (SPR_GRP2_IMMU + 2) -#define CPU_OR1K_SPR_IATBMR0 (SPR_GRP2_IMMU + 4) -#define CPU_OR1K_SPR_IATBMR1 (SPR_GRP2_IMMU + 5) -#define CPU_OR1K_SPR_IATBMR2 (SPR_GRP2_IMMU + 6) -#define CPU_OR1K_SPR_IATBMR3 (SPR_GRP2_IMMU + 7) -#define CPU_OR1K_SPR_IATBTR0 (SPR_GRP2_IMMU + 8) -#define CPU_OR1K_SPR_IATBTR1 (SPR_GRP2_IMMU + 9) -#define CPU_OR1K_SPR_IATBTR2 (SPR_GRP2_IMMU + 10) -#define CPU_OR1K_SPR_IATBTR3 (SPR_GRP2_IMMU + 11) - -/* Group3: Data Cache registers */ -#define CPU_OR1K_SPR_DCCR (SPR_GRP3_DC + 0) -#define CPU_OR1K_SPR_DCBPR (SPR_GRP3_DC + 1) -#define CPU_OR1K_SPR_DCBFR (SPR_GRP3_DC + 2) -#define CPU_OR1K_SPR_DCBIR (SPR_GRP3_DC + 3) -#define CPU_OR1K_SPR_DCBWR (SPR_GRP3_DC + 4) -#define CPU_OR1K_SPR_DCBLR (SPR_GRP3_DC + 5) - -/* Group4: Instruction Cache registers */ -#define CPU_OR1K_SPR_ICCR (SPR_GRP4_IC + 0) -#define CPU_OR1K_SPR_ICBPR (SPR_GRP4_IC + 1) -#define CPU_OR1K_SPR_ICBIR (SPR_GRP4_IC + 2) -#define CPU_OR1K_SPR_ICBLR (SPR_GRP4_IC + 3) - -/* Group5: MAC registers */ -#define CPU_OR1K_SPR_MACLO (SPR_GRP5_MAC + 1) -#define CPU_OR1K_SPR_MACHI (SPR_GRP5_MAC + 2) - -/* Group6: Debug registers */ -#define CPU_OR1K_SPR_DVR0 (SPR_GRP6_DEBUG + 0) -#define CPU_OR1K_SPR_DVR1 (SPR_GRP6_DEBUG + 1) -#define CPU_OR1K_SPR_DVR2 (SPR_GRP6_DEBUG + 2) -#define CPU_OR1K_SPR_DVR3 (SPR_GRP6_DEBUG + 3) -#define CPU_OR1K_SPR_DVR4 (SPR_GRP6_DEBUG + 4) -#define CPU_OR1K_SPR_DVR5 (SPR_GRP6_DEBUG + 5) -#define CPU_OR1K_SPR_DVR6 (SPR_GRP6_DEBUG + 6) -#define CPU_OR1K_SPR_DVR7 (SPR_GRP6_DEBUG + 7) -#define CPU_OR1K_SPR_DCR0 (SPR_GRP6_DEBUG + 8) -#define CPU_OR1K_SPR_DCR1 (SPR_GRP6_DEBUG + 9) -#define CPU_OR1K_SPR_DCR2 (SPR_GRP6_DEBUG + 10) -#define CPU_OR1K_SPR_DCR3 (SPR_GRP6_DEBUG + 11) -#define CPU_OR1K_SPR_DCR4 (SPR_GRP6_DEBUG + 12) -#define CPU_OR1K_SPR_DCR5 (SPR_GRP6_DEBUG + 13) -#define CPU_OR1K_SPR_DCR6 (SPR_GRP6_DEBUG + 14) -#define CPU_OR1K_SPR_DCR7 (SPR_GRP6_DEBUG + 15) -#define CPU_OR1K_SPR_DMR1 (SPR_GRP6_DEBUG + 16) -#define CPU_OR1K_SPR_DMR2 (SPR_GRP6_DEBUG + 17) -#define CPU_OR1K_SPR_DCWR0 (SPR_GRP6_DEBUG + 18) -#define CPU_OR1K_SPR_DCWR1 (SPR_GRP6_DEBUG + 19) -#define CPU_OR1K_SPR_DSR (SPR_GRP6_DEBUG + 20) -#define CPU_OR1K_SPR_DRR (SPR_GRP6_DEBUG + 21) - -/* Group7: Performance counters registers */ -#define CPU_OR1K_SPR_PCCR0 (SPR_GRP7_PERF_CTR + 0) -#define CPU_OR1K_SPR_PCCR1 (SPR_GRP7_PERF_CTR + 1) -#define CPU_OR1K_SPR_PCCR2 (SPR_GRP7_PERF_CTR + 2) -#define CPU_OR1K_SPR_PCCR3 (SPR_GRP7_PERF_CTR + 3) -#define CPU_OR1K_SPR_PCCR4 (SPR_GRP7_PERF_CTR + 4) -#define CPU_OR1K_SPR_PCCR5 (SPR_GRP7_PERF_CTR + 5) -#define CPU_OR1K_SPR_PCCR6 (SPR_GRP7_PERF_CTR + 6) -#define CPU_OR1K_SPR_PCCR7 (SPR_GRP7_PERF_CTR + 7) -#define CPU_OR1K_SPR_PCMR0 (SPR_GRP7_PERF_CTR + 8) -#define CPU_OR1K_SPR_PCMR1 (SPR_GRP7_PERF_CTR + 9) -#define CPU_OR1K_SPR_PCMR2 (SPR_GRP7_PERF_CTR + 10) -#define CPU_OR1K_SPR_PCMR3 (SPR_GRP7_PERF_CTR + 11) -#define CPU_OR1K_SPR_PCMR4 (SPR_GRP7_PERF_CTR + 12) -#define CPU_OR1K_SPR_PCMR5 (SPR_GRP7_PERF_CTR + 13) -#define CPU_OR1K_SPR_PCMR6 (SPR_GRP7_PERF_CTR + 14) -#define CPU_OR1K_SPR_PCMR7 (SPR_GRP7_PERF_CTR + 15) - -/* Group8: Power management register */ -#define CPU_OR1K_SPR_PMR (SPR_GRP8_PWR_MNG + 0) - -/* Group9: PIC registers */ -#define CPU_OR1K_SPR_PICMR (SPR_GRP9_PIC + 0) -#define CPU_OR1K_SPR_PICSR (SPR_GRP9_PIC + 2) - -/* Group10: Tick Timer registers */ -#define CPU_OR1K_SPR_TTMR (SPR_GPR10_TICK_TMR + 0) -#define CPU_OR1K_SPR_TTCR (SPR_GPR10_TICK_TMR + 1) - - /* Shift amount macros for bits position in Supervision Register */ -#define CPU_OR1K_SPR_SR_SHAMT_SM (0) -#define CPU_OR1K_SPR_SR_SHAMT_TEE (1) -#define CPU_OR1K_SPR_SR_SHAMT_IEE (2) -#define CPU_OR1K_SPR_SR_SHAMT_DCE (3) -#define CPU_OR1K_SPR_SR_SHAMT_ICE (4) -#define CPU_OR1K_SPR_SR_SHAMT_DME (5) -#define CPU_OR1K_SPR_SR_SHAMT_IME (6) -#define CPU_OR1K_SPR_SR_SHAMT_LEE (7) -#define CPU_OR1K_SPR_SR_SHAMT_CE (8) -#define CPU_OR1K_SPR_SR_SHAMT_F (9) -#define CPU_OR1K_SPR_SR_SHAMT_CY (10) -#define CPU_OR1K_SPR_SR_SHAMT_OV (11) -#define CPU_OR1K_SPR_SR_SHAMT_OVE (12) -#define CPU_OR1K_SPR_SR_SHAMT_DSX (13) -#define CPU_OR1K_SPR_SR_SHAMT_EPH (14) -#define CPU_OR1K_SPR_SR_SHAMT_FO (15) -#define CPU_OR1K_SPR_SR_SHAMT_SUMRA (16) -#define CPU_OR1K_SPR_SR_SHAMT_CID (28) - -/* Supervision Mode Register. @see OpenRISC architecture manual*/ - - /* Supervisor Mode */ -#define CPU_OR1K_SPR_SR_SM (1 << CPU_OR1K_SPR_SR_SHAMT_SM) -/* Tick Timer Exception Enabled */ -#define CPU_OR1K_SPR_SR_TEE (1 << CPU_OR1K_SPR_SR_SHAMT_TEE) -/* Interrupt Exception Enabled */ -#define CPU_OR1K_SPR_SR_IEE (1 << CPU_OR1K_SPR_SR_SHAMT_IEE) -/* Data Cache Enable */ -#define CPU_OR1K_SPR_SR_DCE (1 << CPU_OR1K_SPR_SR_SHAMT_DCE) -/* Instruction Cache Enable */ -#define CPU_OR1K_SPR_SR_ICE (1 << CPU_OR1K_SPR_SR_SHAMT_ICE) -/* Data MMU Enable */ -#define CPU_OR1K_SPR_SR_DME (1 << CPU_OR1K_SPR_SR_SHAMT_DME) -/* Instruction MMU Enable */ -#define CPU_OR1K_SPR_SR_IME (1 << CPU_OR1K_SPR_SR_SHAMT_IME) -/* Little Endian Enable */ -#define CPU_OR1K_SPR_SR_LEE (1 << CPU_OR1K_SPR_SR_SHAMT_LEE) -/* CID Enable */ -#define CPU_OR1K_SPR_SR_CE (1 << CPU_OR1K_SPR_SR_SHAMT_CE) -/* Conditional branch flag */ -#define CPU_OR1K_SPR_SR_F (1 << CPU_OR1K_SPR_SR_SHAMT_F) -/* Carry flag */ -#define CPU_OR1K_SPR_SR_CY (1 << CPU_OR1K_SPR_SR_SHAMT_CY) -/* Overflow flag */ -#define CPU_OR1K_SPR_SR_OV (1 << CPU_OR1K_SPR_SR_SHAMT_OV) -/* Overflow flag Exception */ -#define CPU_OR1K_SPR_SR_OVE (1 << CPU_OR1K_SPR_SR_SHAMT_OVE) -/* Delay Slot Exception */ -#define CPU_OR1K_SPR_SR_DSX (1 << CPU_OR1K_SPR_SR_SHAMT_DSX) - /* Exception Prefix High */ -#define CPU_OR1K_SPR_SR_EPH (1 << CPU_OR1K_SPR_SR_SHAMT_EPH) -/* Fixed One */ -#define CPU_OR1K_SPR_SR_FO (1 << CPU_OR1K_SPR_SR_SHAMT_FO) -/* SPRs User Mode Read Access */ -#define CPU_OR1K_SPR_SR_SUMRA (1 << CPU_OR1K_SPR_SR_SHAMT_SUMRA) -/*Context ID (Fast Context Switching) */ -#define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) - -/* Tick timer configuration bits */ -#define CPU_OR1K_SPR_TTMR_SHAMT_IP 28 -#define CPU_OR1K_SPR_TTMR_SHAMT_IE 29 -#define CPU_OR1K_SPR_TTMR_SHAMT_MODE 30 - -#define CPU_OR1K_SPR_TTMR_TP_MASK (0x0FFFFFFF) -#define CPU_OR1K_SPR_TTMR_IP (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP) -#define CPU_OR1K_SPR_TTMR_IE (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE) -#define CPU_OR1K_SPR_TTMR_MODE_RESTART (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) -#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) -#define CPU_OR1K_SPR_TTMR_MODE_CONT (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) - -/* Power management register bits */ - -/* Shift amount macros for bit positions in Power Management register */ -#define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 -#define CPU_OR1K_SPR_PMR_SHAMT_DME 4 -#define CPU_OR1K_SPR_PMR_SHAMT_SME 5 -#define CPU_OR1K_SPR_PMR_SHAMT_DCGE 6 -#define CPU_OR1K_SPR_PMR_SHAMT_SUME 7 - -#define CPU_OR1K_SPR_PMR_SDF (0xF << CPU_OR1K_SPR_PMR_SHAMT_SDF) -#define CPU_OR1K_SPR_PMR_DME (1 << CPU_OR1K_SPR_PMR_SHAMT_DME) -#define CPU_OR1K_SPR_PMR_SME (1 << CPU_OR1K_SPR_PMR_SHAMT_SME) -#define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) -#define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) - -#ifndef ASM - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Supervision Mode registers definitions. - * - * @see OpenRISC architecture manual - revision 0. - */ -typedef enum { - OR1K_EXCEPTION_RESET = 1, - OR1K_EXCEPTION_BUS_ERR = 2, - OR1K_EXCEPTION_D_PF = 3, /* Data Page Fault */ - OR1K_EXCEPTION_I_PF = 4, /* Instruction Page Fault */ - OR1K_EXCEPTION_TICK_TIMER = 5, - OR1K_EXCEPTION_ALIGNMENT = 6, - OR1K_EXCEPTION_I_UNDEF= 7, /* Undefiend instruction */ - OR1K_EXCEPTION_IRQ = 8, /* External interrupt */ - OR1K_EXCPETION_D_TLB = 9, /* Data TLB miss */ - OR1K_EXCPETION_I_TLB = 10, /* Instruction TLB miss */ - OR1K_EXCPETION_RANGE = 11, /* Range exception */ - OR1K_EXCPETION_SYS_CALL = 12, - OR1K_EXCPETION_FP = 13, /* Floating point exception */ - OR1K_EXCPETION_TRAP = 14, /* Caused by l.trap instruction or by debug unit */ - OR1K_EXCPETION_RESERVED1 = 15, - OR1K_EXCPETION_RESERVED2 = 16, - OR1K_EXCPETION_RESERVED3 = 17, - MAX_EXCEPTIONS = 17, - OR1K_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff -} OR1K_Symbolic_exception_name; - -static inline uint32_t _OR1K_mfspr(uint32_t reg) -{ - uint32_t spr_value; - - asm volatile ( - "l.mfspr %0, %1, 0;\n\t" - : "=r" (spr_value) : "r" (reg)); - - return spr_value; -} - -static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) -{ - asm volatile ( - "l.mtspr %1, %0, 0;\n\t" - :: "r" (value), "r" (reg) - ); -} - -/** - * @brief The slow down feature takes advantage of the low-power - * dividers in external clock generation circuitry to enable full - * functionality, but at a lower frequency so that power consumption - * is reduced. @see OpenRISC architecture manual, power management section. - * - * @param[in] value is 4 bit value to be written in PMR[SDF]. - * A lower value specifies higher expected performance from the processor core. - * - */ -#define _OR1K_CPU_SlowDown(value) \ - _OR1K_mtspr(CPU_OR1K_SPR_PMR, (value & CPU_OR1K_SPR_PMR_SDF)) - - -#define _OR1K_CPU_Doze() \ - _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_DME) - - -#define _OR1K_CPU_Sleep() \ - _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) - -#define _OR1K_CPU_Suspend() \ - _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) - -static inline void _OR1K_Sync_mem( void ) -{ - asm volatile("l.msync"); -} - -static inline void _OR1K_Sync_pipeline( void ) -{ - asm volatile("l.psync"); -} - -/** - * @brief or1ksim simulator can be sent a halt signal from RTEMS to tell - * the running or1ksim process on the host machine to exit. The following - * implementation has no effect on QEMU or hardware implementation and will - * be treated as normal l.nop. - * - */ -#define _OR1KSIM_CPU_Halt() \ - asm volatile ("l.nop 0xc") - -#ifdef __cplusplus -} -#endif - -#else /* ASM */ - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_OR1K_UTILITY_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k.h b/cpukit/score/cpu/or1k/rtems/score/or1k.h deleted file mode 100644 index e1a3ddce42..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/or1k.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file rtems/score/or1k.h - */ - -/* - * This file contains information pertaining to the OR1K processor. - * - * COPYRIGHT (c) 2014 Hesham ALMatary - * - * Based on code with the following copyright... - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_OR1K_H -#define _RTEMS_SCORE_OR1K_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the OR1K family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - - /* - * Define the name of the CPU family and specific model. - */ - -#define CPU_NAME "OR1K" -#define CPU_MODEL_NAME "OR1200" - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_OR1K_H */ diff --git a/cpukit/score/cpu/or1k/rtems/score/types.h b/cpukit/score/cpu/or1k/rtems/score/types.h deleted file mode 100644 index 09790feb29..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/types.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * - * @brief OR1K Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2014 Hesham ALMatary - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - - #ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void or1k_isr; -typedef void ( *or1k_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/powerpc/Makefile.am b/cpukit/score/cpu/powerpc/Makefile.am index 7ed1f7996f..05ab2f480d 100644 --- a/cpukit/score/cpu/powerpc/Makefile.am +++ b/cpukit/score/cpu/powerpc/Makefile.am @@ -1,18 +1,5 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/powerpc.h -include_rtems_score_HEADERS += rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - -include_rtems_powerpcdir = $(includedir)/rtems/powerpc -include_rtems_powerpc_HEADERS = rtems/powerpc/registers.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c libscorecpu_a_SOURCES += ppc-context-volatile-clobber.S @@ -21,5 +8,5 @@ libscorecpu_a_SOURCES += ppc-isr-disable-mask.S libscorecpu_a_SOURCES += ppc-isr-vector-install.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/powerpc/headers.am b/cpukit/score/cpu/powerpc/headers.am new file mode 100644 index 0000000000..d8253e84f9 --- /dev/null +++ b/cpukit/score/cpu/powerpc/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_powerpcdir = $(includedir)/rtems/powerpc +include_rtems_powerpc_HEADERS = +include_rtems_powerpc_HEADERS += include/rtems/powerpc/registers.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/powerpc.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h b/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h new file mode 100644 index 0000000000..f0fdb3f33b --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/machine/elf_machdep.h @@ -0,0 +1,105 @@ +/* $NetBSD: elf_machdep.h,v 1.9 2011/01/15 10:00:07 matt Exp $ */ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF32_MACHDEP_ID_CASES \ + case EM_PPC: \ + break; + +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF64_MACHDEP_ID_CASES \ + case EM_PPC64: \ + break; + +#define ELF32_MACHDEP_ID EM_PPC +#define ELF64_MACHDEP_ID EM_PPC64 + +#ifdef _LP64 +#define ARCH_ELFSIZE 64 /* MD native binary size */ +#else +#define ARCH_ELFSIZE 32 /* MD native binary size */ +#endif + +/* Specify the value of _GLOBAL_OFFSET_TABLE_ */ +#define DT_PPC_GOT DT_LOPROC + +#define R_PPC_NONE 0 +#define R_PPC_32 1 +#define R_PPC_24 2 +#define R_PPC_16 3 +#define R_PPC_16_LO 4 +#define R_PPC_16_HI 5 /* R_PPC_ADDIS */ +#define R_PPC_16_HA 6 +#define R_PPC_14 7 +#define R_PPC_14_TAKEN 8 +#define R_PPC_14_NTAKEN 9 +#define R_PPC_REL24 10 /* R_PPC_BRANCH */ +#define R_PPC_REL14 11 +#define R_PPC_REL14_TAKEN 12 +#define R_PPC_REL14_NTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLT24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_U32 24 +#define R_PPC_U16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 +#define R_PPC_ADDR30 37 + +/* TLS relocations */ +#define R_PPC_TLS 67 + +#define R_PPC_DTPMOD32 68 +#define R_PPC_TPREL16 69 +#define R_PPC_TPREL16_LO 70 +#define R_PPC_TPREL16_HI 71 +#define R_PPC_TPREL16_HA 72 +#define R_PPC_TPREL32 73 +#define R_PPC_DTPREL16 74 +#define R_PPC_DTPREL16_LO 75 +#define R_PPC_DTPREL16_HI 76 +#define R_PPC_DTPREL16_HA 77 +#define R_PPC_DTPREL32 78 + +#define R_PPC_GOT_TLSGD16 79 +#define R_PPC_GOT_TLSGD16_LO 80 +#define R_PPC_GOT_TLSGD16_HI 81 +#define R_PPC_GOT_TLSGD16_HA 82 +#define R_PPC_GOT_TLSLD16 83 +#define R_PPC_GOT_TLSLD16_LO 84 +#define R_PPC_GOT_TLSLD16_HI 85 +#define R_PPC_GOT_TLSLD16_HA 86 + +#define R_PPC_GOT_TPREL16 87 +#define R_PPC_GOT_TPREL16_LO 88 +#define R_PPC_GOT_TPREL16_HI 89 +#define R_PPC_GOT_TPREL16_HA 90 +#define R_PPC_GOT_DTPREL16 91 +#define R_PPC_GOT_DTPREL16_LO 92 +#define R_PPC_GOT_DTPREL16_HI 93 +#define R_PPC_GOT_DTPREL16_HA 94 +#define R_PPC_TLSGD 95 +#define R_PPC_TLSLD 96 + +/* Used for the secure-plt PIC code sequences */ +#define R_PPC_REL16 249 +#define R_PPC_REL16_LO 250 +#define R_PPC_REL16_HI 251 +#define R_PPC_REL16_HA 252 + +#define R_TYPE(name) __CONCAT(R_PPC_,name) diff --git a/cpukit/score/cpu/powerpc/include/rtems/asm.h b/cpukit/score/cpu/powerpc/include/rtems/asm.h new file mode 100644 index 0000000000..2fddf56e6d --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/asm.h @@ -0,0 +1,310 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1995. + * i-cubed ltd. + * + * COPYRIGHT (c) 1994. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#ifndef __FLOAT_REGISTER_PREFIX__ +#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ +#endif + +#ifndef __PROC_LABEL_PREFIX__ +#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for procedure labels. */ + +#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* Use the right prefix for floating point registers. */ + +#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define r0 REG(0) +#define r1 REG(1) +#define r2 REG(2) +#define r3 REG(3) +#define r4 REG(4) +#define r5 REG(5) +#define r6 REG(6) +#define r7 REG(7) +#define r8 REG(8) +#define r9 REG(9) +#define r10 REG(10) +#define r11 REG(11) +#define r12 REG(12) +#define r13 REG(13) +#define r14 REG(14) +#define r15 REG(15) +#define r16 REG(16) +#define r17 REG(17) +#define r18 REG(18) +#define r19 REG(19) +#define r20 REG(20) +#define r21 REG(21) +#define r22 REG(22) +#define r23 REG(23) +#define r24 REG(24) +#define r25 REG(25) +#define r26 REG(26) +#define r27 REG(27) +#define r28 REG(28) +#define r29 REG(29) +#define r30 REG(30) +#define r31 REG(31) +#define f0 FREG(0) +#define f1 FREG(1) +#define f2 FREG(2) +#define f3 FREG(3) +#define f4 FREG(4) +#define f5 FREG(5) +#define f6 FREG(6) +#define f7 FREG(7) +#define f8 FREG(8) +#define f9 FREG(9) +#define f10 FREG(10) +#define f11 FREG(11) +#define f12 FREG(12) +#define f13 FREG(13) +#define f14 FREG(14) +#define f15 FREG(15) +#define f16 FREG(16) +#define f17 FREG(17) +#define f18 FREG(18) +#define f19 FREG(19) +#define f20 FREG(20) +#define f21 FREG(21) +#define f22 FREG(22) +#define f23 FREG(23) +#define f24 FREG(24) +#define f25 FREG(25) +#define f26 FREG(26) +#define f27 FREG(27) +#define f28 FREG(28) +#define f29 FREG(29) +#define f30 FREG(30) +#define f31 FREG(31) +#define v0 0 +#define v1 1 +#define v2 2 +#define v3 3 +#define v4 4 +#define v5 5 +#define v6 6 +#define v7 7 +#define v8 8 +#define v9 9 +#define v10 10 +#define v11 11 +#define v12 12 +#define v13 13 +#define v14 14 +#define v15 15 +#define v16 16 +#define v17 17 +#define v18 18 +#define v19 19 +#define v20 20 +#define v21 21 +#define v22 22 +#define v23 23 +#define v24 24 +#define v25 25 +#define v26 26 +#define v27 27 +#define v28 28 +#define v29 29 +#define v30 30 +#define v31 31 + +/* + * Some special purpose registers (SPRs). + */ +#define srr0 0x01a +#define srr1 0x01b +#define srr2 0x3de /* IBM 400 series only */ +#define srr3 0x3df /* IBM 400 series only */ +#define csrr0 58 /* Book E */ +#define csrr1 59 /* Book E */ +#define mcsrr0 570 /* e500 */ +#define mcsrr1 571 /* e500 */ +#define dsrr0 574 /* e200 */ +#define dsrr1 575 /* e200 */ + +#define sprg0 0x110 +#define sprg1 0x111 +#define sprg2 0x112 +#define sprg3 0x113 +#define sprg4 276 +#define sprg5 277 +#define sprg6 278 +#define sprg7 279 + +#define usprg0 256 + +#define dar 0x013 /* Data Address Register */ +#define dec 0x016 /* Decrementer Register */ + +#if defined(ppc403) || defined(ppc405) +/* the following SPR/DCR registers exist only in IBM 400 series */ +#define dear 0x3d5 +#define evpr 0x3d6 /* SPR: exception vector prefix register */ +#define iccr 0x3fb /* SPR: instruction cache control reg. */ +#define dccr 0x3fa /* SPR: data cache control reg. */ + +#if defined (ppc403) +#define exisr 0x040 /* DCR: external interrupt status register */ +#define exier 0x042 /* DCR: external interrupt enable register */ +#endif /* ppc403 */ +#if defined(ppc405) +#define exisr 0x0C0 /* DCR: external interrupt status register */ +#define exier 0x0C2 /* DCR: external interrupt enable register */ +#endif /* ppc405 */ + +#define br0 0x080 /* DCR: memory bank register 0 */ +#define br1 0x081 /* DCR: memory bank register 1 */ +#define br2 0x082 /* DCR: memory bank register 2 */ +#define br3 0x083 /* DCR: memory bank register 3 */ +#define br4 0x084 /* DCR: memory bank register 4 */ +#define br5 0x085 /* DCR: memory bank register 5 */ +#define br6 0x086 /* DCR: memory bank register 6 */ +#define br7 0x087 /* DCR: memory bank register 7 */ + +/* end of IBM400 series register definitions */ + +#elif defined(mpc555) +/* The following registers are for the MPC5xx */ +#define eie 0x050 /* External Interrupt Enable Register */ +#define eid 0x051 /* External Interrupt Disable Register */ +#define nri 0x052 /* Non-Recoverable Interrupt Register */ + +#elif defined(mpc860) || defined(mpc821) +/* The following registers are for the MPC8x0 */ +#define der 0x095 /* Debug Enable Register */ +#define ictrl 0x09E /* Instruction Support Control Register */ +#define immr 0x27E /* Internal Memory Map Register */ +/* end of MPC8x0 registers */ +#endif + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC_VAR(sym) .globl SYM (sym) +#define EXTERN_VAR(sym) .extern SYM (sym) +#define PUBLIC_PROC(sym) .globl PROC (sym) +#define EXTERN_PROC(sym) .extern PROC (sym) + +/* Other potentially assembler specific operations */ +#if PPC_ASM == PPC_ASM_ELF +#define ALIGN(n,p) .align p +#define DESCRIPTOR(x) \ + .section .descriptors,"aw"; \ + PUBLIC_VAR (x); \ +SYM (x):; \ + .long PROC (x); \ + .long s.got; \ + .long 0 + +#define EXT_SYM_REF(x) .long x +#define EXT_PROC_REF(x) .long x + +/* + * Define macros to handle section beginning and ends. + */ + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA .data +#define END_DATA +#define BEGIN_BSS .bss +#define END_BSS +#define END + +#else +#error "PPC_ASM_TYPE is not properly defined" +#endif +#ifndef PPC_ASM +#error "PPC_ASM_TYPE is not properly defined" +#endif + +#if defined(__powerpc64__) +#define PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop +#else +#define PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE +#endif + +#endif diff --git a/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h new file mode 100644 index 0000000000..4d9350324e --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h @@ -0,0 +1,774 @@ +/** + * @file + * + * @brief PowerPc MSR and Registers Access Definitions + * + * This file contains some powerpc MSR and registers access definitions. + */ + +/* + * COPYRIGHT (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Added MPC8260 Andy Dachs + * Surrey Satellite Technology Limited + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_POWERPC_REGISTERS_H +#define _RTEMS_POWERPC_REGISTERS_H + +/* Bit encodings for Machine State Register (MSR) */ +#define MSR_CM (1<<31) /* Computation mode */ +#define MSR_GS (1<<28) /* Guest state */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ +#define MSR_SPE (1<<25) /* SPE enable (e500) */ +#define MSR_AP (1<<25) /* Auxiliary processor available */ +#define MSR_APE (1<<19) /* APU exception enable */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait state enable (e500, 4xx) */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* BookE critical interrupt */ +#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ +#define MSR_EE (1<<15) /* External Interrupt enable */ +#define MSR_PR (1<<14) /* Supervisor/User privilege */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */ +#define MSR_DWE (1<<10) /* Debug wait enable (4xx) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* BookE debug exception */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_E300_CE (1<<7) /* e300 critical interrupt */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction MMU enable */ +#define MSR_DR (1<<4) /* Data MMU enable */ +#define MSR_IS (1<<5) /* Instruction address space */ +#define MSR_DS (1<<4) /* Data address space */ +#define MSR_PMM (1<<2) /* Performance monitor mark */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little-Endian enable */ + +/* Bit encodings for Hardware Implementation Register (HID0) + on PowerPC 603, 604, etc. processors (not 601). */ + +/* WARNING: HID0/HID1 are *truely* implementation dependent! + * you *cannot* rely on the same bits to be present, + * at the same place or even in the same register + * on different CPU familys. + * E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the + * on the 7450s. IFFT is XBSEN on 7450 and so on... + */ +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_TBEN (1<<26) /* 7455:this bit must be set + * and TBEN signal must be asserted + * to enable the time base and + * decrementer. + */ +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !! */ +#define HID0_7455_HIGH_BAT_EN (1<<23) + +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<15) /* Instruction Cache Enable */ +#define HID0_DCE (1<<14) /* Data Cache Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<12) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ +#define HID0_DCI (1<<10) /* Data Cache Invalidate */ +/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */ +#define HID0_7455_XBSEN (1<<8) +#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ +#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ +/* S.K. Feng 10/03, added for MPC7455 */ +#define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ +#define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ + +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ + +/* fpscr settings */ +#define FPSCR_FX (1<<31) +#define FPSCR_FEX (1<<30) + +#define _MACH_prep 1 +#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ +#define _MACH_chrp 4 /* chrp machine */ +#define _MACH_mbx 8 /* Motorola MBX board */ +#define _MACH_apus 16 /* amiga with phase5 powerup */ +#define _MACH_fads 32 /* Motorola FADS board */ + +/* see residual.h for these */ +#define _PREP_Motorola 0x01 /* motorola prep */ +#define _PREP_Firm 0x02 /* firmworks prep */ +#define _PREP_IBM 0x00 /* ibm prep */ +#define _PREP_Bull 0x03 /* bull prep */ + +/* these are arbitrary */ +#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ +#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ + +#define _GLOBAL(n)\ + .globl n;\ +n: + +#define TBRU 269 /* Time base Upper/Lower (Reading) */ +#define TBRL 268 +#define TBWU 285 /* Time base Upper/Lower (Writing) */ +#define TBWL 284 +#define PPC_XER 1 +#define PPC_LR 8 +#define PPC_CTR 9 +#define HID0 1008 /* Hardware Implementation 0 */ +#define HID1 1009 /* Hardware Implementation 1 */ +#define HID2 1011 /* Hardware Implementation 2 */ +#define DABR 1013 /* Data Access Breakpoint */ +#define PPC_PVR 287 /* Processor Version */ +#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ +#define IBAT0L 529 +#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ +#define IBAT1L 531 +#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ +#define IBAT2L 533 +#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ +#define IBAT3L 535 + +/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ +#define IBAT4U 560 /* Instruction BAT #4 Upper/Lower */ +#define IBAT4L 561 +#define IBAT5U 562 /* Instruction BAT #5 Upper/Lower */ +#define IBAT5L 563 +#define IBAT6U 564 /* Instruction BAT #6 Upper/Lower */ +#define IBAT6L 565 +#define IBAT7U 566 /* Instruction BAT #7 Upper/Lower */ +#define IBAT7L 567 + +#define DBAT0U 536 /* Data BAT #0 Upper/Lower */ +#define DBAT0L 537 +#define DBAT1U 538 /* Data BAT #1 Upper/Lower */ +#define DBAT1L 539 +#define DBAT2U 540 /* Data BAT #2 Upper/Lower */ +#define DBAT2L 541 +#define DBAT3U 542 /* Data BAT #3 Upper/Lower */ +#define DBAT3L 543 + +/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ +#define DBAT4U 568 /* Instruction BAT #4 Upper/Lower */ +#define DBAT4L 569 +#define DBAT5U 570 /* Instruction BAT #5 Upper/Lower */ +#define DBAT5L 571 +#define DBAT6U 572 /* Instruction BAT #6 Upper/Lower */ +#define DBAT6L 573 +#define DBAT7U 574 /* Instruction BAT #7 Upper/Lower */ +#define DBAT7L 575 + +#define DMISS 976 /* TLB Lookup/Refresh registers */ +#define DCMP 977 +#define HASH1 978 +#define HASH2 979 +#define IMISS 980 +#define ICMP 981 +#define PPC_RPA 982 +#define SDR1 25 /* MMU hash base register */ +#define PPC_DAR 19 /* Data Address Register */ +#define DEAR_BOOKE 61 +#define DEAR_405 981 +#define SPR0 272 /* Supervisor Private Registers */ +#define SPRG0 272 +#define SPR1 273 +#define SPRG1 273 +#define SPR2 274 +#define SPRG2 274 +#define SPR3 275 +#define SPRG3 275 +#define SPRG4 276 +#define SPRG5 277 +#define SPRG6 278 +#define SPRG7 279 +#define USPRG0 256 +#define DSISR 18 +#define SRR0 26 /* Saved Registers (exception) */ +#define SRR1 27 +#define IABR 1010 /* Instruction Address Breakpoint */ +#define PPC_DEC 22 /* Decrementer */ +#define PPC_EAR 282 /* External Address Register */ + +#define MSSCR0 1014 /* Memory Subsystem Control Register */ + +#define L2CR 1017 /* PPC 750 and 74xx L2 control register */ + +#define L2CR_L2E (1<<31) /* enable */ +#define L2CR_L2I (1<<21) /* global invalidate */ + +/* watch out L2IO and L2DO are different between 745x and 7400/7410 */ +/* Oddly, the following L2CR bit defintions in 745x + * is different from that of 7400 and 7410. + * Though not used in 7400 and 7410, it is appeded with _745x just + * to be clarified. + */ +#define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ +#define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ +#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) +#define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ + +#define L3CR 1018 /* PPC 7450/7455 L3 control register */ +#define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ +#define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ + +#define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) + +#define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ +#define L3CR_L3E 0x80000000 /* 0: L3 enable */ +#define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ +#define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ +#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ +#define L3SIZ_1M 0x00000000 +#define L3SIZ_2M 0x10000000 +#define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ +#define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ +#define L3CLK_60 0x00000000 /* core clock / 6 */ +#define L3CLK_20 0x01000000 /* / 2 */ +#define L3CLK_25 0x01800000 /* / 2.5 */ +#define L3CLK_30 0x02000000 /* / 3 */ +#define L3CLK_35 0x02800000 /* / 3.5 */ +#define L3CLK_40 0x03000000 /* / 4 */ +#define L3CLK_50 0x03800000 /* / 5 */ +#define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ +#define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ +#define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ +#define L3CKSP_2 0x00000000 /* 2 clocks */ +#define L3CKSP_3 0x00010000 /* 3 clocks */ +#define L3CKSP_4 0x00020000 /* 4 clocks */ +#define L3CKSP_5 0x00030000 /* 5 clocks */ +#define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ +#define L3PSP_0 0x00000000 /* 0 clocks */ +#define L3PSP_1 0x00002000 /* 1 clocks */ +#define L3PSP_2 0x00004000 /* 2 clocks */ +#define L3PSP_3 0x00006000 /* 3 clocks */ +#define L3PSP_4 0x00008000 /* 4 clocks */ +#define L3PSP_5 0x0000a000 /* 5 clocks */ +#define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ +#define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ +#define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig +lidate */ +#define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ +#define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ +#define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ +#define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ +#define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ +#define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ +#define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ +#define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ + +#define THRM1 1020 +#define THRM2 1021 +#define THRM3 1022 +#define THRM1_TIN (1<<(31-0)) +#define THRM1_TIV (1<<(31-1)) +#define THRM1_THRES (0x7f<<(31-8)) +#define THRM1_TID (1<<(31-29)) +#define THRM1_TIE (1<<(31-30)) +#define THRM1_V (1<<(31-31)) +#define THRM3_SITV (0x1fff << (31-30)) +#define THRM3_E (1<<(31-31)) + +/* Segment Registers */ +#define PPC_SR0 0 +#define PPC_SR1 1 +#define PPC_SR2 2 +#define PPC_SR3 3 +#define PPC_SR4 4 +#define PPC_SR5 5 +#define PPC_SR6 6 +#define PPC_SR7 7 +#define PPC_SR8 8 +#define PPC_SR9 9 +#define PPC_SR10 10 +#define PPC_SR11 11 +#define PPC_SR12 12 +#define PPC_SR13 13 +#define PPC_SR14 14 +#define PPC_SR15 15 + +#define BOOKE_DECAR 54 + +#define PPC405_MCSR 0x23C +#define PPC405_ESR 0x3D4 +#define PPC405_DEAR 0x3D5 +#define BOOKE_DEAR 61 + +#define PPC405_TSR 0x3D8 +#define BOOKE_TSR 336 +#define BOOKE_TSR_ENW (1<<31) +#define BOOKE_TSR_WIS (1<<30) +#define BOOKE_TSR_DIS (1<<27) +#define BOOKE_TSR_FIS (1<<26) + +#define PPC405_TCR 0x3DA +#define BOOKE_TCR 340 +#define BOOKE_TCR_WP(x) (((x)&3)<<30) +#define BOOKE_TCR_WP_MASK (3<<30) +#define BOOKE_TCR_WRC(x) (((x)&3)<<28) +#define BOOKE_TCR_WRC_MASK (3<<28) +#define BOOKE_TCR_WIE (1<<27) +#define BOOKE_TCR_DIE (1<<26) +#define BOOKE_TCR_FP(x) (((x)&3)<<24) +#define BOOKE_TCR_FIE (1<<23) +#define BOOKE_TCR_ARE (1<<22) +#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17) +#define BOOKE_TCR_WPEXT_MASK (0xf<<17) +#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13) +#define BOOKE_TCR_FPEXT_MASK (0xf<<13) + +#define BOOKE_PID 48 /* Process ID */ +#define BOOKE_CSRR0 58 /* Critical Save/Restore Register 0 */ +#define BOOKE_CSRR1 59 /* Critical Save/Restore Register 1 */ +#define BOOKE_ESR 62 /* Exception Syndrome Register */ +#define BOOKE_IVPR 63 /* Interrupt Vector Prefix Register */ +#define BOOKE_SPRG4_W 260 /* Special Purpose Register General 4 (WO) */ +#define BOOKE_SPRG5_W 261 /* Special Purpose Register General 5 (WO) */ +#define BOOKE_SPRG6_W 262 /* Special Purpose Register General 6 (WO) */ +#define BOOKE_SPRG7_W 263 /* Special Purpose Register General 7 (WO) */ +#define BOOKE_PIR 286 /* Processor ID Register */ +#define BOOKE_DBSR 304 /* Debug Status Register */ + +#define BOOKE_EPCR 307 /* Embedded Processor Control Register */ +#define BOOKE_EPCR_EXTGS (1 << 31) +#define BOOKE_EPCR_DTLBGS (1 << 30) +#define BOOKE_EPCR_ITLBGS (1 << 29) +#define BOOKE_EPCR_DSIGS (1 << 28) +#define BOOKE_EPCR_ISIGS (1 << 27) +#define BOOKE_EPCR_DUVD (1 << 26) +#define BOOKE_EPCR_ICM (1 << 25) +#define BOOKE_EPCR_GICM (1 << 24) +#define BOOKE_EPCR_DGTMI (1 << 23) +#define BOOKE_EPCR_DMIUH (1 << 22) +#define BOOKE_EPCR_PMGS (1 << 21) + +#define BOOKE_DBCR0 308 /* Debug Control Register 0 */ +#define BOOKE_DBCR1 309 /* Debug Control Register 1 */ +#define BOOKE_DBCR2 310 /* Debug Control Register 2 */ +#define BOOKE_IAC1 312 /* Instruction Address Compare 1 */ +#define BOOKE_IAC2 313 /* Instruction Address Compare 2 */ +#define BOOKE_IAC3 314 /* Instruction Address Compare 3 */ +#define BOOKE_IAC4 315 /* Instruction Address Compare 4 */ +#define BOOKE_DAC1 316 /* Data Address Compare 1 */ +#define BOOKE_DAC2 317 /* Data Address Compare 2 */ +#define BOOKE_DVC1 318 /* Data Value Compare 1 */ +#define BOOKE_DVC2 319 /* Data Value Compare 2 */ +#define BOOKE_GSRR0 378 /* Guest Save/Restore Register 0 */ +#define BOOKE_GSRR1 379 /* Guest Save/Restore Register 1 */ +#define BOOKE_GEPR 380 /* Guest External Proxy Register */ +#define BOOKE_GDEAR 381 /* Guest Data Exception Address Register */ +#define BOOKE_GPIR 382 /* Guest Processor ID Register */ +#define BOOKE_GESR 383 /* Guest Exception Syndrome Register */ +#define BOOKE_IVOR0 400 /* Interrupt Vector Offset Register 0 */ +#define BOOKE_IVOR1 401 /* Interrupt Vector Offset Register 1 */ +#define BOOKE_IVOR2 402 /* Interrupt Vector Offset Register 2 */ +#define BOOKE_IVOR3 403 /* Interrupt Vector Offset Register 3 */ +#define BOOKE_IVOR4 404 /* Interrupt Vector Offset Register 4 */ +#define BOOKE_IVOR5 405 /* Interrupt Vector Offset Register 5 */ +#define BOOKE_IVOR6 406 /* Interrupt Vector Offset Register 6 */ +#define BOOKE_IVOR7 407 /* Interrupt Vector Offset Register 7 */ +#define BOOKE_IVOR8 408 /* Interrupt Vector Offset Register 8 */ +#define BOOKE_IVOR9 409 /* Interrupt Vector Offset Register 9 */ +#define BOOKE_IVOR10 410 /* Interrupt Vector Offset Register 10 */ +#define BOOKE_IVOR11 411 /* Interrupt Vector Offset Register 11 */ +#define BOOKE_IVOR12 412 /* Interrupt Vector Offset Register 12 */ +#define BOOKE_IVOR13 413 /* Interrupt Vector Offset Register 13 */ +#define BOOKE_IVOR14 414 /* Interrupt Vector Offset Register 14 */ +#define BOOKE_IVOR15 415 /* Interrupt Vector Offset Register 15 */ +#define BOOKE_IVOR42 436 /* Interrupt Vector Offset Register 42 */ +#define BOOKE_IVOR32 528 /* Interrupt Vector Offset Register 32 */ +#define BOOKE_IVOR33 529 /* Interrupt Vector Offset Register 33 */ +#define BOOKE_IVOR34 530 /* Interrupt Vector Offset Register 34 */ +#define BOOKE_IVOR35 531 /* Interrupt Vector Offset Register 35 */ +#define BOOKE_IVOR36 532 /* Interrupt Vector Offset Register 36 */ +#define BOOKE_IVOR37 533 /* Interrupt Vector Offset Register 37 */ +#define BOOKE_IVOR38 432 /* Interrupt Vector Offset Register 38 */ +#define BOOKE_IVOR39 433 /* Interrupt Vector Offset Register 39 */ +#define BOOKE_IVOR40 434 /* Interrupt Vector Offset Register 40 */ +#define BOOKE_IVOR41 435 /* Interrupt Vector Offset Register 41 */ +#define BOOKE_GIVOR2 440 /* Guest Interrupt Vector Offset Register 2 */ +#define BOOKE_GIVOR3 441 /* Guest Interrupt Vector Offset Register 3 */ +#define BOOKE_GIVOR4 442 /* Guest Interrupt Vector Offset Register 4 */ +#define BOOKE_GIVOR8 443 /* Guest Interrupt Vector Offset Register 8 */ +#define BOOKE_GIVOR13 444 /* Guest Interrupt Vector Offset Register 13 */ +#define BOOKE_GIVOR14 445 /* Guest Interrupt Vector Offset Register 14 */ +#define BOOKE_GIVPR 446 /* Guest Interrupt Vector Prefix Register */ +#define BOOKE_MCSRR0 570 /* Machine Check Save/Restore Register 0 */ +#define BOOKE_MCSRR1 571 /* Machine Check Save/Restore Register 1 */ +#define BOOKE_MCSR 572 /* Machine Check Status Register */ +#define BOOKE_DSRR0 574 /* Debug Save/Restore Register 0 */ +#define BOOKE_DSRR1 575 /* Debug Save/Restore Register 1 */ + +#define PPC440_INV0 880 /* Instruction Cache Normal Victim 0 */ +#define PPC440_INV1 881 /* Instruction Cache Normal Victim 1 */ +#define PPC440_INV2 882 /* Instruction Cache Normal Victim 2 */ +#define PPC440_INV3 883 /* Instruction Cache Normal Victim 3 */ +#define PPC440_ITV0 884 /* Instruction Cache Transient Victim 0 */ +#define PPC440_ITV1 885 /* Instruction Cache Transient Victim 1 */ +#define PPC440_ITV2 886 /* Instruction Cache Transient Victim 2 */ +#define PPC440_ITV3 887 /* Instruction Cache Transient Victim 3 */ +#define PPC440_CCR1 888 /* Core Configuration Register 1 */ +#define PPC440_DNV0 912 /* Data Cache Normal Victim 0 */ +#define PPC440_DNV1 913 /* Data Cache Normal Victim 1 */ +#define PPC440_DNV2 914 /* Data Cache Normal Victim 2 */ +#define PPC440_DNV3 915 /* Data Cache Normal Victim 3 */ +#define PPC440_DTV0 916 /* Data Cache Transient Victim 0 */ +#define PPC440_DTV1 917 /* Data Cache Transient Victim 1 */ +#define PPC440_DTV2 918 /* Data Cache Transient Victim 2 */ +#define PPC440_DTV3 919 /* Data Cache Transient Victim 3 */ +#define PPC440_DVLIM 920 /* Data Cache Victim Limit */ +#define PPC440_IVLIM 921 /* Instruction Cache Victim Limit */ +#define PPC440_RSTCFG 923 /* Reset Configuration */ +#define PPC440_DCDBTRL 924 /* Data Cache Debug Tag Register Low */ +#define PPC440_DCDBTRH 925 /* Data Cache Debug Tag Register High */ +#define PPC440_ICDBTRL 926 /* Instruction Cache Debug Tag Register Low */ +#define PPC440_ICDBTRH 927 /* Instruction Cache Debug Tag Register High */ +#define PPC440_MMUCR 946 /* Memory Management Unit Control Register */ +#define PPC440_CCR0 947 /* Core Configuration Register 0 */ +#define PPC440_ICDBDR 979 /* Instruction Cache Debug Data Register */ +#define PPC440_DBDR 1011 /* Debug Data Register */ + +#define PPC440_TLB0_EPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Etended Page Number */ +#define PPC440_TLB0_EPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1)) +#define PPC440_TLB0_V ( 1 << (31-22)) /* Entry valid */ +#define PPC440_TLB0_TS ( 1 << (31-23)) /* Translation space */ +#define PPC440_TLB0_TSIZE(n) ( (0xf & (n)) << (31-27)) /* Page size */ +#define PPC440_TLB0_TSIZE_GET(n) ( ((n) >> (31-27)) & 0xf) +#define PPC440_TLB0_TPAR(n) ( (0xf & (n)) << (31-31)) /* Tag Parity */ +#define PPC440_TLB0_TPAR_GET(n) ( ((n) >> (31-31)) & 0xf) + +#define PPC440_PID_TID(n) ( (0xff & (n)) << (31-31)) /* Translation ID */ +#define PPC440_PID_TID_GET(n) ( ((n) >> (31-31)) & 0xff) + +#define PPC440_TLB1_RPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Real Page Number */ +#define PPC440_TLB1_RPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1)) +#define PPC440_TLB1_PAR1(n) ( (0x3 & (n)) << (31-23)) /* Parity for TLB word 1 */ +#define PPC440_TLB1_PAR1_GET(n) ( ((n) >> (31-23)) & 0x3) +#define PPC440_TLB1_ERPN(n) ( (0xf & (n)) << (31-31)) /* Extended Real Page No. */ +#define PPC440_TLB1_ERPN_GET(n) ( ((n) >> (31-31)) & 0xf) + +#define PPC440_TLB2_PAR2(n) ( (0x3 & (n)) << (31- 1)) /* Parity for TLB word 2 */ +#define PPC440_TLB2_PAR2_GET(n) ( ((n) >> (31- 1)) & 0x3) +#define PPC440_TLB2_U0 ( 1 << (31-16)) /* User attr. 0 */ +#define PPC440_TLB2_U1 ( 1 << (31-17)) /* User attr. 1 */ +#define PPC440_TLB2_U2 ( 1 << (31-18)) /* User attr. 2 */ +#define PPC440_TLB2_U3 ( 1 << (31-19)) /* User attr. 3 */ +#define PPC440_TLB2_W ( 1 << (31-20)) /* Write-through */ +#define PPC440_TLB2_I ( 1 << (31-21)) /* Cache-inhibited */ +#define PPC440_TLB2_M ( 1 << (31-22)) /* Memory-coherence req. */ +#define PPC440_TLB2_G ( 1 << (31-23)) /* Guarded */ +#define PPC440_TLB2_E ( 1 << (31-24)) /* Little-endian */ +#define PPC440_TLB2_UX ( 1 << (31-26)) /* User exec. */ +#define PPC440_TLB2_UW ( 1 << (31-27)) /* User write */ +#define PPC440_TLB2_UR ( 1 << (31-28)) /* User read */ +#define PPC440_TLB2_SX ( 1 << (31-29)) /* Super exec. */ +#define PPC440_TLB2_SW ( 1 << (31-30)) /* Super write */ +#define PPC440_TLB2_SR ( 1 << (31-31)) /* Super read */ + +#define PPC440_TLB2_ATTR(x) ( ((x) & 0x1ff) << 7 ) +#define PPC440_TLB2_ATTR_GET(x) ( ((x) >> 7) & 0x1ff ) + +#define PPC440_TLB2_PERM(n) ( (n) & 0x3f ) +#define PPC440_TLB2_PERM_GET(n) ( (n) & 0x3f ) + +/* Freescale Book E Implementation Standards (EIS): Branch Operations */ + +#define FSL_EIS_BUCSR 1013 +#define FSL_EIS_BUCSR_STAC_EN (1 << (63 - 39)) +#define FSL_EIS_BUCSR_LS_EN (1 << (63 - 41)) +#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54)) +#define FSL_EIS_BUCSR_BALLOC_ALL (0x0 << (63 - 59)) +#define FSL_EIS_BUCSR_BALLOC_FORWARD (0x1 << (63 - 59)) +#define FSL_EIS_BUCSR_BALLOC_BACKWARD (0x2 << (63 - 59)) +#define FSL_EIS_BUCSR_BALLOC_NONE (0x3 << (63 - 59)) +#define FSL_EIS_BUCSR_BPRED_TAKEN (0x0 << (63 - 61)) +#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_FORWARD (0x1 << (63 - 62)) +#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_BACKWARD (0x2 << (63 - 62)) +#define FSL_EIS_BUCSR_BPRED_NOT_TAKEN (0x3 << (63 - 62)) +#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63)) + +/* Freescale Book E Implementation Standards (EIS): Hardware Implementation-Dependent Registers */ + +#define FSL_EIS_SVR 1023 + +/* Freescale Book E Implementation Standards (EIS): Thread Management and Control Registers */ + +#define FSL_EIS_TENSR 437 +#define FSL_EIS_TENS 438 +#define FSL_EIS_TENC 439 +#define FSL_EIS_PPR32 898 + +/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */ + +#define FSL_EIS_MAS0 624 +#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35)) +#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47)) +#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf) +#define FSL_EIS_MAS0_NV (1 << (63 - 63)) + +#define FSL_EIS_MAS1 625 +#define FSL_EIS_MAS1_V (1 << (63 - 32)) +#define FSL_EIS_MAS1_IPROT (1 << (63 - 33)) +#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47)) +#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff) +#define FSL_EIS_MAS1_TS (1 << (63 - 51)) +#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55)) +#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf) + +#define FSL_EIS_MAS2 626 +#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51)) +#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff) +#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12) +#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12) +#define FSL_EIS_MAS2_X0 (1 << (63 - 57)) +#define FSL_EIS_MAS2_X1 (1 << (63 - 58)) +#define FSL_EIS_MAS2_W (1 << (63 - 59)) +#define FSL_EIS_MAS2_I (1 << (63 - 60)) +#define FSL_EIS_MAS2_M (1 << (63 - 61)) +#define FSL_EIS_MAS2_G (1 << (63 - 62)) +#define FSL_EIS_MAS2_E (1 << (63 - 63)) +#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f) +#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f) + +#define FSL_EIS_MAS3 627 +#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51)) +#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff) +#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12) +#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12) +#define FSL_EIS_MAS3_U0 (1 << (63 - 54)) +#define FSL_EIS_MAS3_U1 (1 << (63 - 55)) +#define FSL_EIS_MAS3_U2 (1 << (63 - 56)) +#define FSL_EIS_MAS3_U3 (1 << (63 - 57)) +#define FSL_EIS_MAS3_UX (1 << (63 - 58)) +#define FSL_EIS_MAS3_SX (1 << (63 - 59)) +#define FSL_EIS_MAS3_UW (1 << (63 - 60)) +#define FSL_EIS_MAS3_SW (1 << (63 - 61)) +#define FSL_EIS_MAS3_UR (1 << (63 - 62)) +#define FSL_EIS_MAS3_SR (1 << (63 - 63)) +#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff) +#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff) + +#define FSL_EIS_MAS4 628 +#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35)) +#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47)) +#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55)) +#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0 +#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1 +#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W +#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I +#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M +#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G +#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E + +#define FSL_EIS_MAS5 629 + +#define FSL_EIS_MAS6 630 +#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55)) +#define FSL_EIS_MAS6_SAS (1 << (63 - 63)) + +#define FSL_EIS_MAS7 944 + +#define FSL_EIS_MAS8 341 + +#define FSL_EIS_MMUCFG 1015 +#define FSL_EIS_MMUCSR0 1012 +#define FSL_EIS_PID0 48 +#define FSL_EIS_PID1 633 +#define FSL_EIS_PID2 634 +#define FSL_EIS_TLB0CFG 688 +#define FSL_EIS_TLB1CFG 689 + +/* Freescale Book E Implementation Standards (EIS): L1 Cache */ + +#define FSL_EIS_L1CFG0 515 +#define FSL_EIS_L1CFG1 516 +#define FSL_EIS_L1CSR0 1010 +#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62)) +#define FSL_EIS_L1CSR1 1011 +#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62)) + +/* Freescale Book E Implementation Standards (EIS): L2 Cache */ + +#define FSL_EIS_L2CFG0 519 +#define FSL_EIS_L2CSR0 1017 +#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42)) +#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52)) +#define FSL_EIS_L2CSR1 1018 + +/* Freescale Book E Implementation Standards (EIS): Timer */ + +#define FSL_EIS_ATBL 526 +#define FSL_EIS_ATBU 527 + +/* Freescale Book E Implementation Standards (EIS): Interrupt */ + +#define FSL_EIS_MCAR 573 +#define FSL_EIS_DSRR0 574 +#define FSL_EIS_DSRR1 575 +#define FSL_EIS_EPR 702 + +/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */ + +#define FSL_EIS_SPEFSCR 512 + +/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */ + +#define FSL_EIS_SPRG8 604 +#define FSL_EIS_SPRG9 605 + +/* Freescale Book E Implementation Standards (EIS): Debug */ + +#define FSL_EIS_DBCR3 561 +#define FSL_EIS_DBCR4 563 +#define FSL_EIS_DBCR5 564 +#define FSL_EIS_DBCR6 603 +#define FSL_EIS_DBCNT 562 + +/** + * @brief Default value for the interrupt disable mask. + * + * The interrupt disable mask is stored in the global symbol + * _PPC_INTERRUPT_DISABLE_MASK. + */ +#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE + +#ifndef ASM + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define _CPU_MSR_GET( _msr_value ) \ + do { \ + _msr_value = 0; \ + __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ + } while (0) + +#define _CPU_MSR_SET( _msr_value ) \ +{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } + +/** + * @brief A global symbol used to disable interrupts in the MSR. + * + * A one bit means that this bit should be cleared. + */ +extern char _PPC_INTERRUPT_DISABLE_MASK[]; + +static inline uint32_t ppc_interrupt_get_disable_mask( void ) +{ + return (uint32_t) (uintptr_t) _PPC_INTERRUPT_DISABLE_MASK; +} + +static inline uint32_t ppc_interrupt_disable( void ) +{ + uint32_t level; + +#if defined(__PPC_CPU_E6500__) + __asm__ volatile ( + "mfmsr %0;" + "wrteei 0" + : "=r" (level) + ); +#else + uint32_t mask; + + __asm__ volatile ( + "mfmsr %0;" + "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;" + "ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;" + "andc %1, %0, %1;" + "mtmsr %1" + : "=r" (level), "=r" (mask) + ); +#endif + + return level; +} + +static inline void ppc_interrupt_enable( uint32_t level ) +{ +#if defined(__PPC_CPU_E6500__) + __asm__ volatile ( + "wrtee %0" + : + : "r" (level) + ); +#else + __asm__ volatile ( + "mtmsr %0" + : + : "r" (level) + ); +#endif +} + +static inline void ppc_interrupt_flash( uint32_t level ) +{ + uint32_t current_level; + + __asm__ volatile ( + "mfmsr %0;" + "mtmsr %1;" + "mtmsr %0" + : "=&r" (current_level) + : "r" (level) + ); +} + +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + _isr_cookie = ppc_interrupt_disable(); \ + } while (0) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _isr_cookie is not modified. + */ + +#define _CPU_ISR_Enable( _isr_cookie ) \ + ppc_interrupt_enable(_isr_cookie) + +/* + * This temporarily restores the interrupt to _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _isr_cookie is not + * modified. + * + * NOTE: The version being used is not very optimized but it does + * not trip a problem in gcc where the disable mask does not + * get loaded. Check this for future (post 10/97 gcc versions. + */ + +#define _CPU_ISR_Flash( _isr_cookie ) \ + ppc_interrupt_flash(_isr_cookie) + +/* end of ISR handler macros */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* _RTEMS_POWERPC_REGISTERS_H */ diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h new file mode 100644 index 0000000000..8c0f200641 --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h @@ -0,0 +1,1257 @@ +/** + * @file + * + * @brief PowerPC CPU Department Source + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * COPYRIGHT (c) 1995 i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Copyright (c) 2001 Andy Dachs . + * + * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). + * + * Copyright (c) 2010, 2017 embedded brains GmbH. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#include +#include +#include + +#ifndef ASM + #include /* for memset() */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* conditional compilation parameters */ + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +#define CPU_STACK_GROWS_UP FALSE + +#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "PPC_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if ( PPC_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#define CPU_SOFTWARE_FP FALSE +#else +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * PowerPC Note: It appears the GCC can implicitly generate FPU + * and Altivec instructions when you least expect them. So make + * all tasks floating point. + */ + +#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +#ifndef __SPE__ + #define PPC_GPR_TYPE uintptr_t + #if defined(__powerpc64__) + #define PPC_GPR_SIZE 8 + #define PPC_GPR_LOAD ld + #define PPC_GPR_STORE std + #else + #define PPC_GPR_SIZE 4 + #define PPC_GPR_LOAD lwz + #define PPC_GPR_STORE stw + #endif +#else + #define PPC_GPR_TYPE uint64_t + #define PPC_GPR_SIZE 8 + #define PPC_GPR_LOAD evldd + #define PPC_GPR_STORE evstdd +#endif + +#if defined(__powerpc64__) + #define PPC_REG_SIZE 8 + #define PPC_REG_LOAD ld + #define PPC_REG_STORE std + #define PPC_REG_STORE_UPDATE stdu + #define PPC_REG_CMP cmpd +#else + #define PPC_REG_SIZE 4 + #define PPC_REG_LOAD lwz + #define PPC_REG_STORE stw + #define PPC_REG_STORE_UPDATE stwu + #define PPC_REG_CMP cmpw +#endif + +#ifndef ASM + +/* + * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according + * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - + * Linux and Embedded") + */ +typedef struct { + uint32_t msr; + uint32_t cr; + uintptr_t gpr1; + uintptr_t lr; + PPC_GPR_TYPE gpr14; + PPC_GPR_TYPE gpr15; + PPC_GPR_TYPE gpr16; + PPC_GPR_TYPE gpr17; + PPC_GPR_TYPE gpr18; + PPC_GPR_TYPE gpr19; + PPC_GPR_TYPE gpr20; + PPC_GPR_TYPE gpr21; + PPC_GPR_TYPE gpr22; + PPC_GPR_TYPE gpr23; + PPC_GPR_TYPE gpr24; + PPC_GPR_TYPE gpr25; + PPC_GPR_TYPE gpr26; + PPC_GPR_TYPE gpr27; + PPC_GPR_TYPE gpr28; + PPC_GPR_TYPE gpr29; + PPC_GPR_TYPE gpr30; + PPC_GPR_TYPE gpr31; + uint32_t isr_dispatch_disable; + uint32_t reserved_for_alignment; + #if defined(PPC_MULTILIB_ALTIVEC) + uint8_t v20[16]; + uint8_t v21[16]; + uint8_t v22[16]; + uint8_t v23[16]; + uint8_t v24[16]; + uint8_t v25[16]; + uint8_t v26[16]; + uint8_t v27[16]; + uint8_t v28[16]; + uint8_t v29[16]; + uint8_t v30[16]; + uint8_t v31[16]; + uint32_t vrsave; + #elif defined(__ALTIVEC__) + /* + * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave + * and padding to ensure cache-alignment. Unfortunately, we can't verify + * the cache line size here in the cpukit but altivec support code will + * produce an error if this is ever different from 32 bytes. + * + * Note: it is the BSP/CPU-support's responsibility to save/restore + * volatile vregs across interrupts and exceptions. + */ + uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; + #endif + #if defined(PPC_MULTILIB_FPU) + double f14; + double f15; + double f16; + double f17; + double f18; + double f19; + double f20; + double f21; + double f22; + double f23; + double f24; + double f25; + double f26; + double f27; + double f28; + double f29; + double f30; + double f31; + #endif + /* + * The following items are at the structure end, so that we can use dcbz for + * the previous items to optimize the context switch. We must not set the + * following items to zero via the dcbz. + */ + uintptr_t tp; + #if defined(RTEMS_SMP) + volatile uint32_t is_executing; + #endif +} ppc_context; + +typedef struct { + uint8_t context [ + PPC_DEFAULT_CACHE_LINE_SIZE + + sizeof(ppc_context) + + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 + ? 0 + : PPC_DEFAULT_CACHE_LINE_SIZE + - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) + ]; +} Context_Control; + +static inline ppc_context *ppc_get_context( const Context_Control *context ) +{ + uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; + uintptr_t mask = clsz - 1; + uintptr_t addr = (uintptr_t) context; + + return (ppc_context *) ((addr & ~mask) + clsz); +} + +#define _CPU_Context_Get_SP( _context ) \ + ppc_get_context(_context)->gpr1 + +#ifdef RTEMS_SMP + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + { + return ppc_get_context(context)->is_executing; + } + + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + ppc_get_context(context)->is_executing = is_executing; + } +#endif +#endif /* ASM */ + +#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE) +#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) +#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8) +#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8) + +#define PPC_CONTEXT_GPR_OFFSET( gpr ) \ + (((gpr) - 14) * PPC_GPR_SIZE + \ + PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE) + +#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) +#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) +#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) +#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) +#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) +#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) +#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) +#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) +#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) +#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) +#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) +#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) +#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) +#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) +#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) +#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) +#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) +#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) +#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 ) + +#ifdef PPC_MULTILIB_ALTIVEC + #define PPC_CONTEXT_OFFSET_V( v ) \ + ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8) + #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) + #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) + #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) + #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) + #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) + #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) + #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) + #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) + #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) + #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) + #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) + #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) + #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) + #define PPC_CONTEXT_OFFSET_F( f ) \ + ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 ) +#else + #define PPC_CONTEXT_OFFSET_F( f ) \ + ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 ) +#endif + +#ifdef PPC_MULTILIB_FPU + #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) + #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) + #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) + #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) + #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) + #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) + #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) + #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) + #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) + #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) + #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) + #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) + #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) + #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) + #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) + #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) + #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) + #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) +#endif + +#if defined(PPC_MULTILIB_FPU) + #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) +#elif defined(PPC_MULTILIB_ALTIVEC) + #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) +#elif defined(__ALTIVEC__) + #define PPC_CONTEXT_VOLATILE_SIZE \ + (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \ + + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE) +#else + #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8) +#endif + +#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE + +#ifdef RTEMS_SMP + #define PPC_CONTEXT_OFFSET_IS_EXECUTING \ + (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE) +#endif + +#ifndef ASM +typedef struct { +#if (PPC_HAS_FPU == 1) + /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over + * procedure calls. However, this would mean that the interrupt + * frame had to hold f0-f13, and the fpscr. And as the majority + * of tasks will not have an FP context, we will save the whole + * context here. + */ +#if (PPC_HAS_DOUBLE == 1) + double f[32]; + uint64_t fpscr; +#else + float f[32]; + uint32_t fpscr; +#endif +#endif /* (PPC_HAS_FPU == 1) */ +} Context_Control_fp; + +#endif /* ASM */ + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * PowerPC Specific Information: + * + * The PowerPC and x86 were the first to use the PIC interrupt model. + * They do not use the simple vectored interrupt model. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Note, however that compilers may use floating point registers/ + * instructions for optimization or they may save/restore FP registers + * on the stack. You must not use deferred switching in these cases + * and on the PowerPC attempting to do so will raise a "FP unavailable" + * exception. + */ +/* + * ACB Note: This could make debugging tricky.. + */ + +/* conservative setting (FALSE); probably doesn't affect performance too much */ +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Processor defined structures required for cpukit/score. + */ + +#ifndef ASM + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ + +#endif /* ndef ASM */ + +/* + * This defines the number of levels and the mask used to pick those + * bits out of a thread mode. + */ + +#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * (Optional) # of bytes for libmisc/stackchk to check + * If not specifed, then it defaults to something reasonable + * for most architectures. + */ + +#define CPU_STACK_CHECK_PATTERN_INITIALIZER \ + { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ + 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 } + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. Note that + * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level + * being maintained (e.g. watchdog queues). + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * ISR handler macros + */ + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _isr_cookie. + */ + +#ifndef ASM + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & MSR_EE ) != 0; +} + +static inline uint32_t _CPU_ISR_Get_level( void ) +{ + register unsigned int msr; + _CPU_MSR_GET(msr); + if (msr & MSR_EE) return 0; + else return 1; +} + +static inline void _CPU_ISR_Set_level( uint32_t level ) +{ + register unsigned int msr; + _CPU_MSR_GET(msr); + if (!(level & CPU_MODES_INTERRUPT_MASK)) { + msr |= ppc_interrupt_get_disable_mask(); + } + else { + msr &= ~ppc_interrupt_get_disable_mask(); + } + _CPU_MSR_SET(msr); +} + +#endif /* ASM */ + +#define _CPU_Fatal_halt( _source, _error ) \ + do { \ + ppc_interrupt_disable(); \ + __asm__ volatile ( \ + "mr 3, %0\n" \ + "mr 4, %1\n" \ + "1:\n" \ + "b 1b\n" \ + : \ + : "r" (_source), "r" (_error) \ + : "memory" \ + ); \ + } while ( 0 ) + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + */ + +#define CPU_STACK_MINIMUM_SIZE (1024*8) + +#if defined(__powerpc64__) +#define CPU_SIZEOF_POINTER 8 +#else +#define CPU_SIZEOF_POINTER 4 +#endif + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ + +#define CPU_ALIGNMENT (PPC_ALIGNMENT) + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) + +#ifndef ASM +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + */ + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t swapped; + + __asm__ volatile("rlwimi %0,%1,8,24,31;" + "rlwimi %0,%1,24,16,23;" + "rlwimi %0,%1,8,8,15;" + "rlwimi %0,%1,24,0,7;" : + "=&r" ((swapped)) : "r" ((value))); + + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +static inline CPU_Counter_ticks _CPU_Counter_read( void ) +{ + CPU_Counter_ticks value; + +#if defined(__PPC_CPU_E6500__) + /* Use Alternate Time Base */ + __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); +#else + __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); +#endif + + return value; +} + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif /* ASM */ + + +#ifndef ASM +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + */ + +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_base, + size_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + memset( *(_destination), 0, sizeof( **(_destination) ) ) + +/* end of Context handler macros */ +#endif /* ASM */ + +#ifndef ASM +/* Bitfield handler macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE FALSE + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_bit_map_Word. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_Bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + */ + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ + "1" ((_value))); \ + (_output) = (_output) - 16; \ + } + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + */ + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 0x8000u >> (_bit_number) ) + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + */ + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +/* end of Priority handler macros */ +#endif /* ASM */ + +/* functions */ + +#ifndef ASM + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generallu used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +#ifdef RTEMS_SMP + uint32_t _CPU_SMP_Initialize( void ); + + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + void _CPU_SMP_Prepare_start_multitasking( void ); + + static inline uint32_t _CPU_SMP_Get_current_processor( void ) + { + uint32_t pir; + + /* Use Book E Processor ID Register (PIR) */ + __asm__ volatile ( + "mfspr %[pir], 286" + : [pir] "=&r" (pir) + ); + + return pir; + } + + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + static inline void _CPU_SMP_Processor_event_receive( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } +#endif + +typedef struct { + uintptr_t EXC_SRR0; + uintptr_t EXC_SRR1; + uint32_t _EXC_number; + uint32_t RESERVED_FOR_ALIGNMENT_0; + uint32_t EXC_CR; + uint32_t EXC_XER; + uintptr_t EXC_CTR; + uintptr_t EXC_LR; + uintptr_t RESERVED_FOR_ALIGNMENT_1; + #ifdef __SPE__ + uint32_t EXC_SPEFSCR; + uint64_t EXC_ACC; + #endif + PPC_GPR_TYPE GPR0; + PPC_GPR_TYPE GPR1; + PPC_GPR_TYPE GPR2; + PPC_GPR_TYPE GPR3; + PPC_GPR_TYPE GPR4; + PPC_GPR_TYPE GPR5; + PPC_GPR_TYPE GPR6; + PPC_GPR_TYPE GPR7; + PPC_GPR_TYPE GPR8; + PPC_GPR_TYPE GPR9; + PPC_GPR_TYPE GPR10; + PPC_GPR_TYPE GPR11; + PPC_GPR_TYPE GPR12; + PPC_GPR_TYPE GPR13; + PPC_GPR_TYPE GPR14; + PPC_GPR_TYPE GPR15; + PPC_GPR_TYPE GPR16; + PPC_GPR_TYPE GPR17; + PPC_GPR_TYPE GPR18; + PPC_GPR_TYPE GPR19; + PPC_GPR_TYPE GPR20; + PPC_GPR_TYPE GPR21; + PPC_GPR_TYPE GPR22; + PPC_GPR_TYPE GPR23; + PPC_GPR_TYPE GPR24; + PPC_GPR_TYPE GPR25; + PPC_GPR_TYPE GPR26; + PPC_GPR_TYPE GPR27; + PPC_GPR_TYPE GPR28; + PPC_GPR_TYPE GPR29; + PPC_GPR_TYPE GPR30; + PPC_GPR_TYPE GPR31; + uintptr_t RESERVED_FOR_ALIGNMENT_2; + #ifdef PPC_MULTILIB_ALTIVEC + uint32_t VRSAVE; + uint32_t RESERVED_FOR_ALIGNMENT_3[3]; + + /* This field must take stvewx/lvewx requirements into account */ + uint32_t RESERVED_FOR_ALIGNMENT_4[3]; + uint32_t VSCR; + + uint8_t V0[16]; + uint8_t V1[16]; + uint8_t V2[16]; + uint8_t V3[16]; + uint8_t V4[16]; + uint8_t V5[16]; + uint8_t V6[16]; + uint8_t V7[16]; + uint8_t V8[16]; + uint8_t V9[16]; + uint8_t V10[16]; + uint8_t V11[16]; + uint8_t V12[16]; + uint8_t V13[16]; + uint8_t V14[16]; + uint8_t V15[16]; + uint8_t V16[16]; + uint8_t V17[16]; + uint8_t V18[16]; + uint8_t V19[16]; + uint8_t V20[16]; + uint8_t V21[16]; + uint8_t V22[16]; + uint8_t V23[16]; + uint8_t V24[16]; + uint8_t V25[16]; + uint8_t V26[16]; + uint8_t V27[16]; + uint8_t V28[16]; + uint8_t V29[16]; + uint8_t V30[16]; + uint8_t V31[16]; + #endif + #ifdef PPC_MULTILIB_FPU + double F0; + double F1; + double F2; + double F3; + double F4; + double F5; + double F6; + double F7; + double F8; + double F9; + double F10; + double F11; + double F12; + double F13; + double F14; + double F15; + double F16; + double F17; + double F18; + double F19; + double F20; + double F21; + double F22; + double F23; + double F24; + double F25; + double F26; + double F27; + double F28; + double F29; + double F30; + double F31; + uint64_t FPSCR; + uint64_t RESERVED_FOR_ALIGNMENT_5; + #endif +} CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/* + * _CPU_Initialize_altivec() + * + * Global altivec-related initialization. + */ +void +_CPU_Initialize_altivec(void); + +/* + * _CPU_Context_switch_altivec + * + * This routine switches the altivec contexts passed to it. + */ + +void +_CPU_Context_switch_altivec( + ppc_context *from, + ppc_context *to +); + +/* + * _CPU_Context_restore_altivec + * + * This routine restores the altivec context passed to it. + */ + +void +_CPU_Context_restore_altivec( + ppc_context *ctxt +); + +/* + * _CPU_Context_initialize_altivec + * + * This routine initializes the altivec context passed to it. + */ + +void +_CPU_Context_initialize_altivec( + ppc_context *ctxt +); + +void _CPU_Fatal_error( + uint32_t _error +); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..792a8111ad --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h @@ -0,0 +1,247 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Copyright (C) 2007 Till Straumann + * + * Copyright (c) 2009, 2017 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +/* Exception stack frame -> BSP_Exception_frame */ +#ifdef __powerpc64__ + #define FRAME_LINK_SPACE 32 +#else + #define FRAME_LINK_SPACE 8 +#endif + +#define SRR0_FRAME_OFFSET FRAME_LINK_SPACE +#define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE) +#define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE) +#define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4) +#define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8) +#define EXC_XER_OFFSET (EXC_CR_OFFSET + 4) +#define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4) +#define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE) +#define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE) + +#ifndef __SPE__ + #define PPC_EXC_GPR_OFFSET(gpr) \ + ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) + #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3) + #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) + #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) + #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) + #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) + #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32)) + #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) + #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) + #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) + #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) + #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20)) + #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) + #elif defined(PPC_MULTILIB_ALTIVEC) + #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) + #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) + #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) + #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32) + #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) + #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE) + #elif defined(PPC_MULTILIB_FPU) + #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33)) + #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) + #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) + #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13)) + #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) + #else + #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE) + #endif +#else + #define PPC_EXC_SPEFSCR_OFFSET 44 + #define PPC_EXC_ACC_OFFSET 48 + #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) + #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4) + #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) + #define PPC_EXC_FRAME_SIZE 320 +#endif + +#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0) +#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1) +#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2) +#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3) +#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4) +#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5) +#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6) +#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7) +#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8) +#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9) +#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10) +#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11) +#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12) +#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13) +#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14) +#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15) +#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16) +#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17) +#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18) +#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19) +#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20) +#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21) +#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22) +#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23) +#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24) +#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25) +#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26) +#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27) +#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28) +#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29) +#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30) +#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31) + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifdef RTEMS_SMP + +/* Use SPRG0 for the per-CPU control of the current processor */ +#define PPC_PER_CPU_CONTROL_REGISTER 272 + +#endif /* RTEMS_SMP */ + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uintptr_t FRAME_SP; + #ifdef __powerpc64__ + uint32_t FRAME_CR; + uint32_t FRAME_RESERVED; + #endif + uintptr_t FRAME_LR; + #ifdef __powerpc64__ + uintptr_t FRAME_TOC; + #endif + uintptr_t EXC_SRR0; + uintptr_t EXC_SRR1; + uint32_t RESERVED_FOR_ALIGNMENT_0; + uint32_t EXC_INTERRUPT_ENTRY_INSTANT; + uint32_t EXC_CR; + uint32_t EXC_XER; + uintptr_t EXC_CTR; + uintptr_t EXC_LR; + uintptr_t EXC_INTERRUPT_FRAME; + #ifdef __SPE__ + uint32_t EXC_SPEFSCR; + uint64_t EXC_ACC; + #endif + PPC_GPR_TYPE GPR0; + PPC_GPR_TYPE GPR1; + PPC_GPR_TYPE GPR2; + PPC_GPR_TYPE GPR3; + PPC_GPR_TYPE GPR4; + PPC_GPR_TYPE GPR5; + PPC_GPR_TYPE GPR6; + PPC_GPR_TYPE GPR7; + PPC_GPR_TYPE GPR8; + PPC_GPR_TYPE GPR9; + PPC_GPR_TYPE GPR10; + PPC_GPR_TYPE GPR11; + PPC_GPR_TYPE GPR12; + #ifdef PPC_MULTILIB_ALTIVEC + /* This field must take stvewx/lvewx requirements into account */ + uint32_t RESERVED_FOR_ALIGNMENT_3[3]; + uint32_t VSCR; + + uint8_t V0[16]; + uint8_t V1[16]; + uint8_t V2[16]; + uint8_t V3[16]; + uint8_t V4[16]; + uint8_t V5[16]; + uint8_t V6[16]; + uint8_t V7[16]; + uint8_t V8[16]; + uint8_t V9[16]; + uint8_t V10[16]; + uint8_t V11[16]; + uint8_t V12[16]; + uint8_t V13[16]; + uint8_t V14[16]; + uint8_t V15[16]; + uint8_t V16[16]; + uint8_t V17[16]; + uint8_t V18[16]; + uint8_t V19[16]; + #endif + #ifdef PPC_MULTILIB_FPU + double F0; + double F1; + double F2; + double F3; + double F4; + double F5; + double F6; + double F7; + double F8; + double F9; + double F10; + double F11; + double F12; + double F13; + uint64_t FPSCR; + uint64_t RESERVED_FOR_ALIGNMENT_4; + #endif + #if PPC_STACK_RED_ZONE_SIZE > 0 + uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ]; + #endif +} CPU_Interrupt_frame; + +#ifdef RTEMS_SMP + +static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void ) +{ + struct Per_CPU_Control *cpu_self; + + __asm__ volatile ( + "mfspr %0, " RTEMS_XSTRING( PPC_PER_CPU_CONTROL_REGISTER ) + : "=r" ( cpu_self ) + ); + + return cpu_self; +} + +#define _CPU_Get_current_per_CPU_control() _PPC_Get_current_per_CPU_control() + +#endif /* RTEMS_SMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/powerpc.h b/cpukit/score/cpu/powerpc/include/rtems/score/powerpc.h new file mode 100644 index 0000000000..88ee0020e6 --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/score/powerpc.h @@ -0,0 +1,187 @@ +/** + * @file + * + * @brief IBM/Motorola Power Pc Definitions + * + * This file contains definitions for the IBM/Motorola PowerPC + * family members. + */ + +/* + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * MPC860 support code was added by Jay Monkman + * MPC8260 support added by Andy Dachs + * Surrey Satellite Technology Limited + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Note: + * This file is included by both C and assembler code ( -DASM ) + */ + + +#ifndef _RTEMS_SCORE_POWERPC_H +#define _RTEMS_SCORE_POWERPC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "PowerPC" + +/* + * This file contains the information required to build + * RTEMS for the PowerPC family. + */ + +/* Generic ppc */ + +#ifdef _SOFT_FLOAT +#define CPU_MODEL_NAME "Generic (no FPU)" +#elif defined(__NO_FPRS__) || defined(__SPE__) +#define CPU_MODEL_NAME "Generic (E500/float-gprs/SPE)" +#else +#define CPU_MODEL_NAME "Generic (classic FPU)" +#endif + +#ifdef __PPC_CPU_E6500__ +#define PPC_DEFAULT_CACHE_LINE_POWER 6 +#else +#define PPC_DEFAULT_CACHE_LINE_POWER 5 +#endif + +#define PPC_DEFAULT_CACHE_LINE_SIZE (1 << PPC_DEFAULT_CACHE_LINE_POWER) + +#define PPC_STRUCTURE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE + +/* + * Application binary interfaces. + * + * PPC_ABI MUST be defined as one of these. + * Only big endian is currently supported. + */ + +/* + * SVR4 ABI + */ +#define PPC_ABI_SVR4 2 +/* + * Embedded ABI + */ +#define PPC_ABI_EABI 3 + +/* + * Default to the EABI used by current GNU tools + */ + +#ifndef PPC_ABI +#define PPC_ABI PPC_ABI_EABI +#endif + +/* + * Use worst case stack alignment. For the EABI an 8-byte alignment would be + * sufficient. + */ + +#define PPC_STACK_ALIGN_POWER 4 +#define PPC_STACK_ALIGNMENT (1 << PPC_STACK_ALIGN_POWER) + +/* + * Assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT. + */ + +#if defined(_SOFT_FLOAT) \ + || defined(__NO_FPRS__) /* e500 has unified integer/FP registers */ \ + || defined(__PPC_CPU_E6500__) +#define PPC_HAS_FPU 0 +#else +#define PPC_HAS_FPU 1 +#endif + +#if defined(__PPC_CPU_E6500__) && defined(__ALTIVEC__) +#define PPC_MULTILIB_ALTIVEC +#endif + +#if defined(__PPC_CPU_E6500__) && !defined(_SOFT_FLOAT) +#define PPC_MULTILIB_FPU +#endif + +#ifdef PPC_MULTILIB_ALTIVEC +#define PPC_ALIGNMENT 16 +#else +#define PPC_ALIGNMENT 8 +#endif + +#ifdef __powerpc64__ +#define PPC_STACK_RED_ZONE_SIZE 512 +#else +#define PPC_STACK_RED_ZONE_SIZE 0 +#endif + +/* + * Unless specified above, If the model has FP support, it is assumed to + * support doubles (8-byte floating point numbers). + * + * If the model does NOT have FP support, then the model does + * NOT have double length FP registers. + */ + +#if (PPC_HAS_FPU) +#define PPC_HAS_DOUBLE 1 +#else +#define PPC_HAS_DOUBLE 0 +#endif + +/* + * Assemblers. + * PPC_ASM MUST be defined as one of these. + * + * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. + * + * NOTE: Only PPC_ABI_ELF is currently fully supported. + * + * Also NOTE: cpukit doesn't need this but asm.h which is defined + * in cpukit for consistency with other ports does. + */ + +#define PPC_ASM_ELF 0 + +/* + * Default to the assembler format used by the current GNU tools. + */ +#define PPC_ASM PPC_ASM_ELF + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_POWERPC_H */ diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/types.h b/cpukit/score/cpu/powerpc/include/rtems/score/types.h new file mode 100644 index 0000000000..cdab30234d --- /dev/null +++ b/cpukit/score/cpu/powerpc/include/rtems/score/types.h @@ -0,0 +1,62 @@ +/** + * @file + * + * @brief PowerPC CPU Type Definitions + * + * This include file contains type definitions pertaining to the PowerPC + * processor family. + */ + +/* + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void ppc_isr; + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/powerpc/preinstall.am b/cpukit/score/cpu/powerpc/preinstall.am deleted file mode 100644 index b0f59c24f9..0000000000 --- a/cpukit/score/cpu/powerpc/preinstall.am +++ /dev/null @@ -1,58 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/powerpc.h: rtems/score/powerpc.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/powerpc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/powerpc.h - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - -$(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/powerpc - @: > $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/powerpc/registers.h: rtems/powerpc/registers.h $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/powerpc/registers.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc/registers.h - diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h deleted file mode 100644 index 2fddf56e6d..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/asm.h +++ /dev/null @@ -1,310 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1995. - * i-cubed ltd. - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#ifndef __FLOAT_REGISTER_PREFIX__ -#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ -#endif - -#ifndef __PROC_LABEL_PREFIX__ -#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for procedure labels. */ - -#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* Use the right prefix for floating point registers. */ - -#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(0) -#define r1 REG(1) -#define r2 REG(2) -#define r3 REG(3) -#define r4 REG(4) -#define r5 REG(5) -#define r6 REG(6) -#define r7 REG(7) -#define r8 REG(8) -#define r9 REG(9) -#define r10 REG(10) -#define r11 REG(11) -#define r12 REG(12) -#define r13 REG(13) -#define r14 REG(14) -#define r15 REG(15) -#define r16 REG(16) -#define r17 REG(17) -#define r18 REG(18) -#define r19 REG(19) -#define r20 REG(20) -#define r21 REG(21) -#define r22 REG(22) -#define r23 REG(23) -#define r24 REG(24) -#define r25 REG(25) -#define r26 REG(26) -#define r27 REG(27) -#define r28 REG(28) -#define r29 REG(29) -#define r30 REG(30) -#define r31 REG(31) -#define f0 FREG(0) -#define f1 FREG(1) -#define f2 FREG(2) -#define f3 FREG(3) -#define f4 FREG(4) -#define f5 FREG(5) -#define f6 FREG(6) -#define f7 FREG(7) -#define f8 FREG(8) -#define f9 FREG(9) -#define f10 FREG(10) -#define f11 FREG(11) -#define f12 FREG(12) -#define f13 FREG(13) -#define f14 FREG(14) -#define f15 FREG(15) -#define f16 FREG(16) -#define f17 FREG(17) -#define f18 FREG(18) -#define f19 FREG(19) -#define f20 FREG(20) -#define f21 FREG(21) -#define f22 FREG(22) -#define f23 FREG(23) -#define f24 FREG(24) -#define f25 FREG(25) -#define f26 FREG(26) -#define f27 FREG(27) -#define f28 FREG(28) -#define f29 FREG(29) -#define f30 FREG(30) -#define f31 FREG(31) -#define v0 0 -#define v1 1 -#define v2 2 -#define v3 3 -#define v4 4 -#define v5 5 -#define v6 6 -#define v7 7 -#define v8 8 -#define v9 9 -#define v10 10 -#define v11 11 -#define v12 12 -#define v13 13 -#define v14 14 -#define v15 15 -#define v16 16 -#define v17 17 -#define v18 18 -#define v19 19 -#define v20 20 -#define v21 21 -#define v22 22 -#define v23 23 -#define v24 24 -#define v25 25 -#define v26 26 -#define v27 27 -#define v28 28 -#define v29 29 -#define v30 30 -#define v31 31 - -/* - * Some special purpose registers (SPRs). - */ -#define srr0 0x01a -#define srr1 0x01b -#define srr2 0x3de /* IBM 400 series only */ -#define srr3 0x3df /* IBM 400 series only */ -#define csrr0 58 /* Book E */ -#define csrr1 59 /* Book E */ -#define mcsrr0 570 /* e500 */ -#define mcsrr1 571 /* e500 */ -#define dsrr0 574 /* e200 */ -#define dsrr1 575 /* e200 */ - -#define sprg0 0x110 -#define sprg1 0x111 -#define sprg2 0x112 -#define sprg3 0x113 -#define sprg4 276 -#define sprg5 277 -#define sprg6 278 -#define sprg7 279 - -#define usprg0 256 - -#define dar 0x013 /* Data Address Register */ -#define dec 0x016 /* Decrementer Register */ - -#if defined(ppc403) || defined(ppc405) -/* the following SPR/DCR registers exist only in IBM 400 series */ -#define dear 0x3d5 -#define evpr 0x3d6 /* SPR: exception vector prefix register */ -#define iccr 0x3fb /* SPR: instruction cache control reg. */ -#define dccr 0x3fa /* SPR: data cache control reg. */ - -#if defined (ppc403) -#define exisr 0x040 /* DCR: external interrupt status register */ -#define exier 0x042 /* DCR: external interrupt enable register */ -#endif /* ppc403 */ -#if defined(ppc405) -#define exisr 0x0C0 /* DCR: external interrupt status register */ -#define exier 0x0C2 /* DCR: external interrupt enable register */ -#endif /* ppc405 */ - -#define br0 0x080 /* DCR: memory bank register 0 */ -#define br1 0x081 /* DCR: memory bank register 1 */ -#define br2 0x082 /* DCR: memory bank register 2 */ -#define br3 0x083 /* DCR: memory bank register 3 */ -#define br4 0x084 /* DCR: memory bank register 4 */ -#define br5 0x085 /* DCR: memory bank register 5 */ -#define br6 0x086 /* DCR: memory bank register 6 */ -#define br7 0x087 /* DCR: memory bank register 7 */ - -/* end of IBM400 series register definitions */ - -#elif defined(mpc555) -/* The following registers are for the MPC5xx */ -#define eie 0x050 /* External Interrupt Enable Register */ -#define eid 0x051 /* External Interrupt Disable Register */ -#define nri 0x052 /* Non-Recoverable Interrupt Register */ - -#elif defined(mpc860) || defined(mpc821) -/* The following registers are for the MPC8x0 */ -#define der 0x095 /* Debug Enable Register */ -#define ictrl 0x09E /* Instruction Support Control Register */ -#define immr 0x27E /* Internal Memory Map Register */ -/* end of MPC8x0 registers */ -#endif - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC_VAR(sym) .globl SYM (sym) -#define EXTERN_VAR(sym) .extern SYM (sym) -#define PUBLIC_PROC(sym) .globl PROC (sym) -#define EXTERN_PROC(sym) .extern PROC (sym) - -/* Other potentially assembler specific operations */ -#if PPC_ASM == PPC_ASM_ELF -#define ALIGN(n,p) .align p -#define DESCRIPTOR(x) \ - .section .descriptors,"aw"; \ - PUBLIC_VAR (x); \ -SYM (x):; \ - .long PROC (x); \ - .long s.got; \ - .long 0 - -#define EXT_SYM_REF(x) .long x -#define EXT_PROC_REF(x) .long x - -/* - * Define macros to handle section beginning and ends. - */ - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -#else -#error "PPC_ASM_TYPE is not properly defined" -#endif -#ifndef PPC_ASM -#error "PPC_ASM_TYPE is not properly defined" -#endif - -#if defined(__powerpc64__) -#define PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop -#else -#define PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - -#endif diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h deleted file mode 100644 index 4d9350324e..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h +++ /dev/null @@ -1,774 +0,0 @@ -/** - * @file - * - * @brief PowerPc MSR and Registers Access Definitions - * - * This file contains some powerpc MSR and registers access definitions. - */ - -/* - * COPYRIGHT (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Added MPC8260 Andy Dachs - * Surrey Satellite Technology Limited - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_POWERPC_REGISTERS_H -#define _RTEMS_POWERPC_REGISTERS_H - -/* Bit encodings for Machine State Register (MSR) */ -#define MSR_CM (1<<31) /* Computation mode */ -#define MSR_GS (1<<28) /* Guest state */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ -#define MSR_SPE (1<<25) /* SPE enable (e500) */ -#define MSR_AP (1<<25) /* Auxiliary processor available */ -#define MSR_APE (1<<19) /* APU exception enable */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait state enable (e500, 4xx) */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* BookE critical interrupt */ -#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ -#define MSR_EE (1<<15) /* External Interrupt enable */ -#define MSR_PR (1<<14) /* Supervisor/User privilege */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */ -#define MSR_DWE (1<<10) /* Debug wait enable (4xx) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* BookE debug exception */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_E300_CE (1<<7) /* e300 critical interrupt */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction MMU enable */ -#define MSR_DR (1<<4) /* Data MMU enable */ -#define MSR_IS (1<<5) /* Instruction address space */ -#define MSR_DS (1<<4) /* Data address space */ -#define MSR_PMM (1<<2) /* Performance monitor mark */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little-Endian enable */ - -/* Bit encodings for Hardware Implementation Register (HID0) - on PowerPC 603, 604, etc. processors (not 601). */ - -/* WARNING: HID0/HID1 are *truely* implementation dependent! - * you *cannot* rely on the same bits to be present, - * at the same place or even in the same register - * on different CPU familys. - * E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the - * on the 7450s. IFFT is XBSEN on 7450 and so on... - */ -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_TBEN (1<<26) /* 7455:this bit must be set - * and TBEN signal must be asserted - * to enable the time base and - * decrementer. - */ -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !! */ -#define HID0_7455_HIGH_BAT_EN (1<<23) - -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<15) /* Instruction Cache Enable */ -#define HID0_DCE (1<<14) /* Data Cache Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<12) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ -#define HID0_DCI (1<<10) /* Data Cache Invalidate */ -/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */ -#define HID0_7455_XBSEN (1<<8) -#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ -/* S.K. Feng 10/03, added for MPC7455 */ -#define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ -#define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ - -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ - -/* fpscr settings */ -#define FPSCR_FX (1<<31) -#define FPSCR_FEX (1<<30) - -#define _MACH_prep 1 -#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ -#define _MACH_chrp 4 /* chrp machine */ -#define _MACH_mbx 8 /* Motorola MBX board */ -#define _MACH_apus 16 /* amiga with phase5 powerup */ -#define _MACH_fads 32 /* Motorola FADS board */ - -/* see residual.h for these */ -#define _PREP_Motorola 0x01 /* motorola prep */ -#define _PREP_Firm 0x02 /* firmworks prep */ -#define _PREP_IBM 0x00 /* ibm prep */ -#define _PREP_Bull 0x03 /* bull prep */ - -/* these are arbitrary */ -#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ -#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ - -#define _GLOBAL(n)\ - .globl n;\ -n: - -#define TBRU 269 /* Time base Upper/Lower (Reading) */ -#define TBRL 268 -#define TBWU 285 /* Time base Upper/Lower (Writing) */ -#define TBWL 284 -#define PPC_XER 1 -#define PPC_LR 8 -#define PPC_CTR 9 -#define HID0 1008 /* Hardware Implementation 0 */ -#define HID1 1009 /* Hardware Implementation 1 */ -#define HID2 1011 /* Hardware Implementation 2 */ -#define DABR 1013 /* Data Access Breakpoint */ -#define PPC_PVR 287 /* Processor Version */ -#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ -#define IBAT0L 529 -#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ -#define IBAT1L 531 -#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ -#define IBAT2L 533 -#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ -#define IBAT3L 535 - -/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ -#define IBAT4U 560 /* Instruction BAT #4 Upper/Lower */ -#define IBAT4L 561 -#define IBAT5U 562 /* Instruction BAT #5 Upper/Lower */ -#define IBAT5L 563 -#define IBAT6U 564 /* Instruction BAT #6 Upper/Lower */ -#define IBAT6L 565 -#define IBAT7U 566 /* Instruction BAT #7 Upper/Lower */ -#define IBAT7L 567 - -#define DBAT0U 536 /* Data BAT #0 Upper/Lower */ -#define DBAT0L 537 -#define DBAT1U 538 /* Data BAT #1 Upper/Lower */ -#define DBAT1L 539 -#define DBAT2U 540 /* Data BAT #2 Upper/Lower */ -#define DBAT2L 541 -#define DBAT3U 542 /* Data BAT #3 Upper/Lower */ -#define DBAT3L 543 - -/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ -#define DBAT4U 568 /* Instruction BAT #4 Upper/Lower */ -#define DBAT4L 569 -#define DBAT5U 570 /* Instruction BAT #5 Upper/Lower */ -#define DBAT5L 571 -#define DBAT6U 572 /* Instruction BAT #6 Upper/Lower */ -#define DBAT6L 573 -#define DBAT7U 574 /* Instruction BAT #7 Upper/Lower */ -#define DBAT7L 575 - -#define DMISS 976 /* TLB Lookup/Refresh registers */ -#define DCMP 977 -#define HASH1 978 -#define HASH2 979 -#define IMISS 980 -#define ICMP 981 -#define PPC_RPA 982 -#define SDR1 25 /* MMU hash base register */ -#define PPC_DAR 19 /* Data Address Register */ -#define DEAR_BOOKE 61 -#define DEAR_405 981 -#define SPR0 272 /* Supervisor Private Registers */ -#define SPRG0 272 -#define SPR1 273 -#define SPRG1 273 -#define SPR2 274 -#define SPRG2 274 -#define SPR3 275 -#define SPRG3 275 -#define SPRG4 276 -#define SPRG5 277 -#define SPRG6 278 -#define SPRG7 279 -#define USPRG0 256 -#define DSISR 18 -#define SRR0 26 /* Saved Registers (exception) */ -#define SRR1 27 -#define IABR 1010 /* Instruction Address Breakpoint */ -#define PPC_DEC 22 /* Decrementer */ -#define PPC_EAR 282 /* External Address Register */ - -#define MSSCR0 1014 /* Memory Subsystem Control Register */ - -#define L2CR 1017 /* PPC 750 and 74xx L2 control register */ - -#define L2CR_L2E (1<<31) /* enable */ -#define L2CR_L2I (1<<21) /* global invalidate */ - -/* watch out L2IO and L2DO are different between 745x and 7400/7410 */ -/* Oddly, the following L2CR bit defintions in 745x - * is different from that of 7400 and 7410. - * Though not used in 7400 and 7410, it is appeded with _745x just - * to be clarified. - */ -#define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ -#define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ -#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) -#define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ - -#define L3CR 1018 /* PPC 7450/7455 L3 control register */ -#define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ -#define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ - -#define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) - -#define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ -#define L3CR_L3E 0x80000000 /* 0: L3 enable */ -#define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ -#define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ -#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ -#define L3SIZ_1M 0x00000000 -#define L3SIZ_2M 0x10000000 -#define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ -#define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ -#define L3CLK_60 0x00000000 /* core clock / 6 */ -#define L3CLK_20 0x01000000 /* / 2 */ -#define L3CLK_25 0x01800000 /* / 2.5 */ -#define L3CLK_30 0x02000000 /* / 3 */ -#define L3CLK_35 0x02800000 /* / 3.5 */ -#define L3CLK_40 0x03000000 /* / 4 */ -#define L3CLK_50 0x03800000 /* / 5 */ -#define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ -#define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ -#define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ -#define L3CKSP_2 0x00000000 /* 2 clocks */ -#define L3CKSP_3 0x00010000 /* 3 clocks */ -#define L3CKSP_4 0x00020000 /* 4 clocks */ -#define L3CKSP_5 0x00030000 /* 5 clocks */ -#define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ -#define L3PSP_0 0x00000000 /* 0 clocks */ -#define L3PSP_1 0x00002000 /* 1 clocks */ -#define L3PSP_2 0x00004000 /* 2 clocks */ -#define L3PSP_3 0x00006000 /* 3 clocks */ -#define L3PSP_4 0x00008000 /* 4 clocks */ -#define L3PSP_5 0x0000a000 /* 5 clocks */ -#define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ -#define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ -#define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig -lidate */ -#define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ -#define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ -#define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ -#define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ -#define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ -#define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ -#define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ -#define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ - -#define THRM1 1020 -#define THRM2 1021 -#define THRM3 1022 -#define THRM1_TIN (1<<(31-0)) -#define THRM1_TIV (1<<(31-1)) -#define THRM1_THRES (0x7f<<(31-8)) -#define THRM1_TID (1<<(31-29)) -#define THRM1_TIE (1<<(31-30)) -#define THRM1_V (1<<(31-31)) -#define THRM3_SITV (0x1fff << (31-30)) -#define THRM3_E (1<<(31-31)) - -/* Segment Registers */ -#define PPC_SR0 0 -#define PPC_SR1 1 -#define PPC_SR2 2 -#define PPC_SR3 3 -#define PPC_SR4 4 -#define PPC_SR5 5 -#define PPC_SR6 6 -#define PPC_SR7 7 -#define PPC_SR8 8 -#define PPC_SR9 9 -#define PPC_SR10 10 -#define PPC_SR11 11 -#define PPC_SR12 12 -#define PPC_SR13 13 -#define PPC_SR14 14 -#define PPC_SR15 15 - -#define BOOKE_DECAR 54 - -#define PPC405_MCSR 0x23C -#define PPC405_ESR 0x3D4 -#define PPC405_DEAR 0x3D5 -#define BOOKE_DEAR 61 - -#define PPC405_TSR 0x3D8 -#define BOOKE_TSR 336 -#define BOOKE_TSR_ENW (1<<31) -#define BOOKE_TSR_WIS (1<<30) -#define BOOKE_TSR_DIS (1<<27) -#define BOOKE_TSR_FIS (1<<26) - -#define PPC405_TCR 0x3DA -#define BOOKE_TCR 340 -#define BOOKE_TCR_WP(x) (((x)&3)<<30) -#define BOOKE_TCR_WP_MASK (3<<30) -#define BOOKE_TCR_WRC(x) (((x)&3)<<28) -#define BOOKE_TCR_WRC_MASK (3<<28) -#define BOOKE_TCR_WIE (1<<27) -#define BOOKE_TCR_DIE (1<<26) -#define BOOKE_TCR_FP(x) (((x)&3)<<24) -#define BOOKE_TCR_FIE (1<<23) -#define BOOKE_TCR_ARE (1<<22) -#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17) -#define BOOKE_TCR_WPEXT_MASK (0xf<<17) -#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13) -#define BOOKE_TCR_FPEXT_MASK (0xf<<13) - -#define BOOKE_PID 48 /* Process ID */ -#define BOOKE_CSRR0 58 /* Critical Save/Restore Register 0 */ -#define BOOKE_CSRR1 59 /* Critical Save/Restore Register 1 */ -#define BOOKE_ESR 62 /* Exception Syndrome Register */ -#define BOOKE_IVPR 63 /* Interrupt Vector Prefix Register */ -#define BOOKE_SPRG4_W 260 /* Special Purpose Register General 4 (WO) */ -#define BOOKE_SPRG5_W 261 /* Special Purpose Register General 5 (WO) */ -#define BOOKE_SPRG6_W 262 /* Special Purpose Register General 6 (WO) */ -#define BOOKE_SPRG7_W 263 /* Special Purpose Register General 7 (WO) */ -#define BOOKE_PIR 286 /* Processor ID Register */ -#define BOOKE_DBSR 304 /* Debug Status Register */ - -#define BOOKE_EPCR 307 /* Embedded Processor Control Register */ -#define BOOKE_EPCR_EXTGS (1 << 31) -#define BOOKE_EPCR_DTLBGS (1 << 30) -#define BOOKE_EPCR_ITLBGS (1 << 29) -#define BOOKE_EPCR_DSIGS (1 << 28) -#define BOOKE_EPCR_ISIGS (1 << 27) -#define BOOKE_EPCR_DUVD (1 << 26) -#define BOOKE_EPCR_ICM (1 << 25) -#define BOOKE_EPCR_GICM (1 << 24) -#define BOOKE_EPCR_DGTMI (1 << 23) -#define BOOKE_EPCR_DMIUH (1 << 22) -#define BOOKE_EPCR_PMGS (1 << 21) - -#define BOOKE_DBCR0 308 /* Debug Control Register 0 */ -#define BOOKE_DBCR1 309 /* Debug Control Register 1 */ -#define BOOKE_DBCR2 310 /* Debug Control Register 2 */ -#define BOOKE_IAC1 312 /* Instruction Address Compare 1 */ -#define BOOKE_IAC2 313 /* Instruction Address Compare 2 */ -#define BOOKE_IAC3 314 /* Instruction Address Compare 3 */ -#define BOOKE_IAC4 315 /* Instruction Address Compare 4 */ -#define BOOKE_DAC1 316 /* Data Address Compare 1 */ -#define BOOKE_DAC2 317 /* Data Address Compare 2 */ -#define BOOKE_DVC1 318 /* Data Value Compare 1 */ -#define BOOKE_DVC2 319 /* Data Value Compare 2 */ -#define BOOKE_GSRR0 378 /* Guest Save/Restore Register 0 */ -#define BOOKE_GSRR1 379 /* Guest Save/Restore Register 1 */ -#define BOOKE_GEPR 380 /* Guest External Proxy Register */ -#define BOOKE_GDEAR 381 /* Guest Data Exception Address Register */ -#define BOOKE_GPIR 382 /* Guest Processor ID Register */ -#define BOOKE_GESR 383 /* Guest Exception Syndrome Register */ -#define BOOKE_IVOR0 400 /* Interrupt Vector Offset Register 0 */ -#define BOOKE_IVOR1 401 /* Interrupt Vector Offset Register 1 */ -#define BOOKE_IVOR2 402 /* Interrupt Vector Offset Register 2 */ -#define BOOKE_IVOR3 403 /* Interrupt Vector Offset Register 3 */ -#define BOOKE_IVOR4 404 /* Interrupt Vector Offset Register 4 */ -#define BOOKE_IVOR5 405 /* Interrupt Vector Offset Register 5 */ -#define BOOKE_IVOR6 406 /* Interrupt Vector Offset Register 6 */ -#define BOOKE_IVOR7 407 /* Interrupt Vector Offset Register 7 */ -#define BOOKE_IVOR8 408 /* Interrupt Vector Offset Register 8 */ -#define BOOKE_IVOR9 409 /* Interrupt Vector Offset Register 9 */ -#define BOOKE_IVOR10 410 /* Interrupt Vector Offset Register 10 */ -#define BOOKE_IVOR11 411 /* Interrupt Vector Offset Register 11 */ -#define BOOKE_IVOR12 412 /* Interrupt Vector Offset Register 12 */ -#define BOOKE_IVOR13 413 /* Interrupt Vector Offset Register 13 */ -#define BOOKE_IVOR14 414 /* Interrupt Vector Offset Register 14 */ -#define BOOKE_IVOR15 415 /* Interrupt Vector Offset Register 15 */ -#define BOOKE_IVOR42 436 /* Interrupt Vector Offset Register 42 */ -#define BOOKE_IVOR32 528 /* Interrupt Vector Offset Register 32 */ -#define BOOKE_IVOR33 529 /* Interrupt Vector Offset Register 33 */ -#define BOOKE_IVOR34 530 /* Interrupt Vector Offset Register 34 */ -#define BOOKE_IVOR35 531 /* Interrupt Vector Offset Register 35 */ -#define BOOKE_IVOR36 532 /* Interrupt Vector Offset Register 36 */ -#define BOOKE_IVOR37 533 /* Interrupt Vector Offset Register 37 */ -#define BOOKE_IVOR38 432 /* Interrupt Vector Offset Register 38 */ -#define BOOKE_IVOR39 433 /* Interrupt Vector Offset Register 39 */ -#define BOOKE_IVOR40 434 /* Interrupt Vector Offset Register 40 */ -#define BOOKE_IVOR41 435 /* Interrupt Vector Offset Register 41 */ -#define BOOKE_GIVOR2 440 /* Guest Interrupt Vector Offset Register 2 */ -#define BOOKE_GIVOR3 441 /* Guest Interrupt Vector Offset Register 3 */ -#define BOOKE_GIVOR4 442 /* Guest Interrupt Vector Offset Register 4 */ -#define BOOKE_GIVOR8 443 /* Guest Interrupt Vector Offset Register 8 */ -#define BOOKE_GIVOR13 444 /* Guest Interrupt Vector Offset Register 13 */ -#define BOOKE_GIVOR14 445 /* Guest Interrupt Vector Offset Register 14 */ -#define BOOKE_GIVPR 446 /* Guest Interrupt Vector Prefix Register */ -#define BOOKE_MCSRR0 570 /* Machine Check Save/Restore Register 0 */ -#define BOOKE_MCSRR1 571 /* Machine Check Save/Restore Register 1 */ -#define BOOKE_MCSR 572 /* Machine Check Status Register */ -#define BOOKE_DSRR0 574 /* Debug Save/Restore Register 0 */ -#define BOOKE_DSRR1 575 /* Debug Save/Restore Register 1 */ - -#define PPC440_INV0 880 /* Instruction Cache Normal Victim 0 */ -#define PPC440_INV1 881 /* Instruction Cache Normal Victim 1 */ -#define PPC440_INV2 882 /* Instruction Cache Normal Victim 2 */ -#define PPC440_INV3 883 /* Instruction Cache Normal Victim 3 */ -#define PPC440_ITV0 884 /* Instruction Cache Transient Victim 0 */ -#define PPC440_ITV1 885 /* Instruction Cache Transient Victim 1 */ -#define PPC440_ITV2 886 /* Instruction Cache Transient Victim 2 */ -#define PPC440_ITV3 887 /* Instruction Cache Transient Victim 3 */ -#define PPC440_CCR1 888 /* Core Configuration Register 1 */ -#define PPC440_DNV0 912 /* Data Cache Normal Victim 0 */ -#define PPC440_DNV1 913 /* Data Cache Normal Victim 1 */ -#define PPC440_DNV2 914 /* Data Cache Normal Victim 2 */ -#define PPC440_DNV3 915 /* Data Cache Normal Victim 3 */ -#define PPC440_DTV0 916 /* Data Cache Transient Victim 0 */ -#define PPC440_DTV1 917 /* Data Cache Transient Victim 1 */ -#define PPC440_DTV2 918 /* Data Cache Transient Victim 2 */ -#define PPC440_DTV3 919 /* Data Cache Transient Victim 3 */ -#define PPC440_DVLIM 920 /* Data Cache Victim Limit */ -#define PPC440_IVLIM 921 /* Instruction Cache Victim Limit */ -#define PPC440_RSTCFG 923 /* Reset Configuration */ -#define PPC440_DCDBTRL 924 /* Data Cache Debug Tag Register Low */ -#define PPC440_DCDBTRH 925 /* Data Cache Debug Tag Register High */ -#define PPC440_ICDBTRL 926 /* Instruction Cache Debug Tag Register Low */ -#define PPC440_ICDBTRH 927 /* Instruction Cache Debug Tag Register High */ -#define PPC440_MMUCR 946 /* Memory Management Unit Control Register */ -#define PPC440_CCR0 947 /* Core Configuration Register 0 */ -#define PPC440_ICDBDR 979 /* Instruction Cache Debug Data Register */ -#define PPC440_DBDR 1011 /* Debug Data Register */ - -#define PPC440_TLB0_EPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Etended Page Number */ -#define PPC440_TLB0_EPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1)) -#define PPC440_TLB0_V ( 1 << (31-22)) /* Entry valid */ -#define PPC440_TLB0_TS ( 1 << (31-23)) /* Translation space */ -#define PPC440_TLB0_TSIZE(n) ( (0xf & (n)) << (31-27)) /* Page size */ -#define PPC440_TLB0_TSIZE_GET(n) ( ((n) >> (31-27)) & 0xf) -#define PPC440_TLB0_TPAR(n) ( (0xf & (n)) << (31-31)) /* Tag Parity */ -#define PPC440_TLB0_TPAR_GET(n) ( ((n) >> (31-31)) & 0xf) - -#define PPC440_PID_TID(n) ( (0xff & (n)) << (31-31)) /* Translation ID */ -#define PPC440_PID_TID_GET(n) ( ((n) >> (31-31)) & 0xff) - -#define PPC440_TLB1_RPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Real Page Number */ -#define PPC440_TLB1_RPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1)) -#define PPC440_TLB1_PAR1(n) ( (0x3 & (n)) << (31-23)) /* Parity for TLB word 1 */ -#define PPC440_TLB1_PAR1_GET(n) ( ((n) >> (31-23)) & 0x3) -#define PPC440_TLB1_ERPN(n) ( (0xf & (n)) << (31-31)) /* Extended Real Page No. */ -#define PPC440_TLB1_ERPN_GET(n) ( ((n) >> (31-31)) & 0xf) - -#define PPC440_TLB2_PAR2(n) ( (0x3 & (n)) << (31- 1)) /* Parity for TLB word 2 */ -#define PPC440_TLB2_PAR2_GET(n) ( ((n) >> (31- 1)) & 0x3) -#define PPC440_TLB2_U0 ( 1 << (31-16)) /* User attr. 0 */ -#define PPC440_TLB2_U1 ( 1 << (31-17)) /* User attr. 1 */ -#define PPC440_TLB2_U2 ( 1 << (31-18)) /* User attr. 2 */ -#define PPC440_TLB2_U3 ( 1 << (31-19)) /* User attr. 3 */ -#define PPC440_TLB2_W ( 1 << (31-20)) /* Write-through */ -#define PPC440_TLB2_I ( 1 << (31-21)) /* Cache-inhibited */ -#define PPC440_TLB2_M ( 1 << (31-22)) /* Memory-coherence req. */ -#define PPC440_TLB2_G ( 1 << (31-23)) /* Guarded */ -#define PPC440_TLB2_E ( 1 << (31-24)) /* Little-endian */ -#define PPC440_TLB2_UX ( 1 << (31-26)) /* User exec. */ -#define PPC440_TLB2_UW ( 1 << (31-27)) /* User write */ -#define PPC440_TLB2_UR ( 1 << (31-28)) /* User read */ -#define PPC440_TLB2_SX ( 1 << (31-29)) /* Super exec. */ -#define PPC440_TLB2_SW ( 1 << (31-30)) /* Super write */ -#define PPC440_TLB2_SR ( 1 << (31-31)) /* Super read */ - -#define PPC440_TLB2_ATTR(x) ( ((x) & 0x1ff) << 7 ) -#define PPC440_TLB2_ATTR_GET(x) ( ((x) >> 7) & 0x1ff ) - -#define PPC440_TLB2_PERM(n) ( (n) & 0x3f ) -#define PPC440_TLB2_PERM_GET(n) ( (n) & 0x3f ) - -/* Freescale Book E Implementation Standards (EIS): Branch Operations */ - -#define FSL_EIS_BUCSR 1013 -#define FSL_EIS_BUCSR_STAC_EN (1 << (63 - 39)) -#define FSL_EIS_BUCSR_LS_EN (1 << (63 - 41)) -#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54)) -#define FSL_EIS_BUCSR_BALLOC_ALL (0x0 << (63 - 59)) -#define FSL_EIS_BUCSR_BALLOC_FORWARD (0x1 << (63 - 59)) -#define FSL_EIS_BUCSR_BALLOC_BACKWARD (0x2 << (63 - 59)) -#define FSL_EIS_BUCSR_BALLOC_NONE (0x3 << (63 - 59)) -#define FSL_EIS_BUCSR_BPRED_TAKEN (0x0 << (63 - 61)) -#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_FORWARD (0x1 << (63 - 62)) -#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_BACKWARD (0x2 << (63 - 62)) -#define FSL_EIS_BUCSR_BPRED_NOT_TAKEN (0x3 << (63 - 62)) -#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63)) - -/* Freescale Book E Implementation Standards (EIS): Hardware Implementation-Dependent Registers */ - -#define FSL_EIS_SVR 1023 - -/* Freescale Book E Implementation Standards (EIS): Thread Management and Control Registers */ - -#define FSL_EIS_TENSR 437 -#define FSL_EIS_TENS 438 -#define FSL_EIS_TENC 439 -#define FSL_EIS_PPR32 898 - -/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */ - -#define FSL_EIS_MAS0 624 -#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35)) -#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47)) -#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf) -#define FSL_EIS_MAS0_NV (1 << (63 - 63)) - -#define FSL_EIS_MAS1 625 -#define FSL_EIS_MAS1_V (1 << (63 - 32)) -#define FSL_EIS_MAS1_IPROT (1 << (63 - 33)) -#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47)) -#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff) -#define FSL_EIS_MAS1_TS (1 << (63 - 51)) -#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55)) -#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf) - -#define FSL_EIS_MAS2 626 -#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51)) -#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff) -#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12) -#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12) -#define FSL_EIS_MAS2_X0 (1 << (63 - 57)) -#define FSL_EIS_MAS2_X1 (1 << (63 - 58)) -#define FSL_EIS_MAS2_W (1 << (63 - 59)) -#define FSL_EIS_MAS2_I (1 << (63 - 60)) -#define FSL_EIS_MAS2_M (1 << (63 - 61)) -#define FSL_EIS_MAS2_G (1 << (63 - 62)) -#define FSL_EIS_MAS2_E (1 << (63 - 63)) -#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f) -#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f) - -#define FSL_EIS_MAS3 627 -#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51)) -#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff) -#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12) -#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12) -#define FSL_EIS_MAS3_U0 (1 << (63 - 54)) -#define FSL_EIS_MAS3_U1 (1 << (63 - 55)) -#define FSL_EIS_MAS3_U2 (1 << (63 - 56)) -#define FSL_EIS_MAS3_U3 (1 << (63 - 57)) -#define FSL_EIS_MAS3_UX (1 << (63 - 58)) -#define FSL_EIS_MAS3_SX (1 << (63 - 59)) -#define FSL_EIS_MAS3_UW (1 << (63 - 60)) -#define FSL_EIS_MAS3_SW (1 << (63 - 61)) -#define FSL_EIS_MAS3_UR (1 << (63 - 62)) -#define FSL_EIS_MAS3_SR (1 << (63 - 63)) -#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff) -#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff) - -#define FSL_EIS_MAS4 628 -#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35)) -#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47)) -#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55)) -#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0 -#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1 -#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W -#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I -#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M -#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G -#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E - -#define FSL_EIS_MAS5 629 - -#define FSL_EIS_MAS6 630 -#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55)) -#define FSL_EIS_MAS6_SAS (1 << (63 - 63)) - -#define FSL_EIS_MAS7 944 - -#define FSL_EIS_MAS8 341 - -#define FSL_EIS_MMUCFG 1015 -#define FSL_EIS_MMUCSR0 1012 -#define FSL_EIS_PID0 48 -#define FSL_EIS_PID1 633 -#define FSL_EIS_PID2 634 -#define FSL_EIS_TLB0CFG 688 -#define FSL_EIS_TLB1CFG 689 - -/* Freescale Book E Implementation Standards (EIS): L1 Cache */ - -#define FSL_EIS_L1CFG0 515 -#define FSL_EIS_L1CFG1 516 -#define FSL_EIS_L1CSR0 1010 -#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62)) -#define FSL_EIS_L1CSR1 1011 -#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62)) - -/* Freescale Book E Implementation Standards (EIS): L2 Cache */ - -#define FSL_EIS_L2CFG0 519 -#define FSL_EIS_L2CSR0 1017 -#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42)) -#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52)) -#define FSL_EIS_L2CSR1 1018 - -/* Freescale Book E Implementation Standards (EIS): Timer */ - -#define FSL_EIS_ATBL 526 -#define FSL_EIS_ATBU 527 - -/* Freescale Book E Implementation Standards (EIS): Interrupt */ - -#define FSL_EIS_MCAR 573 -#define FSL_EIS_DSRR0 574 -#define FSL_EIS_DSRR1 575 -#define FSL_EIS_EPR 702 - -/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */ - -#define FSL_EIS_SPEFSCR 512 - -/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */ - -#define FSL_EIS_SPRG8 604 -#define FSL_EIS_SPRG9 605 - -/* Freescale Book E Implementation Standards (EIS): Debug */ - -#define FSL_EIS_DBCR3 561 -#define FSL_EIS_DBCR4 563 -#define FSL_EIS_DBCR5 564 -#define FSL_EIS_DBCR6 603 -#define FSL_EIS_DBCNT 562 - -/** - * @brief Default value for the interrupt disable mask. - * - * The interrupt disable mask is stored in the global symbol - * _PPC_INTERRUPT_DISABLE_MASK. - */ -#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE - -#ifndef ASM - -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define _CPU_MSR_GET( _msr_value ) \ - do { \ - _msr_value = 0; \ - __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -/** - * @brief A global symbol used to disable interrupts in the MSR. - * - * A one bit means that this bit should be cleared. - */ -extern char _PPC_INTERRUPT_DISABLE_MASK[]; - -static inline uint32_t ppc_interrupt_get_disable_mask( void ) -{ - return (uint32_t) (uintptr_t) _PPC_INTERRUPT_DISABLE_MASK; -} - -static inline uint32_t ppc_interrupt_disable( void ) -{ - uint32_t level; - -#if defined(__PPC_CPU_E6500__) - __asm__ volatile ( - "mfmsr %0;" - "wrteei 0" - : "=r" (level) - ); -#else - uint32_t mask; - - __asm__ volatile ( - "mfmsr %0;" - "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;" - "ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;" - "andc %1, %0, %1;" - "mtmsr %1" - : "=r" (level), "=r" (mask) - ); -#endif - - return level; -} - -static inline void ppc_interrupt_enable( uint32_t level ) -{ -#if defined(__PPC_CPU_E6500__) - __asm__ volatile ( - "wrtee %0" - : - : "r" (level) - ); -#else - __asm__ volatile ( - "mtmsr %0" - : - : "r" (level) - ); -#endif -} - -static inline void ppc_interrupt_flash( uint32_t level ) -{ - uint32_t current_level; - - __asm__ volatile ( - "mfmsr %0;" - "mtmsr %1;" - "mtmsr %0" - : "=&r" (current_level) - : "r" (level) - ); -} - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - _isr_cookie = ppc_interrupt_disable(); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - ppc_interrupt_enable(_isr_cookie) - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - * - * NOTE: The version being used is not very optimized but it does - * not trip a problem in gcc where the disable mask does not - * get loaded. Check this for future (post 10/97 gcc versions. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - ppc_interrupt_flash(_isr_cookie) - -/* end of ISR handler macros */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* _RTEMS_POWERPC_REGISTERS_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h deleted file mode 100644 index 8c0f200641..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ /dev/null @@ -1,1257 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Department Source - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * COPYRIGHT (c) 1995 i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Copyright (c) 2001 Andy Dachs . - * - * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). - * - * Copyright (c) 2010, 2017 embedded brains GmbH. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include -#include -#include - -#ifndef ASM - #include /* for memset() */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* conditional compilation parameters */ - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * PowerPC Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef __SPE__ - #define PPC_GPR_TYPE uintptr_t - #if defined(__powerpc64__) - #define PPC_GPR_SIZE 8 - #define PPC_GPR_LOAD ld - #define PPC_GPR_STORE std - #else - #define PPC_GPR_SIZE 4 - #define PPC_GPR_LOAD lwz - #define PPC_GPR_STORE stw - #endif -#else - #define PPC_GPR_TYPE uint64_t - #define PPC_GPR_SIZE 8 - #define PPC_GPR_LOAD evldd - #define PPC_GPR_STORE evstdd -#endif - -#if defined(__powerpc64__) - #define PPC_REG_SIZE 8 - #define PPC_REG_LOAD ld - #define PPC_REG_STORE std - #define PPC_REG_STORE_UPDATE stdu - #define PPC_REG_CMP cmpd -#else - #define PPC_REG_SIZE 4 - #define PPC_REG_LOAD lwz - #define PPC_REG_STORE stw - #define PPC_REG_STORE_UPDATE stwu - #define PPC_REG_CMP cmpw -#endif - -#ifndef ASM - -/* - * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according - * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - - * Linux and Embedded") - */ -typedef struct { - uint32_t msr; - uint32_t cr; - uintptr_t gpr1; - uintptr_t lr; - PPC_GPR_TYPE gpr14; - PPC_GPR_TYPE gpr15; - PPC_GPR_TYPE gpr16; - PPC_GPR_TYPE gpr17; - PPC_GPR_TYPE gpr18; - PPC_GPR_TYPE gpr19; - PPC_GPR_TYPE gpr20; - PPC_GPR_TYPE gpr21; - PPC_GPR_TYPE gpr22; - PPC_GPR_TYPE gpr23; - PPC_GPR_TYPE gpr24; - PPC_GPR_TYPE gpr25; - PPC_GPR_TYPE gpr26; - PPC_GPR_TYPE gpr27; - PPC_GPR_TYPE gpr28; - PPC_GPR_TYPE gpr29; - PPC_GPR_TYPE gpr30; - PPC_GPR_TYPE gpr31; - uint32_t isr_dispatch_disable; - uint32_t reserved_for_alignment; - #if defined(PPC_MULTILIB_ALTIVEC) - uint8_t v20[16]; - uint8_t v21[16]; - uint8_t v22[16]; - uint8_t v23[16]; - uint8_t v24[16]; - uint8_t v25[16]; - uint8_t v26[16]; - uint8_t v27[16]; - uint8_t v28[16]; - uint8_t v29[16]; - uint8_t v30[16]; - uint8_t v31[16]; - uint32_t vrsave; - #elif defined(__ALTIVEC__) - /* - * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave - * and padding to ensure cache-alignment. Unfortunately, we can't verify - * the cache line size here in the cpukit but altivec support code will - * produce an error if this is ever different from 32 bytes. - * - * Note: it is the BSP/CPU-support's responsibility to save/restore - * volatile vregs across interrupts and exceptions. - */ - uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; - #endif - #if defined(PPC_MULTILIB_FPU) - double f14; - double f15; - double f16; - double f17; - double f18; - double f19; - double f20; - double f21; - double f22; - double f23; - double f24; - double f25; - double f26; - double f27; - double f28; - double f29; - double f30; - double f31; - #endif - /* - * The following items are at the structure end, so that we can use dcbz for - * the previous items to optimize the context switch. We must not set the - * following items to zero via the dcbz. - */ - uintptr_t tp; - #if defined(RTEMS_SMP) - volatile uint32_t is_executing; - #endif -} ppc_context; - -typedef struct { - uint8_t context [ - PPC_DEFAULT_CACHE_LINE_SIZE - + sizeof(ppc_context) - + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 - ? 0 - : PPC_DEFAULT_CACHE_LINE_SIZE - - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) - ]; -} Context_Control; - -static inline ppc_context *ppc_get_context( const Context_Control *context ) -{ - uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; - uintptr_t mask = clsz - 1; - uintptr_t addr = (uintptr_t) context; - - return (ppc_context *) ((addr & ~mask) + clsz); -} - -#define _CPU_Context_Get_SP( _context ) \ - ppc_get_context(_context)->gpr1 - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return ppc_get_context(context)->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - ppc_get_context(context)->is_executing = is_executing; - } -#endif -#endif /* ASM */ - -#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE) -#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) -#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8) -#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8) - -#define PPC_CONTEXT_GPR_OFFSET( gpr ) \ - (((gpr) - 14) * PPC_GPR_SIZE + \ - PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE) - -#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) -#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) -#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) -#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) -#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) -#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) -#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) -#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) -#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) -#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) -#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) -#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) -#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) -#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) -#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) -#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) -#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) -#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) -#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 ) - -#ifdef PPC_MULTILIB_ALTIVEC - #define PPC_CONTEXT_OFFSET_V( v ) \ - ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8) - #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) - #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) - #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) - #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) - #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) - #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) - #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) - #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) - #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) - #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) - #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) - #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) - #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 ) -#else - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 ) -#endif - -#ifdef PPC_MULTILIB_FPU - #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) - #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) - #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) - #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) - #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) - #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) - #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) - #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) - #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) - #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) - #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) - #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) - #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) - #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) - #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) - #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) - #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) - #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) -#endif - -#if defined(PPC_MULTILIB_FPU) - #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) -#elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) -#elif defined(__ALTIVEC__) - #define PPC_CONTEXT_VOLATILE_SIZE \ - (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \ - + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE) -#else - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8) -#endif - -#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE - -#ifdef RTEMS_SMP - #define PPC_CONTEXT_OFFSET_IS_EXECUTING \ - (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE) -#endif - -#ifndef ASM -typedef struct { -#if (PPC_HAS_FPU == 1) - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - uint64_t fpscr; -#else - float f[32]; - uint32_t fpscr; -#endif -#endif /* (PPC_HAS_FPU == 1) */ -} Context_Control_fp; - -#endif /* ASM */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Note, however that compilers may use floating point registers/ - * instructions for optimization or they may save/restore FP registers - * on the stack. You must not use deferred switching in these cases - * and on the PowerPC attempting to do so will raise a "FP unavailable" - * exception. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -/* conservative setting (FALSE); probably doesn't affect performance too much */ -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Processor defined structures required for cpukit/score. - */ - -#ifndef ASM - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -#endif /* ndef ASM */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_PATTERN_INITIALIZER \ - { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 } - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. Note that - * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level - * being maintained (e.g. watchdog queues). - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * ISR handler macros - */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#ifndef ASM - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & MSR_EE ) != 0; -} - -static inline uint32_t _CPU_ISR_Get_level( void ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (msr & MSR_EE) return 0; - else return 1; -} - -static inline void _CPU_ISR_Set_level( uint32_t level ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (!(level & CPU_MODES_INTERRUPT_MASK)) { - msr |= ppc_interrupt_get_disable_mask(); - } - else { - msr &= ~ppc_interrupt_get_disable_mask(); - } - _CPU_MSR_SET(msr); -} - -#endif /* ASM */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - ppc_interrupt_disable(); \ - __asm__ volatile ( \ - "mr 3, %0\n" \ - "mr 4, %1\n" \ - "1:\n" \ - "b 1b\n" \ - : \ - : "r" (_source), "r" (_error) \ - : "memory" \ - ); \ - } while ( 0 ) - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#if defined(__powerpc64__) -#define CPU_SIZEOF_POINTER 8 -#else -#define CPU_SIZEOF_POINTER 4 -#endif - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -#ifndef ASM -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t swapped; - - __asm__ volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=&r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - CPU_Counter_ticks value; - -#if defined(__PPC_CPU_E6500__) - /* Use Alternate Time Base */ - __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); -#else - __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); -#endif - - return value; -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - - -#ifndef ASM -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *(_destination), 0, sizeof( **(_destination) ) ) - -/* end of Context handler macros */ -#endif /* ASM */ - -#ifndef ASM -/* Bitfield handler macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - (_output) = (_output) - 16; \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000u >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ -#endif /* ASM */ - -/* functions */ - -#ifndef ASM - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t pir; - - /* Use Book E Processor ID Register (PIR) */ - __asm__ volatile ( - "mfspr %[pir], 286" - : [pir] "=&r" (pir) - ); - - return pir; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -typedef struct { - uintptr_t EXC_SRR0; - uintptr_t EXC_SRR1; - uint32_t _EXC_number; - uint32_t RESERVED_FOR_ALIGNMENT_0; - uint32_t EXC_CR; - uint32_t EXC_XER; - uintptr_t EXC_CTR; - uintptr_t EXC_LR; - uintptr_t RESERVED_FOR_ALIGNMENT_1; - #ifdef __SPE__ - uint32_t EXC_SPEFSCR; - uint64_t EXC_ACC; - #endif - PPC_GPR_TYPE GPR0; - PPC_GPR_TYPE GPR1; - PPC_GPR_TYPE GPR2; - PPC_GPR_TYPE GPR3; - PPC_GPR_TYPE GPR4; - PPC_GPR_TYPE GPR5; - PPC_GPR_TYPE GPR6; - PPC_GPR_TYPE GPR7; - PPC_GPR_TYPE GPR8; - PPC_GPR_TYPE GPR9; - PPC_GPR_TYPE GPR10; - PPC_GPR_TYPE GPR11; - PPC_GPR_TYPE GPR12; - PPC_GPR_TYPE GPR13; - PPC_GPR_TYPE GPR14; - PPC_GPR_TYPE GPR15; - PPC_GPR_TYPE GPR16; - PPC_GPR_TYPE GPR17; - PPC_GPR_TYPE GPR18; - PPC_GPR_TYPE GPR19; - PPC_GPR_TYPE GPR20; - PPC_GPR_TYPE GPR21; - PPC_GPR_TYPE GPR22; - PPC_GPR_TYPE GPR23; - PPC_GPR_TYPE GPR24; - PPC_GPR_TYPE GPR25; - PPC_GPR_TYPE GPR26; - PPC_GPR_TYPE GPR27; - PPC_GPR_TYPE GPR28; - PPC_GPR_TYPE GPR29; - PPC_GPR_TYPE GPR30; - PPC_GPR_TYPE GPR31; - uintptr_t RESERVED_FOR_ALIGNMENT_2; - #ifdef PPC_MULTILIB_ALTIVEC - uint32_t VRSAVE; - uint32_t RESERVED_FOR_ALIGNMENT_3[3]; - - /* This field must take stvewx/lvewx requirements into account */ - uint32_t RESERVED_FOR_ALIGNMENT_4[3]; - uint32_t VSCR; - - uint8_t V0[16]; - uint8_t V1[16]; - uint8_t V2[16]; - uint8_t V3[16]; - uint8_t V4[16]; - uint8_t V5[16]; - uint8_t V6[16]; - uint8_t V7[16]; - uint8_t V8[16]; - uint8_t V9[16]; - uint8_t V10[16]; - uint8_t V11[16]; - uint8_t V12[16]; - uint8_t V13[16]; - uint8_t V14[16]; - uint8_t V15[16]; - uint8_t V16[16]; - uint8_t V17[16]; - uint8_t V18[16]; - uint8_t V19[16]; - uint8_t V20[16]; - uint8_t V21[16]; - uint8_t V22[16]; - uint8_t V23[16]; - uint8_t V24[16]; - uint8_t V25[16]; - uint8_t V26[16]; - uint8_t V27[16]; - uint8_t V28[16]; - uint8_t V29[16]; - uint8_t V30[16]; - uint8_t V31[16]; - #endif - #ifdef PPC_MULTILIB_FPU - double F0; - double F1; - double F2; - double F3; - double F4; - double F5; - double F6; - double F7; - double F8; - double F9; - double F10; - double F11; - double F12; - double F13; - double F14; - double F15; - double F16; - double F17; - double F18; - double F19; - double F20; - double F21; - double F22; - double F23; - double F24; - double F25; - double F26; - double F27; - double F28; - double F29; - double F30; - double F31; - uint64_t FPSCR; - uint64_t RESERVED_FOR_ALIGNMENT_5; - #endif -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * _CPU_Initialize_altivec() - * - * Global altivec-related initialization. - */ -void -_CPU_Initialize_altivec(void); - -/* - * _CPU_Context_switch_altivec - * - * This routine switches the altivec contexts passed to it. - */ - -void -_CPU_Context_switch_altivec( - ppc_context *from, - ppc_context *to -); - -/* - * _CPU_Context_restore_altivec - * - * This routine restores the altivec context passed to it. - */ - -void -_CPU_Context_restore_altivec( - ppc_context *ctxt -); - -/* - * _CPU_Context_initialize_altivec - * - * This routine initializes the altivec context passed to it. - */ - -void -_CPU_Context_initialize_altivec( - ppc_context *ctxt -); - -void _CPU_Fatal_error( - uint32_t _error -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h b/cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h deleted file mode 100644 index 792a8111ad..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Copyright (C) 2007 Till Straumann - * - * Copyright (c) 2009, 2017 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -/* Exception stack frame -> BSP_Exception_frame */ -#ifdef __powerpc64__ - #define FRAME_LINK_SPACE 32 -#else - #define FRAME_LINK_SPACE 8 -#endif - -#define SRR0_FRAME_OFFSET FRAME_LINK_SPACE -#define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE) -#define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE) -#define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4) -#define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8) -#define EXC_XER_OFFSET (EXC_CR_OFFSET + 4) -#define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4) -#define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE) -#define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE) - -#ifndef __SPE__ - #define PPC_EXC_GPR_OFFSET(gpr) \ - ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) - #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3) - #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) - #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) - #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) - #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) - #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32)) - #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) - #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) - #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) - #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) - #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20)) - #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) - #elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) - #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) - #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) - #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32) - #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) - #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE) - #elif defined(PPC_MULTILIB_FPU) - #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33)) - #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) - #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) - #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13)) - #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) - #else - #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE) - #endif -#else - #define PPC_EXC_SPEFSCR_OFFSET 44 - #define PPC_EXC_ACC_OFFSET 48 - #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) - #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4) - #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) - #define PPC_EXC_FRAME_SIZE 320 -#endif - -#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0) -#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1) -#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2) -#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3) -#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4) -#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5) -#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6) -#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7) -#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8) -#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9) -#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10) -#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11) -#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12) -#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13) -#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14) -#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15) -#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16) -#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17) -#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18) -#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19) -#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20) -#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21) -#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22) -#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23) -#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24) -#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25) -#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26) -#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27) -#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28) -#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29) -#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30) -#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31) - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifdef RTEMS_SMP - -/* Use SPRG0 for the per-CPU control of the current processor */ -#define PPC_PER_CPU_CONTROL_REGISTER 272 - -#endif /* RTEMS_SMP */ - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uintptr_t FRAME_SP; - #ifdef __powerpc64__ - uint32_t FRAME_CR; - uint32_t FRAME_RESERVED; - #endif - uintptr_t FRAME_LR; - #ifdef __powerpc64__ - uintptr_t FRAME_TOC; - #endif - uintptr_t EXC_SRR0; - uintptr_t EXC_SRR1; - uint32_t RESERVED_FOR_ALIGNMENT_0; - uint32_t EXC_INTERRUPT_ENTRY_INSTANT; - uint32_t EXC_CR; - uint32_t EXC_XER; - uintptr_t EXC_CTR; - uintptr_t EXC_LR; - uintptr_t EXC_INTERRUPT_FRAME; - #ifdef __SPE__ - uint32_t EXC_SPEFSCR; - uint64_t EXC_ACC; - #endif - PPC_GPR_TYPE GPR0; - PPC_GPR_TYPE GPR1; - PPC_GPR_TYPE GPR2; - PPC_GPR_TYPE GPR3; - PPC_GPR_TYPE GPR4; - PPC_GPR_TYPE GPR5; - PPC_GPR_TYPE GPR6; - PPC_GPR_TYPE GPR7; - PPC_GPR_TYPE GPR8; - PPC_GPR_TYPE GPR9; - PPC_GPR_TYPE GPR10; - PPC_GPR_TYPE GPR11; - PPC_GPR_TYPE GPR12; - #ifdef PPC_MULTILIB_ALTIVEC - /* This field must take stvewx/lvewx requirements into account */ - uint32_t RESERVED_FOR_ALIGNMENT_3[3]; - uint32_t VSCR; - - uint8_t V0[16]; - uint8_t V1[16]; - uint8_t V2[16]; - uint8_t V3[16]; - uint8_t V4[16]; - uint8_t V5[16]; - uint8_t V6[16]; - uint8_t V7[16]; - uint8_t V8[16]; - uint8_t V9[16]; - uint8_t V10[16]; - uint8_t V11[16]; - uint8_t V12[16]; - uint8_t V13[16]; - uint8_t V14[16]; - uint8_t V15[16]; - uint8_t V16[16]; - uint8_t V17[16]; - uint8_t V18[16]; - uint8_t V19[16]; - #endif - #ifdef PPC_MULTILIB_FPU - double F0; - double F1; - double F2; - double F3; - double F4; - double F5; - double F6; - double F7; - double F8; - double F9; - double F10; - double F11; - double F12; - double F13; - uint64_t FPSCR; - uint64_t RESERVED_FOR_ALIGNMENT_4; - #endif - #if PPC_STACK_RED_ZONE_SIZE > 0 - uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ]; - #endif -} CPU_Interrupt_frame; - -#ifdef RTEMS_SMP - -static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void ) -{ - struct Per_CPU_Control *cpu_self; - - __asm__ volatile ( - "mfspr %0, " RTEMS_XSTRING( PPC_PER_CPU_CONTROL_REGISTER ) - : "=r" ( cpu_self ) - ); - - return cpu_self; -} - -#define _CPU_Get_current_per_CPU_control() _PPC_Get_current_per_CPU_control() - -#endif /* RTEMS_SMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h deleted file mode 100644 index 88ee0020e6..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h +++ /dev/null @@ -1,187 +0,0 @@ -/** - * @file - * - * @brief IBM/Motorola Power Pc Definitions - * - * This file contains definitions for the IBM/Motorola PowerPC - * family members. - */ - -/* - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * MPC860 support code was added by Jay Monkman - * MPC8260 support added by Andy Dachs - * Surrey Satellite Technology Limited - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - */ - - -#ifndef _RTEMS_SCORE_POWERPC_H -#define _RTEMS_SCORE_POWERPC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "PowerPC" - -/* - * This file contains the information required to build - * RTEMS for the PowerPC family. - */ - -/* Generic ppc */ - -#ifdef _SOFT_FLOAT -#define CPU_MODEL_NAME "Generic (no FPU)" -#elif defined(__NO_FPRS__) || defined(__SPE__) -#define CPU_MODEL_NAME "Generic (E500/float-gprs/SPE)" -#else -#define CPU_MODEL_NAME "Generic (classic FPU)" -#endif - -#ifdef __PPC_CPU_E6500__ -#define PPC_DEFAULT_CACHE_LINE_POWER 6 -#else -#define PPC_DEFAULT_CACHE_LINE_POWER 5 -#endif - -#define PPC_DEFAULT_CACHE_LINE_SIZE (1 << PPC_DEFAULT_CACHE_LINE_POWER) - -#define PPC_STRUCTURE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE - -/* - * Application binary interfaces. - * - * PPC_ABI MUST be defined as one of these. - * Only big endian is currently supported. - */ - -/* - * SVR4 ABI - */ -#define PPC_ABI_SVR4 2 -/* - * Embedded ABI - */ -#define PPC_ABI_EABI 3 - -/* - * Default to the EABI used by current GNU tools - */ - -#ifndef PPC_ABI -#define PPC_ABI PPC_ABI_EABI -#endif - -/* - * Use worst case stack alignment. For the EABI an 8-byte alignment would be - * sufficient. - */ - -#define PPC_STACK_ALIGN_POWER 4 -#define PPC_STACK_ALIGNMENT (1 << PPC_STACK_ALIGN_POWER) - -/* - * Assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT. - */ - -#if defined(_SOFT_FLOAT) \ - || defined(__NO_FPRS__) /* e500 has unified integer/FP registers */ \ - || defined(__PPC_CPU_E6500__) -#define PPC_HAS_FPU 0 -#else -#define PPC_HAS_FPU 1 -#endif - -#if defined(__PPC_CPU_E6500__) && defined(__ALTIVEC__) -#define PPC_MULTILIB_ALTIVEC -#endif - -#if defined(__PPC_CPU_E6500__) && !defined(_SOFT_FLOAT) -#define PPC_MULTILIB_FPU -#endif - -#ifdef PPC_MULTILIB_ALTIVEC -#define PPC_ALIGNMENT 16 -#else -#define PPC_ALIGNMENT 8 -#endif - -#ifdef __powerpc64__ -#define PPC_STACK_RED_ZONE_SIZE 512 -#else -#define PPC_STACK_RED_ZONE_SIZE 0 -#endif - -/* - * Unless specified above, If the model has FP support, it is assumed to - * support doubles (8-byte floating point numbers). - * - * If the model does NOT have FP support, then the model does - * NOT have double length FP registers. - */ - -#if (PPC_HAS_FPU) -#define PPC_HAS_DOUBLE 1 -#else -#define PPC_HAS_DOUBLE 0 -#endif - -/* - * Assemblers. - * PPC_ASM MUST be defined as one of these. - * - * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. - * - * NOTE: Only PPC_ABI_ELF is currently fully supported. - * - * Also NOTE: cpukit doesn't need this but asm.h which is defined - * in cpukit for consistency with other ports does. - */ - -#define PPC_ASM_ELF 0 - -/* - * Default to the assembler format used by the current GNU tools. - */ -#define PPC_ASM PPC_ASM_ELF - - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_POWERPC_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/types.h b/cpukit/score/cpu/powerpc/rtems/score/types.h deleted file mode 100644 index cdab30234d..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/types.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Type Definitions - * - * This include file contains type definitions pertaining to the PowerPC - * processor family. - */ - -/* - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void ppc_isr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/riscv/Makefile.am b/cpukit/score/cpu/riscv/Makefile.am index 1de5b2da42..3630c038a7 100644 --- a/cpukit/score/cpu/riscv/Makefile.am +++ b/cpukit/score/cpu/riscv/Makefile.am @@ -1,16 +1,4 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/riscv.h -include_rtems_score_HEADERS += rtems/score/riscv-utility.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) libscorecpu_a_SOURCES = cpu.c @@ -22,5 +10,5 @@ libscorecpu_a_SOURCES += riscv-context-initialize.c libscorecpu_a_SOURCES += riscv-context-validate.S libscorecpu_a_SOURCES += riscv-context-volatile-clobber.S -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/riscv/headers.am b/cpukit/score/cpu/riscv/headers.am new file mode 100644 index 0000000000..b5d3295c33 --- /dev/null +++ b/cpukit/score/cpu/riscv/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/riscv-utility.h +include_rtems_score_HEADERS += include/rtems/score/riscv.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h new file mode 100644 index 0000000000..34b6474515 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/asm.h @@ -0,0 +1,120 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __RISCV_ASM_H +#define __RISCV_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .extern SYM (sym) +#define TYPE_FUNC(sym) .type SYM (sym), %function + +#endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h new file mode 100644 index 0000000000..3f8af862bf --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -0,0 +1,604 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RISCV_CPU_H +#define _RISCV_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* pick up machine definitions */ +#include +#include +#ifndef ASM +#include +#include +#include /* for printk */ +#endif + +#define CPU_INLINE_ENABLE_DISPATCH FALSE +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE +#define CPU_ISR_PASSES_FRAME_POINTER 1 +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE +#define CPU_ALL_TASKS_ARE_FP FALSE +#define CPU_IDLE_TASK_IS_FP FALSE +#define CPU_USE_DEFERRED_FP_SWITCH FALSE +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE +#define CPU_STACK_GROWS_UP FALSE + +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) +#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE +#define CPU_BIG_ENDIAN FALSE +#define CPU_LITTLE_ENDIAN TRUE +#define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 + +/* + * Processor defined structures required for cpukit/score. + */ + +#ifndef ASM + +typedef struct { + /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/ + unsigned long x[32]; + + /* Special purpose registers */ + unsigned long mstatus; + unsigned long mcause; + unsigned long mepc; +#ifdef RTEMS_SMP + /** + * @brief On SMP configurations the thread context must contain a boolean + * indicator to signal if this context is executing on a processor. + * + * This field must be updated during a context switch. The context switch + * to the heir must wait until the heir context indicates that it is no + * longer executing on a processor. The context switch must also check if + * a thread dispatch is necessary to honor updates of the heir thread for + * this processor. This indicator must be updated using an atomic test and + * set operation to ensure that at most one processor uses the heir + * context at the same time. + * + * @code + * void _CPU_Context_switch( + * Context_Control *executing, + * Context_Control *heir + * ) + * { + * save( executing ); + * + * executing->is_executing = false; + * memory_barrier(); + * + * if ( test_and_set( &heir->is_executing ) ) { + * do { + * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); + * + * if ( cpu_self->dispatch_necessary ) { + * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); + * } + * } while ( test_and_set( &heir->is_executing ) ); + * } + * + * restore( heir ); + * } + * @endcode + */ + volatile bool is_executing; +#endif +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->x[2] + +typedef struct { + /** TODO FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +typedef Context_Control CPU_Interrupt_frame; + +#define CPU_CONTEXT_FP_SIZE 0 +Context_Control_fp _CPU_Null_fp_context; + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 +#if __riscv_xlen == 32 +#define CPU_STACK_MINIMUM_SIZE 4096 +#else +#define CPU_STACK_MINIMUM_SIZE 4096 * 2 +#endif +#define CPU_ALIGNMENT 8 +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT +#define CPU_STACK_ALIGNMENT 8 +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + * + */ + +static inline unsigned long riscv_interrupt_disable( void ) +{ + register unsigned long status = read_csr(mstatus); + clear_csr(mstatus, MSTATUS_MIE); + return status; +} + +static inline void riscv_interrupt_enable(unsigned long level) +{ + write_csr(mstatus, level); +} + +#define _CPU_ISR_Disable( _level ) \ + _level = riscv_interrupt_disable() + +#define _CPU_ISR_Enable( _level ) \ + riscv_interrupt_enable( _level ) + +#define _CPU_ISR_Flash( _level ) \ + do{ \ + _CPU_ISR_Enable( _level ); \ + riscv_interrupt_disable(); \ + } while(0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) +{ + return ( level & MSTATUS_MIE ) != 0; +} + +void _CPU_ISR_Set_level( unsigned long level ); + +unsigned long _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ +#define RISCV_GCC_RED_ZONE_SIZE 128 + +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + unsigned long new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ) + + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + (_output) = 0; /* do something to prevent warnings */ \ + } +#endif + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + * + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + (1 << _bit_number) + +#endif + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +#define CPU_MAXIMUM_PROCESSORS 32 + +#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE +#define CPU_TIMESTAMP_USE_INT64 TRUE +#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE + +typedef struct { + /* There is no CPU specific per-CPU state */ +} CPU_Per_CPU_control; +#endif /* ASM */ + +#if __riscv_xlen == 32 +#define CPU_SIZEOF_POINTER 4 + +/* 32-bit load/store instructions */ +#define LREG lw +#define SREG sw + +#define CPU_EXCEPTION_FRAME_SIZE 128 +#else /* xlen = 64 */ +#define CPU_SIZEOF_POINTER 8 + +/* 64-bit load/store instructions */ +#define LREG ld +#define SREG sd + +#define CPU_EXCEPTION_FRAME_SIZE 256 +#endif + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM +typedef uint16_t Priority_bit_map_Word; + +typedef struct { + unsigned long x[32];; +} CPU_Exception_frame; + +/** + * @brief Prints the exception frame via printk(). + * + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. + */ +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + * + */ + +void _CPU_Initialize( + void +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + unsigned long vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + * + * RISCV Specific Information: + * + * Please see the comments in the .c file for a description of how + * this function works. There are several things to be aware of. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + * + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + * + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to insure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + */ + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return ( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +#ifdef RTEMS_SMP +/** + * @brief Performs CPU specific SMP initialization in the context of the boot + * processor. + * + * This function is invoked on the boot processor during system + * initialization. All interrupt stacks are allocated at this point in case + * the CPU port allocates the interrupt stacks. This function is called + * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is + * used. + * + * @return The count of physically or virtually available processors. + * Depending on the configuration the application may use not all processors. + */ +uint32_t _CPU_SMP_Initialize( void ); + +/** + * @brief Starts a processor specified by its index. + * + * This function is invoked on the boot processor during system + * initialization. + * + * This function will be called after _CPU_SMP_Initialize(). + * + * @param[in] cpu_index The processor index. + * + * @retval true Successful operation. + * @retval false Unable to start this processor. + */ +bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + +/** + * @brief Performs final steps of CPU specific SMP initialization in the + * context of the boot processor. + * + * This function is invoked on the boot processor during system + * initialization. + * + * This function will be called after all processors requested by the + * application have been started. + * + * @param[in] cpu_count The minimum value of the count of processors + * requested by the application configuration and the count of physically or + * virtually available processors. + */ +void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + +/** + * @brief Returns the index of the current processor. + * + * An architecture specific method must be used to obtain the index of the + * current processor in the system. The set of processor indices is the + * range of integers starting with zero up to the processor count minus one. + */ +uint32_t _CPU_SMP_Get_current_processor( void ); + +/** + * @brief Sends an inter-processor interrupt to the specified target + * processor. + * + * This operation is undefined for target processor indices out of range. + * + * @param[in] target_processor_index The target processor index. + */ +void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + +/** + * @brief Broadcasts a processor event. + * + * Some architectures provide a low-level synchronization primitive for + * processors in a multi-processor environment. Processors waiting for this + * event may go into a low-power state and stop generating system bus + * transactions. This function must ensure that preceding store operations + * can be observed by other processors. + * + * @see _CPU_SMP_Processor_event_receive(). + */ +void _CPU_SMP_Processor_event_broadcast( void ); + +/** + * @brief Receives a processor event. + * + * This function will wait for the processor event and may wait forever if no + * such event arrives. + * + * @see _CPU_SMP_Processor_event_broadcast(). + */ +static inline void _CPU_SMP_Processor_event_receive( void ) +{ + __asm__ volatile ( "" : : : "memory" ); +} + +/** + * @brief Gets the is executing indicator of the thread context. + * + * @param[in] context The context. + */ +static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context +) +{ + return context->is_executing; +} + +/** + * @brief Sets the is executing indicator of the thread context. + * + * @param[in] context The context. + * @param[in] is_executing The new value for the is executing indicator. + */ +static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing +) +{ + context->is_executing = is_executing; +} +#endif /* RTEMS_SMP */ + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..b5a56f3e22 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu_asm.h @@ -0,0 +1,90 @@ +/** + * @file + * + * @brief riscv32 Assembly File + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +/* +#include +*/ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..8ee9606b44 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h @@ -0,0 +1,31 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..3904c84bf9 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h new file mode 100644 index 0000000000..dc4836bee2 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h @@ -0,0 +1,1526 @@ +/* Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST + * PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +/** + * @file + * + * @brief RISCV utility + */ +/* + * COPYRIGHT (c) 2015 Hesham Almatary + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* This file is copied from riscv-tools/encoding.h with additions/modifications to work + * with RTEMS. + */ +#ifndef _RTEMS_SCORE_RISCV_UTILITY_H +#define _RTEMS_SCORE_RISCV_UTILITY_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SPTBR32_MODE 0x80000000 +#define SPTBR32_ASID 0x7FC00000 +#define SPTBR32_PPN 0x003FFFFF +#define SPTBR64_MODE 0xF000000000000000 +#define SPTBR64_ASID 0x0FFFF00000000000 +#define SPTBR64_PPN 0x00000FFFFFFFFFFF + +#define SPTBR_MODE_OFF 0 +#define SPTBR_MODE_SV32 1 +#define SPTBR_MODE_SV39 8 +#define SPTBR_MODE_SV48 9 +#define SPTBR_MODE_SV57 10 +#define SPTBR_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SPTBR_MODE SPTBR64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SPTBR_MODE SPTBR32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +/** + * @brief Priv Mode registers definitions. + * + * @see RISC-V priv-spec 1.10. + */ +typedef enum { + RISCV_USER_INTERRUPT = 0, + RISCV_SUPERVISOR_SW_INTERRUPT = 1, + RISCV_MACHINE_SW_INTERRUPT = 3, + RISCV_USER_TIMER_INTERRUPT = 4, + RISCV_SUPERVISOR_TIMER_INTERRUPT = 4, + RISCV_MACHINE_TIMER_INTERRUPT = 7, + RISCV_USER_EXTERNAL_INTERRUPT = 8, + RISCV_SUPERVISOR_EXTERNAL_INTERRUPT = 9, + RISCV_MACHINE_EXTERNAL_INTERRUPT = 11 +} RISCV_Symbolic_interrupt_name; + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN( or , MATCH_OR, MASK_OR) +DECLARE_INSN( and , MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv.h b/cpukit/score/cpu/riscv/include/rtems/score/riscv.h new file mode 100644 index 0000000000..6e7f1370c6 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv.h @@ -0,0 +1,66 @@ +/** + * @file rtems/score/riscv.h + */ + +/* + * This file contains information pertaining to the riscv32 processor. + * + * COPYRIGHT (c) 2014 Hesham Almatary + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_RISCV_H +#define _RTEMS_SCORE_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the RISCV family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +/* +* Define the name of the CPU family and specific model. +*/ + +#define CPU_NAME "RISCV" +#define CPU_MODEL_NAME "RISCV" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_RISCV_H */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/types.h b/cpukit/score/cpu/riscv/include/rtems/score/types.h new file mode 100644 index 0000000000..d1440fb319 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/types.h @@ -0,0 +1,70 @@ +/** + * @file + * + * @brief RISC-V Architecture Types API + */ + +/* + * This include file contains type definitions pertaining to the + * RISC-V processor family. + * + * COPYRIGHT (c) 2014 Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + */ +/**@{**/ + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef uint16_t Priority_bit_map_Word; +typedef void riscv_isr; +typedef void ( *riscv_isr_entry )( void ); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/riscv/preinstall.am b/cpukit/score/cpu/riscv/preinstall.am deleted file mode 100644 index 14256ba876..0000000000 --- a/cpukit/score/cpu/riscv/preinstall.am +++ /dev/null @@ -1,57 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/riscv.h: rtems/score/riscv.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/riscv.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/riscv.h - -$(PROJECT_INCLUDE)/rtems/score/riscv-utility.h: rtems/score/riscv-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/riscv-utility.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/riscv-utility.h - diff --git a/cpukit/score/cpu/riscv/rtems/asm.h b/cpukit/score/cpu/riscv/rtems/asm.h deleted file mode 100644 index 34b6474515..0000000000 --- a/cpukit/score/cpu/riscv/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef __RISCV_ASM_H -#define __RISCV_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .extern SYM (sym) -#define TYPE_FUNC(sym) .type SYM (sym), %function - -#endif diff --git a/cpukit/score/cpu/riscv/rtems/score/cpu.h b/cpukit/score/cpu/riscv/rtems/score/cpu.h deleted file mode 100644 index 3f8af862bf..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/cpu.h +++ /dev/null @@ -1,604 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RISCV_CPU_H -#define _RISCV_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include /* pick up machine definitions */ -#include -#include -#ifndef ASM -#include -#include -#include /* for printk */ -#endif - -#define CPU_INLINE_ENABLE_DISPATCH FALSE -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE -#define CPU_ISR_PASSES_FRAME_POINTER 1 -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#define CPU_STACK_GROWS_UP FALSE - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 - -/* - * Processor defined structures required for cpukit/score. - */ - -#ifndef ASM - -typedef struct { - /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/ - unsigned long x[32]; - - /* Special purpose registers */ - unsigned long mstatus; - unsigned long mcause; - unsigned long mepc; -#ifdef RTEMS_SMP - /** - * @brief On SMP configurations the thread context must contain a boolean - * indicator to signal if this context is executing on a processor. - * - * This field must be updated during a context switch. The context switch - * to the heir must wait until the heir context indicates that it is no - * longer executing on a processor. The context switch must also check if - * a thread dispatch is necessary to honor updates of the heir thread for - * this processor. This indicator must be updated using an atomic test and - * set operation to ensure that at most one processor uses the heir - * context at the same time. - * - * @code - * void _CPU_Context_switch( - * Context_Control *executing, - * Context_Control *heir - * ) - * { - * save( executing ); - * - * executing->is_executing = false; - * memory_barrier(); - * - * if ( test_and_set( &heir->is_executing ) ) { - * do { - * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); - * - * if ( cpu_self->dispatch_necessary ) { - * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); - * } - * } while ( test_and_set( &heir->is_executing ) ); - * } - * - * restore( heir ); - * } - * @endcode - */ - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->x[2] - -typedef struct { - /** TODO FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -#define CPU_CONTEXT_FP_SIZE 0 -Context_Control_fp _CPU_Null_fp_context; - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 -#if __riscv_xlen == 32 -#define CPU_STACK_MINIMUM_SIZE 4096 -#else -#define CPU_STACK_MINIMUM_SIZE 4096 * 2 -#endif -#define CPU_ALIGNMENT 8 -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT -#define CPU_STACK_ALIGNMENT 8 -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline unsigned long riscv_interrupt_disable( void ) -{ - register unsigned long status = read_csr(mstatus); - clear_csr(mstatus, MSTATUS_MIE); - return status; -} - -static inline void riscv_interrupt_enable(unsigned long level) -{ - write_csr(mstatus, level); -} - -#define _CPU_ISR_Disable( _level ) \ - _level = riscv_interrupt_disable() - -#define _CPU_ISR_Enable( _level ) \ - riscv_interrupt_enable( _level ) - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - _CPU_ISR_Enable( _level ); \ - riscv_interrupt_disable(); \ - } while(0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) -{ - return ( level & MSTATUS_MIE ) != 0; -} - -void _CPU_ISR_Set_level( unsigned long level ); - -unsigned long _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ -#define RISCV_GCC_RED_ZONE_SIZE 128 - -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - unsigned long new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ) - - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - (1 << _bit_number) - -#endif - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_MAXIMUM_PROCESSORS 32 - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; -#endif /* ASM */ - -#if __riscv_xlen == 32 -#define CPU_SIZEOF_POINTER 4 - -/* 32-bit load/store instructions */ -#define LREG lw -#define SREG sw - -#define CPU_EXCEPTION_FRAME_SIZE 128 -#else /* xlen = 64 */ -#define CPU_SIZEOF_POINTER 8 - -/* 64-bit load/store instructions */ -#define LREG ld -#define SREG sd - -#define CPU_EXCEPTION_FRAME_SIZE 256 -#endif - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM -typedef uint16_t Priority_bit_map_Word; - -typedef struct { - unsigned long x[32];; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned long vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * RISCV Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return ( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -#ifdef RTEMS_SMP -/** - * @brief Performs CPU specific SMP initialization in the context of the boot - * processor. - * - * This function is invoked on the boot processor during system - * initialization. All interrupt stacks are allocated at this point in case - * the CPU port allocates the interrupt stacks. This function is called - * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is - * used. - * - * @return The count of physically or virtually available processors. - * Depending on the configuration the application may use not all processors. - */ -uint32_t _CPU_SMP_Initialize( void ); - -/** - * @brief Starts a processor specified by its index. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after _CPU_SMP_Initialize(). - * - * @param[in] cpu_index The processor index. - * - * @retval true Successful operation. - * @retval false Unable to start this processor. - */ -bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - -/** - * @brief Performs final steps of CPU specific SMP initialization in the - * context of the boot processor. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after all processors requested by the - * application have been started. - * - * @param[in] cpu_count The minimum value of the count of processors - * requested by the application configuration and the count of physically or - * virtually available processors. - */ -void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - -/** - * @brief Returns the index of the current processor. - * - * An architecture specific method must be used to obtain the index of the - * current processor in the system. The set of processor indices is the - * range of integers starting with zero up to the processor count minus one. - */ -uint32_t _CPU_SMP_Get_current_processor( void ); - -/** - * @brief Sends an inter-processor interrupt to the specified target - * processor. - * - * This operation is undefined for target processor indices out of range. - * - * @param[in] target_processor_index The target processor index. - */ -void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - -/** - * @brief Broadcasts a processor event. - * - * Some architectures provide a low-level synchronization primitive for - * processors in a multi-processor environment. Processors waiting for this - * event may go into a low-power state and stop generating system bus - * transactions. This function must ensure that preceding store operations - * can be observed by other processors. - * - * @see _CPU_SMP_Processor_event_receive(). - */ -void _CPU_SMP_Processor_event_broadcast( void ); - -/** - * @brief Receives a processor event. - * - * This function will wait for the processor event and may wait forever if no - * such event arrives. - * - * @see _CPU_SMP_Processor_event_broadcast(). - */ -static inline void _CPU_SMP_Processor_event_receive( void ) -{ - __asm__ volatile ( "" : : : "memory" ); -} - -/** - * @brief Gets the is executing indicator of the thread context. - * - * @param[in] context The context. - */ -static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context -) -{ - return context->is_executing; -} - -/** - * @brief Sets the is executing indicator of the thread context. - * - * @param[in] context The context. - * @param[in] is_executing The new value for the is executing indicator. - */ -static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing -) -{ - context->is_executing = is_executing; -} -#endif /* RTEMS_SMP */ - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/riscv/rtems/score/cpu_asm.h b/cpukit/score/cpu/riscv/rtems/score/cpu_asm.h deleted file mode 100644 index b5a56f3e22..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/cpu_asm.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * @file - * - * @brief riscv32 Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/riscv/rtems/score/cpuatomic.h b/cpukit/score/cpu/riscv/rtems/score/cpuatomic.h deleted file mode 100644 index 8ee9606b44..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/cpuatomic.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/riscv/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/rtems/score/cpuimpl.h deleted file mode 100644 index 3904c84bf9..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/cpuimpl.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/riscv/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv/rtems/score/riscv-utility.h deleted file mode 100644 index dc4836bee2..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/riscv-utility.h +++ /dev/null @@ -1,1526 +0,0 @@ -/* Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written - * permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, - * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST - * PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -/** - * @file - * - * @brief RISCV utility - */ -/* - * COPYRIGHT (c) 2015 Hesham Almatary - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* This file is copied from riscv-tools/encoding.h with additions/modifications to work - * with RTEMS. - */ -#ifndef _RTEMS_SCORE_RISCV_UTILITY_H -#define _RTEMS_SCORE_RISCV_UTILITY_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_HPP 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define SPTBR32_MODE 0x80000000 -#define SPTBR32_ASID 0x7FC00000 -#define SPTBR32_PPN 0x003FFFFF -#define SPTBR64_MODE 0xF000000000000000 -#define SPTBR64_ASID 0x0FFFF00000000000 -#define SPTBR64_PPN 0x00000FFFFFFFFFFF - -#define SPTBR_MODE_OFF 0 -#define SPTBR_MODE_SV32 1 -#define SPTBR_MODE_SV39 8 -#define SPTBR_MODE_SV48 9 -#define SPTBR_MODE_SV57 10 -#define SPTBR_MODE_SV64 11 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SPTBR_MODE SPTBR64_MODE -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SPTBR_MODE SPTBR32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -/** - * @brief Priv Mode registers definitions. - * - * @see RISC-V priv-spec 1.10. - */ -typedef enum { - RISCV_USER_INTERRUPT = 0, - RISCV_SUPERVISOR_SW_INTERRUPT = 1, - RISCV_MACHINE_SW_INTERRUPT = 3, - RISCV_USER_TIMER_INTERRUPT = 4, - RISCV_SUPERVISOR_TIMER_INTERRUPT = 4, - RISCV_MACHINE_TIMER_INTERRUPT = 7, - RISCV_USER_EXTERNAL_INTERRUPT = 8, - RISCV_SUPERVISOR_EXTERNAL_INTERRUPT = 9, - RISCV_MACHINE_EXTERNAL_INTERRUPT = 11 -} RISCV_Symbolic_interrupt_name; - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FMV_X_Q 0xe6000053 -#define MASK_FMV_X_Q 0xfff0707f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FMV_Q_X 0xf6000053 -#define MASK_FMV_Q_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 -#define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_MIP 0x344 -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN( or , MATCH_OR, MASK_OR) -DECLARE_INSN( and , MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) -DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) -DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -#endif diff --git a/cpukit/score/cpu/riscv/rtems/score/riscv.h b/cpukit/score/cpu/riscv/rtems/score/riscv.h deleted file mode 100644 index 6e7f1370c6..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/riscv.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * @file rtems/score/riscv.h - */ - -/* - * This file contains information pertaining to the riscv32 processor. - * - * COPYRIGHT (c) 2014 Hesham Almatary - * - * Based on code with the following copyright... - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_RISCV_H -#define _RTEMS_SCORE_RISCV_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the RISCV family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -/* -* Define the name of the CPU family and specific model. -*/ - -#define CPU_NAME "RISCV" -#define CPU_MODEL_NAME "RISCV" - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_RISCV_H */ diff --git a/cpukit/score/cpu/riscv/rtems/score/types.h b/cpukit/score/cpu/riscv/rtems/score/types.h deleted file mode 100644 index d1440fb319..0000000000 --- a/cpukit/score/cpu/riscv/rtems/score/types.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * @brief RISC-V Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * RISC-V processor family. - * - * COPYRIGHT (c) 2014 Hesham Almatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void riscv_isr; -typedef void ( *riscv_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sh/Makefile.am b/cpukit/score/cpu/sh/Makefile.am index b480b1aa26..6a19ce4cb8 100644 --- a/cpukit/score/cpu/sh/Makefile.am +++ b/cpukit/score/cpu/sh/Makefile.am @@ -1,21 +1,10 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/sh.h -include_rtems_score_HEADERS += rtems/score/sh_io.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c context.c libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += sh-exception-frame-print.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/sh/headers.am b/cpukit/score/cpu/sh/headers.am new file mode 100644 index 0000000000..40073e7186 --- /dev/null +++ b/cpukit/score/cpu/sh/headers.am @@ -0,0 +1,14 @@ +## This file was generated by "./boostrap -H". + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/sh.h +include_rtems_score_HEADERS += include/rtems/score/sh_io.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/sh/include/rtems/asm.h b/cpukit/score/cpu/sh/include/rtems/asm.h new file mode 100644 index 0000000000..ac730310cd --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/asm.h @@ -0,0 +1,137 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * @note The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif + +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define r0 REG (r0) +#define r1 REG (r1) +#define r2 REG (r2) +#define r3 REG (r3) +#define r4 REG (r4) +#define r5 REG (r5) +#define r6 REG (r6) +#define r7 REG (r7) +#define r8 REG (r8) +#define r9 REG (r9) +#define r10 REG (r10) +#define r11 REG (r11) +#define r12 REG (r12) +#define r13 REG (r13) +#define r14 REG (r14) +#define r15 REG (r15) +#define vbr REG (vbr) +#define gbr REG (gbr) +#define pr REG (pr) +#define mach REG (mach) +#define macl REG (macl) +#define sr REG (sr) +#define pc REG (pc) + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .global SYM (sym) + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h b/cpukit/score/cpu/sh/include/rtems/score/cpu.h new file mode 100644 index 0000000000..c2b7081e9e --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/cpu.h @@ -0,0 +1,738 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * SH Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * We define the interrupt stack in the linker script + */ +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * We currently support sh1 only, which has no FPU, other SHes have an FPU + * + * The macro name "SH_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if SH_HAS_FPU +#define CPU_HARDWARE_FP TRUE +#define CPU_SOFTWARE_FP FALSE +#else +#define CPU_SOFTWARE_FP FALSE +#define CPU_HARDWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + */ + +#if SH_HAS_FPU +#define CPU_ALL_TASKS_ARE_FP TRUE +#else +#define CPU_ALL_TASKS_ARE_FP FALSE +#endif + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#if SH_HAS_FPU +#define CPU_IDLE_TASK_IS_FP TRUE +#else +#define CPU_IDLE_TASK_IS_FP FALSE +#endif + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + */ + +#if SH_HAS_FPU +#define CPU_USE_DEFERRED_FP_SWITCH FALSE +#else +#define CPU_USE_DEFERRED_FP_SWITCH TRUE +#endif + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 16 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + */ + +#define CPU_MODES_INTERRUPT_MASK 0x0000000f + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +typedef struct { + uint32_t *r15; /* stack pointer */ + + uint32_t macl; + uint32_t mach; + uint32_t *pr; + + uint32_t *r14; /* frame pointer/call saved */ + + uint32_t r13; /* call saved */ + uint32_t r12; /* call saved */ + uint32_t r11; /* call saved */ + uint32_t r10; /* call saved */ + uint32_t r9; /* call saved */ + uint32_t r8; /* call saved */ + + uint32_t *r7; /* arg in */ + uint32_t *r6; /* arg in */ + +#if 0 + uint32_t *r5; /* arg in */ + uint32_t *r4; /* arg in */ +#endif + + uint32_t *r3; /* scratch */ + uint32_t *r2; /* scratch */ + uint32_t *r1; /* scratch */ + + uint32_t *r0; /* arg return */ + + uint32_t gbr; + uint32_t sr; + +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r15 + +typedef struct { +#if SH_HAS_FPU +#ifdef SH4_USE_X_REGISTERS + union { + float f[16]; + double d[8]; + } x; +#endif + union { + float f[16]; + double d[8]; + } r; + float fpul; /* fp communication register */ + uint32_t fpscr; /* fp control register */ +#endif /* SH_HAS_FPU */ +} Context_Control_fp; + +typedef struct { +} CPU_Interrupt_frame; + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +#if SH_HAS_FPU +extern Context_Control_fp _CPU_Null_fp_context; +#endif + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +/* XXX: if needed, put more variables here */ +void CPU_delay( uint32_t microseconds ); + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + */ + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * We have been able to run the sptests with this value, but have not + * been able to run the tmtest suite. + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +#define CPU_SIZEOF_POINTER 4 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ +#if defined(__SH4__) +/* FIXME: sh3 and SH3E? */ +#define CPU_ALIGNMENT 8 +#else +#define CPU_ALIGNMENT 4 +#endif + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * SH Specific Information: NONE + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + */ + +#define _CPU_ISR_Disable( _level) \ + sh_disable_interrupts( _level ) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _level) \ + sh_enable_interrupts( _level) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _level) \ + sh_flash_interrupts( _level) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + sh_get_interrupt_level( level ); + return level == 0; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + */ + +#define _CPU_ISR_Set_level( _newlevel) \ + sh_set_interrupt_level(_newlevel) + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + */ + +/* + * FIXME: defined as a function for debugging - should be a macro + */ +void _CPU_Context_Initialize( + Context_Control *_the_context, + void *_stack_base, + uint32_t _size, + uint32_t _isr, + void (*_entry_point)(void), + int _is_fp, + void *_tls_area ); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. + */ + +#if SH_HAS_FPU +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *(*(_destination)) = _CPU_Null_fp_context;\ + } while(0) +#else +#define _CPU_Context_Initialize_fp( _destination ) \ + { } +#endif + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * FIXME: Trap32 ??? + * + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * invokes a Trap32 Instruction which returns to the breakpoint + * routine of cmon. + */ + +#ifdef BSP_FATAL_HALT + /* we manage the fatal error in the board support package */ + void bsp_fatal_halt( uint32_t _error); +#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) +#else +#define _CPU_Fatal_halt( _source, _error)\ +{ \ + __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ + __asm__ volatile("mov #1, r4"); \ + __asm__ volatile("trapa #34"); \ +} +#endif + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/* + * @brief CPU Initialize + * + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * @brief This routine saves the floating point context passed to it. + * + * _CPU_Context_save_fp + * + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * @brief This routine restores the floating point context passed to it. + * + * _CPU_Context_restore_fp + * + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sh/include/rtems/score/sh.h b/cpukit/score/cpu/sh/include/rtems/score/sh.h new file mode 100644 index 0000000000..4e26478b8b --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/sh.h @@ -0,0 +1,277 @@ +/** + * @file + * + * @brief Hitachi SH CPU Department Source + * + * This include file contains information pertaining to the Hitachi SH + * processor. + */ + +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SH_H +#define _RTEMS_SCORE_SH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "SH" family. + * + * It does this by setting variables to indicate which implementation + * dependent features are present in a particular member of the family. + */ + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#if defined(__SH2E__) || defined(__SH3E__) + +/* FIXME: SH-DSP context not currently supported */ +#define SH_HAS_FPU 0 + +#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) + +/* + * Define this if you want to use XD-registers. + * Then this registers will be saved/restored on context switch. + * ! They will not be saved/restored on interrupts! + */ +#define SH4_USE_X_REGISTERS 0 + +#if defined(__LITTLE_ENDIAN__) +#define SH_HAS_FPU 1 +#else +/* FIXME: Context_Control_fp does not support big endian */ +#warning FPU not supported +#define SH_HAS_FPU 0 +#endif + +#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) +#define SH_HAS_FPU 0 +#else +#warning Cannot detect FPU support, assuming no FPU +#define SH_HAS_FPU 0 +#endif + +/* this should not be here */ +#ifndef CPU_MODEL_NAME +#define CPU_MODEL_NAME "SH-Multilib" +#endif + +/* + * If the following macro is set to 0 there will be no software irq stack + */ + +#ifndef SH_HAS_SEPARATE_STACKS +#define SH_HAS_SEPARATE_STACKS 1 +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "Hitachi SH" + +#ifndef ASM + +#if defined(__sh1__) || defined(__sh2__) + +/* + * Mask for disabling interrupts + */ +#define SH_IRQDIS_VALUE 0xf0 + +#define sh_disable_interrupts( _level ) \ + __asm__ volatile ( \ + "stc sr,%0\n\t" \ + "ldc %1,sr\n\t"\ + : "=&r" (_level ) \ + : "r" (SH_IRQDIS_VALUE) ); + +#define sh_enable_interrupts( _level ) \ + __asm__ volatile( "ldc %0,sr\n\t" \ + "nop\n\t" \ + :: "r" (_level) ); + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define sh_flash_interrupts( _level ) \ + __asm__ volatile( \ + "ldc %1,sr\n\t" \ + "nop\n\t" \ + "ldc %0,sr\n\t" \ + "nop\n\t" \ + : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); + +#else + +#define SH_IRQDIS_MASK 0xf0 + +#define sh_disable_interrupts( _level ) \ + __asm__ volatile ( \ + "stc sr,%0\n\t" \ + "mov %0,r5\n\t" \ + "or %1,r5\n\t" \ + "ldc r5,sr\n\t"\ + : "=&r" (_level ) \ + : "r" (SH_IRQDIS_MASK) \ + : "r5" ); + +#define sh_enable_interrupts( _level ) \ + __asm__ volatile( "ldc %0,sr\n\t" \ + "nop\n\t" \ + :: "r" (_level) ); + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define sh_flash_interrupts( _level ) \ + __asm__ volatile( \ + "stc sr,r5\n\t" \ + "ldc %1,sr\n\t" \ + "nop\n\t" \ + "or %0,r5\n\t" \ + "ldc r5,sr\n\t" \ + "nop\n\t" \ + : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5"); + +#endif + +#define sh_get_interrupt_level( _level ) \ +{ \ + register uint32_t _tmpsr ; \ + \ + __asm__ volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ + _level = (_tmpsr & 0xf0) >> 4 ; \ +} + +#define sh_set_interrupt_level( _newlevel ) \ +{ \ + register uint32_t _tmpsr; \ + \ + __asm__ volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ + _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ + __asm__ volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ +} + +/* + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + */ + +static inline uint32_t sh_swap_u32( + uint32_t value +) +{ + register uint32_t swapped; + + __asm__ volatile ( + "swap.b %1,%0; " + "swap.w %0,%0; " + "swap.b %0,%0" + : "=r" (swapped) + : "r" (value) ); + + return( swapped ); +} + +static inline uint16_t sh_swap_u16( + uint16_t value +) +{ + register uint16_t swapped ; + + __asm__ volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) ); + + return( swapped ); +} + +#define CPU_swap_u32( value ) sh_swap_u32( value ) +#define CPU_swap_u16( value ) sh_swap_u16( value ) + +extern unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ); + +#endif /* !ASM */ + +/* + * Bits on SH-4 registers. + * See SH-4 Programming manual for more details. + * + * Added by Alexandra Kossovsky + */ + +#if defined(__SH4__) +#define SH4_SR_MD 0x40000000 /* Priveleged mode */ +#define SH4_SR_RB 0x20000000 /* General register bank specifier */ +#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ +#define SH4_SR_FD 0x00008000 /* FPU disable bit */ +#define SH4_SR_M 0x00000200 /* For signed division: + divisor (module) is negative */ +#define SH4_SR_Q 0x00000100 /* For signed division: + dividend (and quotient) is negative */ +#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ +#define SH4_SR_IMASK_S 4 +#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: + if set, data in MACH/L register + is restricted to 48/32 bits + for MAC.W/L instructions */ +#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ +#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ + +/* FPSCR -- FPU Status/Control Register */ +#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ +#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ +#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point + operations flag */ + /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ +#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ +#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ +#define SH4_FPSCR_CAUSE_S 12 +#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ +#define SH4_FPSCR_ENABLE_s 7 +#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ +#define SH4_FPSCR_FLAG_S 2 +#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: + 1/0 -- round to zero/nearest */ +#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/sh_io.h b/cpukit/score/cpu/sh/include/rtems/score/sh_io.h new file mode 100644 index 0000000000..8d81965f78 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/sh_io.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture + * + * These are some macros to access memory mapped devices + * on the SH7000-architecture. + */ + +/* + * Inspired from the linux kernel's include/asm/io.h + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1996-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SH_IO_H +#define _RTEMS_SCORE_SH_IO_H + +#define readb(addr) (*(volatile unsigned char *) (addr)) +#define readw(addr) (*(volatile unsigned short *) (addr)) +#define readl(addr) (*(volatile unsigned int *) (addr)) +#define read8(addr) (*(volatile uint8_t *) (addr)) +#define read16(addr) (*(volatile uint16_t *) (addr)) +#define read32(addr) (*(volatile uint32_t *) (addr)) + +#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) +#define write8(b,addr) ((*(volatile uint8_t *) (addr)) = (b)) +#define write16(b,addr) ((*(volatile uint16_t *) (addr)) = (b)) +#define write32(b,addr) ((*(volatile uint32_t *) (addr)) = (b)) + +#define inb(addr) readb(addr) +#define outb(b,addr) writeb(b,addr) + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/types.h b/cpukit/score/cpu/sh/include/rtems/score/types.h new file mode 100644 index 0000000000..a449a6d6e3 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/types.h @@ -0,0 +1,56 @@ +/** + * @file + * + * @brief Hitachi SH CPU Type Definitions + * + * This include file contains information pertaining to the Hitachi SH + * processor. + */ + +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void sh_isr; +typedef void ( *sh_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/sh/preinstall.am b/cpukit/score/cpu/sh/preinstall.am deleted file mode 100644 index 08d2352709..0000000000 --- a/cpukit/score/cpu/sh/preinstall.am +++ /dev/null @@ -1,53 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/sh.h: rtems/score/sh.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sh.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/sh.h - -$(PROJECT_INCLUDE)/rtems/score/sh_io.h: rtems/score/sh_io.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sh_io.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/sh_io.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/sh/rtems/asm.h b/cpukit/score/cpu/sh/rtems/asm.h deleted file mode 100644 index ac730310cd..0000000000 --- a/cpukit/score/cpu/sh/rtems/asm.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG (r0) -#define r1 REG (r1) -#define r2 REG (r2) -#define r3 REG (r3) -#define r4 REG (r4) -#define r5 REG (r5) -#define r6 REG (r6) -#define r7 REG (r7) -#define r8 REG (r8) -#define r9 REG (r9) -#define r10 REG (r10) -#define r11 REG (r11) -#define r12 REG (r12) -#define r13 REG (r13) -#define r14 REG (r14) -#define r15 REG (r15) -#define vbr REG (vbr) -#define gbr REG (gbr) -#define pr REG (pr) -#define mach REG (mach) -#define macl REG (macl) -#define sr REG (sr) -#define pc REG (pc) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h deleted file mode 100644 index c2b7081e9e..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/cpu.h +++ /dev/null @@ -1,738 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SH Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * We define the interrupt stack in the linker script - */ -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * We currently support sh1 only, which has no FPU, other SHes have an FPU - * - * The macro name "SH_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if SH_HAS_FPU -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_SOFTWARE_FP FALSE -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#if SH_HAS_FPU -#define CPU_ALL_TASKS_ARE_FP TRUE -#else -#define CPU_ALL_TASKS_ARE_FP FALSE -#endif - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#if SH_HAS_FPU -#define CPU_IDLE_TASK_IS_FP TRUE -#else -#define CPU_IDLE_TASK_IS_FP FALSE -#endif - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#if SH_HAS_FPU -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else -#define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 16 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000f - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - uint32_t *r15; /* stack pointer */ - - uint32_t macl; - uint32_t mach; - uint32_t *pr; - - uint32_t *r14; /* frame pointer/call saved */ - - uint32_t r13; /* call saved */ - uint32_t r12; /* call saved */ - uint32_t r11; /* call saved */ - uint32_t r10; /* call saved */ - uint32_t r9; /* call saved */ - uint32_t r8; /* call saved */ - - uint32_t *r7; /* arg in */ - uint32_t *r6; /* arg in */ - -#if 0 - uint32_t *r5; /* arg in */ - uint32_t *r4; /* arg in */ -#endif - - uint32_t *r3; /* scratch */ - uint32_t *r2; /* scratch */ - uint32_t *r1; /* scratch */ - - uint32_t *r0; /* arg return */ - - uint32_t gbr; - uint32_t sr; - -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r15 - -typedef struct { -#if SH_HAS_FPU -#ifdef SH4_USE_X_REGISTERS - union { - float f[16]; - double d[8]; - } x; -#endif - union { - float f[16]; - double d[8]; - } r; - float fpul; /* fp communication register */ - uint32_t fpscr; /* fp control register */ -#endif /* SH_HAS_FPU */ -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -#if SH_HAS_FPU -extern Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ -void CPU_delay( uint32_t microseconds ); - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * We have been able to run the sptests with this value, but have not - * been able to run the tmtest suite. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ -#if defined(__SH4__) -/* FIXME: sh3 and SH3E? */ -#define CPU_ALIGNMENT 8 -#else -#define CPU_ALIGNMENT 4 -#endif - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * SH Specific Information: NONE - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level) \ - sh_disable_interrupts( _level ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level) \ - sh_enable_interrupts( _level) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level) \ - sh_flash_interrupts( _level) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - sh_get_interrupt_level( level ); - return level == 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( _newlevel) \ - sh_set_interrupt_level(_newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -/* - * FIXME: defined as a function for debugging - should be a macro - */ -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp, - void *_tls_area ); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. - */ - -#if SH_HAS_FPU -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context;\ - } while(0) -#else -#define _CPU_Context_Initialize_fp( _destination ) \ - { } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * FIXME: Trap32 ??? - * - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * invokes a Trap32 Instruction which returns to the breakpoint - * routine of cmon. - */ - -#ifdef BSP_FATAL_HALT - /* we manage the fatal error in the board support package */ - void bsp_fatal_halt( uint32_t _error); -#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) -#else -#define _CPU_Fatal_halt( _source, _error)\ -{ \ - __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ - __asm__ volatile("mov #1, r4"); \ - __asm__ volatile("trapa #34"); \ -} -#endif - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/* - * @brief CPU Initialize - * - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * @brief This routine saves the floating point context passed to it. - * - * _CPU_Context_save_fp - * - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * @brief This routine restores the floating point context passed to it. - * - * _CPU_Context_restore_fp - * - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/cpuatomic.h b/cpukit/score/cpu/sh/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sh/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sh/rtems/score/sh.h b/cpukit/score/cpu/sh/rtems/score/sh.h deleted file mode 100644 index 4e26478b8b..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/sh.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - * @file - * - * @brief Hitachi SH CPU Department Source - * - * This include file contains information pertaining to the Hitachi SH - * processor. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SH_H -#define _RTEMS_SCORE_SH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "SH" family. - * - * It does this by setting variables to indicate which implementation - * dependent features are present in a particular member of the family. - */ - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#if defined(__SH2E__) || defined(__SH3E__) - -/* FIXME: SH-DSP context not currently supported */ -#define SH_HAS_FPU 0 - -#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) - -/* - * Define this if you want to use XD-registers. - * Then this registers will be saved/restored on context switch. - * ! They will not be saved/restored on interrupts! - */ -#define SH4_USE_X_REGISTERS 0 - -#if defined(__LITTLE_ENDIAN__) -#define SH_HAS_FPU 1 -#else -/* FIXME: Context_Control_fp does not support big endian */ -#warning FPU not supported -#define SH_HAS_FPU 0 -#endif - -#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) -#define SH_HAS_FPU 0 -#else -#warning Cannot detect FPU support, assuming no FPU -#define SH_HAS_FPU 0 -#endif - -/* this should not be here */ -#ifndef CPU_MODEL_NAME -#define CPU_MODEL_NAME "SH-Multilib" -#endif - -/* - * If the following macro is set to 0 there will be no software irq stack - */ - -#ifndef SH_HAS_SEPARATE_STACKS -#define SH_HAS_SEPARATE_STACKS 1 -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Hitachi SH" - -#ifndef ASM - -#if defined(__sh1__) || defined(__sh2__) - -/* - * Mask for disabling interrupts - */ -#define SH_IRQDIS_VALUE 0xf0 - -#define sh_disable_interrupts( _level ) \ - __asm__ volatile ( \ - "stc sr,%0\n\t" \ - "ldc %1,sr\n\t"\ - : "=&r" (_level ) \ - : "r" (SH_IRQDIS_VALUE) ); - -#define sh_enable_interrupts( _level ) \ - __asm__ volatile( "ldc %0,sr\n\t" \ - "nop\n\t" \ - :: "r" (_level) ); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define sh_flash_interrupts( _level ) \ - __asm__ volatile( \ - "ldc %1,sr\n\t" \ - "nop\n\t" \ - "ldc %0,sr\n\t" \ - "nop\n\t" \ - : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); - -#else - -#define SH_IRQDIS_MASK 0xf0 - -#define sh_disable_interrupts( _level ) \ - __asm__ volatile ( \ - "stc sr,%0\n\t" \ - "mov %0,r5\n\t" \ - "or %1,r5\n\t" \ - "ldc r5,sr\n\t"\ - : "=&r" (_level ) \ - : "r" (SH_IRQDIS_MASK) \ - : "r5" ); - -#define sh_enable_interrupts( _level ) \ - __asm__ volatile( "ldc %0,sr\n\t" \ - "nop\n\t" \ - :: "r" (_level) ); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define sh_flash_interrupts( _level ) \ - __asm__ volatile( \ - "stc sr,r5\n\t" \ - "ldc %1,sr\n\t" \ - "nop\n\t" \ - "or %0,r5\n\t" \ - "ldc r5,sr\n\t" \ - "nop\n\t" \ - : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5"); - -#endif - -#define sh_get_interrupt_level( _level ) \ -{ \ - register uint32_t _tmpsr ; \ - \ - __asm__ volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ - _level = (_tmpsr & 0xf0) >> 4 ; \ -} - -#define sh_set_interrupt_level( _newlevel ) \ -{ \ - register uint32_t _tmpsr; \ - \ - __asm__ volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ - _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ - __asm__ volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ -} - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - */ - -static inline uint32_t sh_swap_u32( - uint32_t value -) -{ - register uint32_t swapped; - - __asm__ volatile ( - "swap.b %1,%0; " - "swap.w %0,%0; " - "swap.b %0,%0" - : "=r" (swapped) - : "r" (value) ); - - return( swapped ); -} - -static inline uint16_t sh_swap_u16( - uint16_t value -) -{ - register uint16_t swapped ; - - __asm__ volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) ); - - return( swapped ); -} - -#define CPU_swap_u32( value ) sh_swap_u32( value ) -#define CPU_swap_u16( value ) sh_swap_u16( value ) - -extern unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ); - -#endif /* !ASM */ - -/* - * Bits on SH-4 registers. - * See SH-4 Programming manual for more details. - * - * Added by Alexandra Kossovsky - */ - -#if defined(__SH4__) -#define SH4_SR_MD 0x40000000 /* Priveleged mode */ -#define SH4_SR_RB 0x20000000 /* General register bank specifier */ -#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ -#define SH4_SR_FD 0x00008000 /* FPU disable bit */ -#define SH4_SR_M 0x00000200 /* For signed division: - divisor (module) is negative */ -#define SH4_SR_Q 0x00000100 /* For signed division: - dividend (and quotient) is negative */ -#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ -#define SH4_SR_IMASK_S 4 -#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: - if set, data in MACH/L register - is restricted to 48/32 bits - for MAC.W/L instructions */ -#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ -#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ - -/* FPSCR -- FPU Status/Control Register */ -#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ -#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ -#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point - operations flag */ - /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ -#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ -#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ -#define SH4_FPSCR_CAUSE_S 12 -#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ -#define SH4_FPSCR_ENABLE_s 7 -#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ -#define SH4_FPSCR_FLAG_S 2 -#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: - 1/0 -- round to zero/nearest */ -#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/sh_io.h b/cpukit/score/cpu/sh/rtems/score/sh_io.h deleted file mode 100644 index 8d81965f78..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/sh_io.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file - * - * @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture - * - * These are some macros to access memory mapped devices - * on the SH7000-architecture. - */ - -/* - * Inspired from the linux kernel's include/asm/io.h - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1996-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SH_IO_H -#define _RTEMS_SCORE_SH_IO_H - -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) -#define read8(addr) (*(volatile uint8_t *) (addr)) -#define read16(addr) (*(volatile uint16_t *) (addr)) -#define read32(addr) (*(volatile uint32_t *) (addr)) - -#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) -#define write8(b,addr) ((*(volatile uint8_t *) (addr)) = (b)) -#define write16(b,addr) ((*(volatile uint16_t *) (addr)) = (b)) -#define write32(b,addr) ((*(volatile uint32_t *) (addr)) = (b)) - -#define inb(addr) readb(addr) -#define outb(b,addr) writeb(b,addr) - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/types.h b/cpukit/score/cpu/sh/rtems/score/types.h deleted file mode 100644 index a449a6d6e3..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file - * - * @brief Hitachi SH CPU Type Definitions - * - * This include file contains information pertaining to the Hitachi SH - * processor. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void sh_isr; -typedef void ( *sh_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sparc/Makefile.am b/cpukit/score/cpu/sparc/Makefile.am index e03aabc0ff..1a76a2f009 100644 --- a/cpukit/score/cpu/sparc/Makefile.am +++ b/cpukit/score/cpu/sparc/Makefile.am @@ -1,19 +1,5 @@ include $(top_srcdir)/automake/compile.am -include_libcpudir = $(includedir)/libcpu -include_libcpu_HEADERS = include/libcpu/byteorder.h - -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/sparc.h -include_rtems_score_HEADERS += rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/sparcimpl.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c libscorecpu_a_SOURCES += sparc-context-volatile-clobber.S @@ -22,5 +8,5 @@ libscorecpu_a_SOURCES += sparc-counter.c libscorecpu_a_SOURCES += sparc-counter-asm.S libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/sparc/headers.am b/cpukit/score/cpu/sparc/headers.am new file mode 100644 index 0000000000..89f4f63cf2 --- /dev/null +++ b/cpukit/score/cpu/sparc/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += include/libcpu/byteorder.h + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/sparc.h +include_rtems_score_HEADERS += include/rtems/score/sparcimpl.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/sparc/include/machine/elf_machdep.h b/cpukit/score/cpu/sparc/include/machine/elf_machdep.h new file mode 100644 index 0000000000..e8f2b630c2 --- /dev/null +++ b/cpukit/score/cpu/sparc/include/machine/elf_machdep.h @@ -0,0 +1,92 @@ +/* $NetBSD: elf_machdep.h,v 1.7 2009/05/30 05:56:53 skrll Exp $ */ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF32_MACHDEP_ID_CASES \ + case EM_SPARC: \ + case EM_SPARC32PLUS: \ + break; + +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF64_MACHDEP_ID_CASES \ + case EM_SPARC32PLUS: \ + case EM_SPARCV9: \ + /* no 64-bit ELF machine types supported */ + +#define ELF32_MACHDEP_ID EM_SPARC /* XXX right? */ + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +#define R_SPARC_NONE 0 +#define R_SPARC_8 1 +#define R_SPARC_16 2 +#define R_SPARC_32 3 +#define R_SPARC_DISP8 4 +#define R_SPARC_DISP16 5 +#define R_SPARC_DISP32 6 +#define R_SPARC_WDISP30 7 +#define R_SPARC_WDISP22 8 +#define R_SPARC_HI22 9 +#define R_SPARC_22 10 +#define R_SPARC_13 11 +#define R_SPARC_LO10 12 +#define R_SPARC_GOT10 13 +#define R_SPARC_GOT13 14 +#define R_SPARC_GOT22 15 +#define R_SPARC_PC10 16 +#define R_SPARC_PC22 17 +#define R_SPARC_WPLT30 18 +#define R_SPARC_COPY 19 +#define R_SPARC_GLOB_DAT 20 +#define R_SPARC_JMP_SLOT 21 +#define R_SPARC_RELATIVE 22 +#define R_SPARC_UA32 23 +#define R_SPARC_PLT32 24 +#define R_SPARC_HIPLT22 25 +#define R_SPARC_LOPLT10 26 +#define R_SPARC_PCPLT32 27 +#define R_SPARC_PCPLT22 28 +#define R_SPARC_PCPLT10 29 +#define R_SPARC_10 30 +#define R_SPARC_11 31 +#define R_SPARC_64 32 +#define R_SPARC_OLO10 33 +#define R_SPARC_HH22 34 +#define R_SPARC_HM10 35 +#define R_SPARC_LM22 36 +#define R_SPARC_PC_HH22 37 +#define R_SPARC_PC_HM10 38 +#define R_SPARC_PC_LM22 39 +#define R_SPARC_WDISP16 40 +#define R_SPARC_WDISP19 41 +#define R_SPARC_GLOB_JMP 42 +#define R_SPARC_7 43 +#define R_SPARC_5 44 +#define R_SPARC_6 45 + +/* TLS relocations */ +#define R_SPARC_TLS_GD_HI22 56 +#define R_SPARC_TLS_GD_LO10 57 +#define R_SPARC_TLS_GD_ADD 58 +#define R_SPARC_TLS_GD_CALL 59 +#define R_SPARC_TLS_LDM_HI22 60 +#define R_SPARC_TLS_LDM_LO10 61 +#define R_SPARC_TLS_LDM_ADD 62 +#define R_SPARC_TLS_LDM_CALL 63 +#define R_SPARC_TLS_LDO_HIX22 64 +#define R_SPARC_TLS_LDO_LOX10 65 +#define R_SPARC_TLS_LDO_ADD 66 +#define R_SPARC_TLS_IE_HI22 67 +#define R_SPARC_TLS_IE_LO10 68 +#define R_SPARC_TLS_IE_LD 69 +#define R_SPARC_TLS_IE_LDX 70 +#define R_SPARC_TLS_IE_ADD 71 +#define R_SPARC_TLS_LE_HIX22 72 +#define R_SPARC_TLS_LE_LOX10 73 +#define R_SPARC_TLS_DTPMOD32 74 +#define R_SPARC_TLS_DTPMOD64 75 +#define R_SPARC_TLS_DTPOFF32 76 +#define R_SPARC_TLS_DTPOFF64 77 +#define R_SPARC_TLS_TPOFF32 78 +#define R_SPARC_TLS_TPOFF64 79 + +#define R_TYPE(name) __CONCAT(R_SPARC_,name) diff --git a/cpukit/score/cpu/sparc/include/rtems/asm.h b/cpukit/score/cpu/sparc/include/rtems/asm.h new file mode 100644 index 0000000000..a2b11f63fc --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/asm.h @@ -0,0 +1,120 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif + +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ +/* XXX The following ifdef magic fixes the problem but results in a warning */ +/* XXX when compiling assembly code. */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +/* + * Entry for traps which jump to a programmer-specified trap handler. + */ + +#define TRAP(_vector, _handler) \ + mov %psr, %l0 ; \ + sethi %hi(_handler), %l4 ; \ + jmp %l4+%lo(_handler); \ + mov _vector, %l3 + +/* + * Used for the reset trap to avoid a supervisor instruction + */ + +#define RTRAP(_vector, _handler) \ + mov %g0, %l0 ; \ + sethi %hi(_handler), %l4 ; \ + jmp %l4+%lo(_handler); \ + mov _vector, %l3 + +#endif diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h new file mode 100644 index 0000000000..2b50592e08 --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h @@ -0,0 +1,1202 @@ +/** + * @file + * + * @brief SPARC CPU Department Source + * + * This include file contains information pertaining to the port of + * the executive to the SPARC processor. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/* + * The SPARC ABI is a bit special with respect to the floating point context. + * The complete floating point context is volatile. Thus, from an ABI point + * of view nothing needs to be saved and restored during a context switch. + * Instead the floating point context must be saved and restored during + * interrupt processing. Historically, the deferred floating point switch was + * used for SPARC and the complete floating point context is saved and + * restored during a context switch to the new floating point unit owner. + * This is a bit dangerous since post-switch actions (e.g. signal handlers) + * and context switch extensions may silently corrupt the floating point + * context. + * + * The floating point unit is disabled for interrupt handlers. Thus, in case + * an interrupt handler uses the floating point unit then this will result in a + * trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). + * + * In uniprocessor configurations, a lazy floating point context switch is + * used. In case an active floating point thread is interrupted (PSR[EF] == 1) + * and a thread dispatch is carried out, then this thread is registered as the + * floating point owner. When a floating point owner is present during a + * context switch, the floating point unit is disabled for the heir thread + * (PSR[EF] == 0). The floating point disabled trap checks that the use of the + * floating point unit is allowed and saves/restores the floating point context + * on demand. + * + * In SMP configurations, the deferred floating point switch is not supported + * in principle. So, use here a synchronous floating point switching. + * Synchronous means that the volatile floating point context is saved and + * restored around a thread dispatch issued during interrupt processing. Thus + * post-switch actions and context switch extensions may safely use the + * floating point unit. + */ +#if SPARC_HAS_FPU == 1 + #if defined(RTEMS_SMP) + #define SPARC_USE_SYNCHRONOUS_FP_SWITCH + #else + #define SPARC_USE_LAZY_FP_SWITCH + #endif +#endif + +/** + * Does the executive manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * The SPARC does not have a dedicated HW interrupt stack and one has + * been implemented in SW. + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/** + * Does the CPU follow the simple vectored interrupt model? + * + * - If TRUE, then RTEMS allocates the vector table it internally manages. + * - If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * THe SPARC is a simple vectored architecture. Usually there is no + * PIC and the CPU directly vectors the interrupts. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * - If TRUE, then it must be installed during initialization. + * - If FALSE, then no installation is performed. + * + * The SPARC does not have a dedicated HW interrupt stack. + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/** + * Do we allocate a dedicated interrupt stack in the Interrupt Manager? + * + * - If TRUE, then the memory is allocated during initialization. + * - If FALSE, then the memory is allocated during initialization. + * + * The SPARC does not have hardware support for switching to a + * dedicated interrupt stack. The port includes support for doing this + * in software. + * + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * The SPARC port does not pass an Interrupt Stack Frame pointer to + * interrupt handlers. + */ +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/** + * Does the CPU have hardware floating point? + * + * - If TRUE, then the FLOATING_POINT task attribute is supported. + * - If FALSE, then the FLOATING_POINT task attribute is ignored. + * + * This is set based upon the multilib settings. + */ +#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH) + #define CPU_HARDWARE_FP TRUE +#else + #define CPU_HARDWARE_FP FALSE +#endif + +/** + * The SPARC GCC port does not have a software floating point library + * that requires RTEMS assistance. + */ +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks FLOATING_POINT tasks implicitly? + * + * - If TRUE, then the FLOATING_POINT task attribute is assumed. + * - If FALSE, then the FLOATING_POINT task attribute is followed. + * + * The SPARC GCC port does not implicitly use floating point registers. + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/** + * Should the IDLE task have a floating point context? + * + * - If TRUE, then the IDLE task is created as a FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * - If FALSE, then the IDLE task does not have a floating point context. + * + * The IDLE task does not have to be floating point on the SPARC. + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * - If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * - If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * The SPARC architecture does not have a low power or halt instruction. + * It is left to the BSP and/or CPU specific code to provide an IDLE + * thread body which is aware of low power modes. + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * - If TRUE, then the grows upward. + * - If FALSE, then the grows toward smaller addresses. + * + * The stack grows to lower addresses on the SPARC. + */ +#define CPU_STACK_GROWS_UP FALSE + +/* LEON3 systems may use a cache line size of 64 */ +#define CPU_CACHE_LINE_BYTES 64 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/** + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + * The SPARC has 16 interrupt levels in the PIL field of the PSR. + */ +#define CPU_MODES_INTERRUPT_MASK 0x0000000F + +#ifndef ASM +/** + * This structure represents the organization of the minimum stack frame + * for the SPARC. More framing information is required in certain situaions + * such as when there are a large number of out parameters or when the callee + * must save floating point registers. + */ +typedef struct { + /** This is the offset of the l0 register. */ + uint32_t l0; + /** This is the offset of the l1 register. */ + uint32_t l1; + /** This is the offset of the l2 register. */ + uint32_t l2; + /** This is the offset of the l3 register. */ + uint32_t l3; + /** This is the offset of the l4 register. */ + uint32_t l4; + /** This is the offset of the l5 register. */ + uint32_t l5; + /** This is the offset of the l6 register. */ + uint32_t l6; + /** This is the offset of the l7 register. */ + uint32_t l7; + /** This is the offset of the l0 register. */ + uint32_t i0; + /** This is the offset of the i1 register. */ + uint32_t i1; + /** This is the offset of the i2 register. */ + uint32_t i2; + /** This is the offset of the i3 register. */ + uint32_t i3; + /** This is the offset of the i4 register. */ + uint32_t i4; + /** This is the offset of the i5 register. */ + uint32_t i5; + /** This is the offset of the i6 register. */ + uint32_t i6_fp; + /** This is the offset of the i7 register. */ + uint32_t i7; + /** This is the offset of the register used to return structures. */ + void *structure_return_address; + + /* + * The following are for the callee to save the register arguments in + * should this be necessary. + */ + /** This is the offset of the register for saved argument 0. */ + uint32_t saved_arg0; + /** This is the offset of the register for saved argument 1. */ + uint32_t saved_arg1; + /** This is the offset of the register for saved argument 2. */ + uint32_t saved_arg2; + /** This is the offset of the register for saved argument 3. */ + uint32_t saved_arg3; + /** This is the offset of the register for saved argument 4. */ + uint32_t saved_arg4; + /** This is the offset of the register for saved argument 5. */ + uint32_t saved_arg5; + /** This field pads the structure so ldd and std instructions can be used. */ + uint32_t pad0; +} SPARC_Minimum_stack_frame; + +#endif /* ASM */ + +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L0_OFFSET 0x00 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L1_OFFSET 0x04 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L2_OFFSET 0x08 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L3_OFFSET 0x0c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L4_OFFSET 0x10 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L5_OFFSET 0x14 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L6_OFFSET 0x18 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_L7_OFFSET 0x1c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I0_OFFSET 0x20 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I1_OFFSET 0x24 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I2_OFFSET 0x28 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I3_OFFSET 0x2c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I4_OFFSET 0x30 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I5_OFFSET 0x34 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_I7_OFFSET 0x3c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 +/** This macro defines an offset into the stack frame for use in assembly. */ +#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c + +#define CPU_MAXIMUM_PROCESSORS 32 + +/** + * @defgroup Contexts SPARC Context Structures + * + * @ingroup Score + * + * Generally there are 2 types of context to save. + * + Interrupt registers to save + * + Task level registers to save + * + * This means we have the following 3 context items: + * + task level context stuff:: Context_Control + * + floating point task stuff:: Context_Control_fp + * + special interrupt level context :: Context_Control_interrupt + * + * On the SPARC, we are relatively conservative in that we save most + * of the CPU state in the context area. The ET (enable trap) bit and + * the CWP (current window pointer) fields of the PSR are considered + * system wide resources and are not maintained on a per-thread basis. + */ +/**@{**/ + +#ifndef ASM +typedef struct Context_Control_fp Context_Control_fp; + +/** + * @brief SPARC basic context. + * + * This structure defines the non-volatile integer and processor state context + * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY + * INTERFACE - SPARC Processor Supplement", Third Edition. + * + * The registers g2 through g4 are reserved for applications. GCC uses them as + * volatile registers by default. So they are treated like volatile registers + * in RTEMS as well. + * + * The register g6 contains the per-CPU control of the current processor. It + * is an invariant of the processor context. This register must not be saved + * and restored during context switches or interrupt services. + */ +typedef struct { + /** This will contain the contents of the g5 register. */ + uint32_t g5; + /** This will contain the contents of the g7 register. */ + uint32_t g7; + + /** + * This will contain the contents of the l0 and l1 registers. + * + * Using a double l0_and_l1 will put everything in this structure on a double + * word boundary which allows us to use double word loads and stores safely + * in the context switch. + */ + double l0_and_l1; + /** This will contain the contents of the l2 register. */ + uint32_t l2; + /** This will contain the contents of the l3 register. */ + uint32_t l3; + /** This will contain the contents of the l4 register. */ + uint32_t l4; + /** This will contain the contents of the l5 registeer.*/ + uint32_t l5; + /** This will contain the contents of the l6 register. */ + uint32_t l6; + /** This will contain the contents of the l7 register. */ + uint32_t l7; + + /** This will contain the contents of the i0 register. */ + uint32_t i0; + /** This will contain the contents of the i1 register. */ + uint32_t i1; + /** This will contain the contents of the i2 register. */ + uint32_t i2; + /** This will contain the contents of the i3 register. */ + uint32_t i3; + /** This will contain the contents of the i4 register. */ + uint32_t i4; + /** This will contain the contents of the i5 register. */ + uint32_t i5; + /** This will contain the contents of the i6 (e.g. frame pointer) register. */ + uint32_t i6_fp; + /** This will contain the contents of the i7 register. */ + uint32_t i7; + + /** This will contain the contents of the o6 (e.g. frame pointer) register. */ + uint32_t o6_sp; + /** + * This will contain the contents of the o7 (e.g. address of CALL + * instruction) register. + */ + uint32_t o7; + + /** This will contain the contents of the processor status register. */ + uint32_t psr; + /** + * This field is used to prevent heavy nesting of calls to _Thread_Dispatch + * on an interrupted task's stack. This is problematic on the slower + * SPARC CPU models at high interrupt rates. + */ + uint32_t isr_dispatch_disable; + +#if defined(SPARC_USE_LAZY_FP_SWITCH) + Context_Control_fp *fp_context; +#endif + +#if defined(RTEMS_SMP) + volatile uint32_t is_executing; +#endif +} Context_Control; + +/** + * This macro provides a CPU independent way for RTEMS to access the + * stack pointer in a context structure. The actual name and offset is + * CPU architecture dependent. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->o6_sp + +#ifdef RTEMS_SMP + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + { + return context->is_executing; + } + + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + context->is_executing = is_executing; + } +#endif + +#endif /* ASM */ + +/* + * Offsets of fields with Context_Control for assembly routines. + */ + +/** This macro defines an offset into the context for use in assembly. */ +#define G5_OFFSET 0x00 +/** This macro defines an offset into the context for use in assembly. */ +#define G7_OFFSET 0x04 + +/** This macro defines an offset into the context for use in assembly. */ +#define L0_OFFSET 0x08 +/** This macro defines an offset into the context for use in assembly. */ +#define L1_OFFSET 0x0C +/** This macro defines an offset into the context for use in assembly. */ +#define L2_OFFSET 0x10 +/** This macro defines an offset into the context for use in assembly. */ +#define L3_OFFSET 0x14 +/** This macro defines an offset into the context for use in assembly. */ +#define L4_OFFSET 0x18 +/** This macro defines an offset into the context for use in assembly. */ +#define L5_OFFSET 0x1C +/** This macro defines an offset into the context for use in assembly. */ +#define L6_OFFSET 0x20 +/** This macro defines an offset into the context for use in assembly. */ +#define L7_OFFSET 0x24 + +/** This macro defines an offset into the context for use in assembly. */ +#define I0_OFFSET 0x28 +/** This macro defines an offset into the context for use in assembly. */ +#define I1_OFFSET 0x2C +/** This macro defines an offset into the context for use in assembly. */ +#define I2_OFFSET 0x30 +/** This macro defines an offset into the context for use in assembly. */ +#define I3_OFFSET 0x34 +/** This macro defines an offset into the context for use in assembly. */ +#define I4_OFFSET 0x38 +/** This macro defines an offset into the context for use in assembly. */ +#define I5_OFFSET 0x3C +/** This macro defines an offset into the context for use in assembly. */ +#define I6_FP_OFFSET 0x40 +/** This macro defines an offset into the context for use in assembly. */ +#define I7_OFFSET 0x44 + +/** This macro defines an offset into the context for use in assembly. */ +#define O6_SP_OFFSET 0x48 +/** This macro defines an offset into the context for use in assembly. */ +#define O7_OFFSET 0x4C + +/** This macro defines an offset into the context for use in assembly. */ +#define PSR_OFFSET 0x50 +/** This macro defines an offset into the context for use in assembly. */ +#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 + +#if defined(RTEMS_SMP) + #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 +#endif + +#ifndef ASM +/** + * @brief SPARC basic context. + * + * This structure defines floating point context area. + */ +struct Context_Control_fp { + /** This will contain the contents of the f0 and f1 register. */ + double f0_f1; + /** This will contain the contents of the f2 and f3 register. */ + double f2_f3; + /** This will contain the contents of the f4 and f5 register. */ + double f4_f5; + /** This will contain the contents of the f6 and f7 register. */ + double f6_f7; + /** This will contain the contents of the f8 and f9 register. */ + double f8_f9; + /** This will contain the contents of the f10 and f11 register. */ + double f10_f11; + /** This will contain the contents of the f12 and f13 register. */ + double f12_f13; + /** This will contain the contents of the f14 and f15 register. */ + double f14_f15; + /** This will contain the contents of the f16 and f17 register. */ + double f16_f17; + /** This will contain the contents of the f18 and f19 register. */ + double f18_f19; + /** This will contain the contents of the f20 and f21 register. */ + double f20_f21; + /** This will contain the contents of the f22 and f23 register. */ + double f22_f23; + /** This will contain the contents of the f24 and f25 register. */ + double f24_f25; + /** This will contain the contents of the f26 and f27 register. */ + double f26_f27; + /** This will contain the contents of the f28 and f29 register. */ + double f28_f29; + /** This will contain the contents of the f30 and f31 register. */ + double f30_f31; + /** This will contain the contents of the floating point status register. */ + uint32_t fsr; +}; + +#endif /* ASM */ + +/* + * Offsets of fields with Context_Control_fp for assembly routines. + */ + +/** This macro defines an offset into the FPU context for use in assembly. */ +#define FO_F1_OFFSET 0x00 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F2_F3_OFFSET 0x08 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F4_F5_OFFSET 0x10 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F6_F7_OFFSET 0x18 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F8_F9_OFFSET 0x20 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F1O_F11_OFFSET 0x28 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F12_F13_OFFSET 0x30 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F14_F15_OFFSET 0x38 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F16_F17_OFFSET 0x40 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F18_F19_OFFSET 0x48 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F2O_F21_OFFSET 0x50 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F22_F23_OFFSET 0x58 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F24_F25_OFFSET 0x60 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F26_F27_OFFSET 0x68 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F28_F29_OFFSET 0x70 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define F3O_F31_OFFSET 0x78 +/** This macro defines an offset into the FPU context for use in assembly. */ +#define FSR_OFFSET 0x80 + +/** This defines the size of the FPU context area for use in assembly. */ +#define CONTEXT_CONTROL_FP_SIZE 0x84 + +#ifndef ASM + +/** @} */ + +/** + * @brief Interrupt stack frame (ISF). + * + * Context saved on stack for an interrupt. + * + * NOTE: The PSR, PC, and NPC are only saved in this structure for the + * benefit of the user's handler. + */ +typedef struct { + /** On an interrupt, we must save the minimum stack frame. */ + SPARC_Minimum_stack_frame Stack_frame; + /** This is the offset of the PSR on an ISF. */ + uint32_t psr; + /** This is the offset of the XXX on an ISF. */ + uint32_t pc; + /** This is the offset of the XXX on an ISF. */ + uint32_t npc; + /** This is the offset of the g1 register on an ISF. */ + uint32_t g1; + /** This is the offset of the g2 register on an ISF. */ + uint32_t g2; + /** This is the offset of the g3 register on an ISF. */ + uint32_t g3; + /** This is the offset of the g4 register on an ISF. */ + uint32_t g4; + /** This is the offset of the g5 register on an ISF. */ + uint32_t g5; + /** This is the offset is reserved for alignment on an ISF. */ + uint32_t reserved_for_alignment; + /** This is the offset of the g7 register on an ISF. */ + uint32_t g7; + /** This is the offset of the i0 register on an ISF. */ + uint32_t i0; + /** This is the offset of the i1 register on an ISF. */ + uint32_t i1; + /** This is the offset of the i2 register on an ISF. */ + uint32_t i2; + /** This is the offset of the i3 register on an ISF. */ + uint32_t i3; + /** This is the offset of the i4 register on an ISF. */ + uint32_t i4; + /** This is the offset of the i5 register on an ISF. */ + uint32_t i5; + /** This is the offset of the i6 register on an ISF. */ + uint32_t i6_fp; + /** This is the offset of the i7 register on an ISF. */ + uint32_t i7; + /** This is the offset of the y register on an ISF. */ + uint32_t y; + /** This is the offset of the tpc register on an ISF. */ + uint32_t tpc; +} CPU_Interrupt_frame; + +#endif /* ASM */ + +#ifndef ASM +/** + * The following type defines an entry in the SPARC's trap table. + * + * NOTE: The instructions chosen are RTEMS dependent although one is + * obligated to use two of the four instructions to perform a + * long jump. The other instructions load one register with the + * trap type (a.k.a. vector) and another with the psr. + */ +typedef struct { + /** This will contain a "mov %psr, %l0" instruction. */ + uint32_t mov_psr_l0; + /** This will contain a "sethi %hi(_handler), %l4" instruction. */ + uint32_t sethi_of_handler_to_l4; + /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ + uint32_t jmp_to_low_of_handler_plus_l4; + /** This will contain a " mov _vector, %l3" instruction. */ + uint32_t mov_vector_l3; +} CPU_Trap_table_entry; + +/** + * This is the set of opcodes for the instructions loaded into a trap + * table entry. The routine which installs a handler is responsible + * for filling in the fields for the _handler address and the _vector + * trap type. + * + * The constants following this structure are masks for the fields which + * must be filled in when the handler is installed. + */ +extern const CPU_Trap_table_entry _CPU_Trap_slot_template; + +/** + * The size of the floating point context area. + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#endif + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 + +/** + * This defines the number of entries in the ISR_Vector_table managed + * by the executive. + * + * On the SPARC, there are really only 256 vectors. However, the executive + * has no easy, fast, reliable way to determine which traps are synchronous + * and which are asynchronous. By default, synchronous traps return to the + * instruction which caused the interrupt. So if you install a software + * trap handler as an executive interrupt handler (which is desirable since + * RTEMS takes care of window and register issues), then the executive needs + * to know that the return address is to the trap rather than the instruction + * following the trap. + * + * So vectors 0 through 255 are treated as regular asynchronous traps which + * provide the "correct" return address. Vectors 256 through 512 are assumed + * by the executive to be synchronous and to require that the return address + * be fudged. + * + * If you use this mechanism to install a trap handler which must reexecute + * the instruction which caused the trap, then it should be installed as + * an asynchronous trap. This will avoid the executive changing the return + * address. + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 + +/** + * The SPARC has 256 vectors but the port treats 256-512 as synchronous + * traps. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 + +/** + * This is the bit step in a vector number to indicate it is being installed + * as a synchronous trap. + */ +#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 + +/** + * This macro indicates that @a _trap as an asynchronous trap. + */ +#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) + +/** + * This macro indicates that @a _trap as a synchronous trap. + */ +#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) + +/** + * This macro returns the real hardware vector number associated with @a _trap. + */ +#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) + +/** + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * Should be large enough to run all tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * This appears to be a fairly generous number for the SPARC since + * represents a call depth of about 20 routines based on the minimum + * stack frame. + */ +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +/** + * What is the size of a pointer on this architecture? + */ +#define CPU_SIZEOF_POINTER 4 + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * On the SPARC, this is required for double word loads and stores. + */ +#define CPU_ALIGNMENT 8 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * Stack frames must be doubleword aligned according to the System V ABI for + * SPARC. + */ +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +#ifndef ASM + +/* + * ISR handler macros + */ + +/** + * Support routine to initialize the RTEMS vector table after it is allocated. + */ +#define _CPU_Initialize_vectors() + +/** + * Disable all interrupts for a critical section. The previous + * level is returned in _level. + */ +#define _CPU_ISR_Disable( _level ) \ + (_level) = sparc_disable_interrupts() + +/** + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of a critical section. The parameter + * _level is not modified. + */ +#define _CPU_ISR_Enable( _level ) \ + sparc_enable_interrupts( _level ) + +/** + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long critical + * sections into two or more parts. The parameter _level is not + * modified. + */ +#define _CPU_ISR_Flash( _level ) \ + sparc_flash_interrupts( _level ) + +#define _CPU_ISR_Is_enabled( _isr_cookie ) \ + sparc_interrupt_is_enabled( _isr_cookie ) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & SPARC_PSR_PIL_MASK ) == 0; +} + +/** + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a straight fashion are undefined. + */ +#define _CPU_ISR_Set_level( _newlevel ) \ + sparc_enable_interrupts( _newlevel << 8) + +/** + * @brief Obtain the current interrupt disable level. + * + * This method is invoked to return the current interrupt disable level. + * + * @return This method returns the current interrupt disable level. + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/** + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * @param[in] the_context points to the context area + * @param[in] stack_base is the low address of the allocated stack area + * @param[in] size is the size of the stack area in bytes + * @param[in] new_level is the interrupt level for the task + * @param[in] entry_point is the task's entry point + * @param[in] is_fp is set to TRUE if the task is a floating point task + * @param[in] tls_area is the thread-local storage (TLS) area + * + * NOTE: Implemented as a subroutine for the SPARC port. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/** + * This macro is invoked from _Thread_Handler to do whatever CPU + * specific magic is required that must be done in the context of + * the thread when it starts. + * + * On the SPARC, this is setting the frame pointer so GDB is happy. + * Make GDB stop unwinding at _Thread_Handler, previous register window + * Frame pointer is 0 and calling address must be a function with starting + * with a SAVE instruction. If return address is leaf-function (no SAVE) + * GDB will not look at prev reg window fp. + * + * _Thread_Handler is known to start with SAVE. + */ +#define _CPU_Context_Initialization_at_thread_begin() \ + do { \ + __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ + } while (0) + +/** + * This routine is responsible for somehow restarting the currently + * executing task. + * + * On the SPARC, this is is relatively painless but requires a small + * amount of wrapper code before using the regular restore code in + * of the context switch. + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/** + * @brief Nothing to do due to the synchronous or lazy floating point switch. + */ +#define _CPU_Context_Initialize_fp( _destination ) \ + do { } while ( 0 ) + +/** + * @brief Nothing to do due to the synchronous or lazy floating point switch. + */ +#define _CPU_Context_save_fp( _fp_context_ptr ) \ + do { } while ( 0 ) + +/** + * @brief Nothing to do due to the synchronous or lazy floating point switch. + */ +#define _CPU_Context_restore_fp( _fp_context_ptr ) \ + do { } while ( 0 ) +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ +extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) + RTEMS_NO_RETURN; + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +#if ( SPARC_HAS_BITSCAN == 0 ) + /** + * The SPARC port uses the generic C algorithm for bitfield scan if the + * CPU model does not have a scan instruction. + */ + #define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#else + #error "scan instruction not currently supported by RTEMS!!" +#endif + +/* end of Bitfield handler macros */ + +/* functions */ + +/** + * @brief SPARC specific initialization. + * + * This routine performs CPU dependent initialization. + */ +void _CPU_Initialize(void); + +/** + * @brief SPARC specific raw ISR installer. + * + * This routine installs @a new_handler to be directly called from the trap + * table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the new ISR handler + * @param[in] old_handler will contain the old ISR handler + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @brief SPARC specific RTEMS ISR installer. + * + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the new ISR handler + * @param[in] old_handler will contain the old ISR handler + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @brief SPARC specific context switch. + * + * This routine switches from the run context to the heir context. + * + * @param[in] run is the currently executing thread + * @param[in] heir will become the currently executing thread + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * @brief SPARC specific context restore. + * + * This routine is generally used only to restart self in an + * efficient manner. + * + * @param[in] new_context is the context to restore + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +#if defined(RTEMS_SMP) + uint32_t _CPU_SMP_Initialize( void ); + + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + void _CPU_SMP_Prepare_start_multitasking( void ); + + #if defined(__leon__) && !defined(RTEMS_PARAVIRT) + static inline uint32_t _CPU_SMP_Get_current_processor( void ) + { + return _LEON3_Get_current_processor(); + } + #else + uint32_t _CPU_SMP_Get_current_processor( void ); + #endif + + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + static inline void _CPU_SMP_Processor_event_receive( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } +#endif + +#if defined(SPARC_USE_LAZY_FP_SWITCH) +#define _CPU_Context_Destroy( _the_thread, _the_context ) \ + do { \ + Per_CPU_Control *cpu_self = _Per_CPU_Get(); \ + Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \ + if ( _fp_owner == _the_thread ) { \ + cpu_self->cpu_per_cpu.fp_owner = NULL; \ + } \ + } while ( 0 ) +#endif + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +typedef struct { + uint32_t trap; + CPU_Interrupt_frame *isf; +} CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @brief SPARC specific method to endian swap an uint32_t. + * + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * @param[in] value is the value to endian swap + * + * This version will work on any processor, but if you come across a better + * way for the SPARC PLEASE use it. The most common way to swap a 32-bit + * entity as shown below is not any more efficient on the SPARC. + * + * - swap least significant two bytes with 16-bit rotate + * - swap upper and lower 16-bits + * - swap most significant two bytes with 16-bit rotate + * + * It is not obvious how the SPARC can do significantly better than the + * generic code. gcc 2.7.0 only generates about 12 instructions for the + * following code at optimization level four (i.e. -O4). + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +/** + * @brief SPARC specific method to endian swap an uint16_t. + * + * The following routine swaps the endian format of a uint16_t. + * + * @param[in] value is the value to endian swap + */ +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void ); + +typedef CPU_Counter_ticks ( *SPARC_Counter_difference )( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +/* + * The SPARC processors supported by RTEMS have no built-in CPU counter + * support. We have to use some hardware counter module for this purpose, for + * example the GPTIMER instance used by the clock driver. The BSP must provide + * an implementation of the CPU counter read and difference functions. This + * allows the use of dynamic hardware enumeration. + */ +typedef struct { + SPARC_Counter_read counter_read; + SPARC_Counter_difference counter_difference; + volatile const CPU_Counter_ticks *counter_address; +} SPARC_Counter; + +extern const SPARC_Counter _SPARC_Counter; + +static inline CPU_Counter_ticks _CPU_Counter_read( void ) +{ + return ( *_SPARC_Counter.counter_read )(); +} + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return ( *_SPARC_Counter.counter_difference )( second, first ); +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..4f2311e755 --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h @@ -0,0 +1,155 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR) + * Copyright (c) 2013, 2016 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +/** This defines the size of the minimum stack frame. */ +#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60 + +/* + * Offsets of fields with CPU_Interrupt_frame for assembly routines. + */ + +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48 +/** This macro defines an offset into the ISF for use in assembly. */ +#define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c + +/** This defines the size of the ISF area for use in assembly. */ +#define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50 + +#define SPARC_FP_CONTEXT_OFFSET_F0_F1 0 +#define SPARC_FP_CONTEXT_OFFSET_F2_F3 8 +#define SPARC_FP_CONTEXT_OFFSET_F4_F5 16 +#define SPARC_FP_CONTEXT_OFFSET_F6_F7 24 +#define SPARC_FP_CONTEXT_OFFSET_F8_F9 32 +#define SPARC_FP_CONTEXT_OFFSET_F10_F11 40 +#define SPARC_FP_CONTEXT_OFFSET_F12_F13 48 +#define SPARC_FP_CONTEXT_OFFSET_F14_F15 56 +#define SPARC_FP_CONTEXT_OFFSET_F16_F17 64 +#define SPARC_FP_CONTEXT_OFFSET_F18_F19 72 +#define SPARC_FP_CONTEXT_OFFSET_F20_F21 80 +#define SPARC_FP_CONTEXT_OFFSET_F22_F23 88 +#define SPARC_FP_CONTEXT_OFFSET_F24_F25 96 +#define SPARC_FP_CONTEXT_OFFSET_F26_F27 104 +#define SPARC_FP_CONTEXT_OFFSET_F28_F29 112 +#define SPARC_FP_CONTEXT_OFFSET_F30_F31 120 +#define SPARC_FP_CONTEXT_OFFSET_FSR 128 + +#if ( SPARC_HAS_FPU == 1 ) + #define CPU_PER_CPU_CONTROL_SIZE 8 +#else + #define CPU_PER_CPU_CONTROL_SIZE 0 +#endif + +#if ( SPARC_HAS_FPU == 1 ) + /** + * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the + * Per_CPU_Control begin. + */ + #define SPARC_PER_CPU_FSR_OFFSET 0 + + #if defined(SPARC_USE_LAZY_FP_SWITCH) + /** + * @brief Offset of the CPU_Per_CPU_control::fp_owner field relative to the + * Per_CPU_Control begin. + */ + #define SPARC_PER_CPU_FP_OWNER_OFFSET 4 + #endif +#endif + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { +#if ( SPARC_HAS_FPU == 1 ) + /** + * @brief Memory location to store the FSR register during interrupt + * processing. + * + * This is a write-only field. The FSR is written to force a completion of + * floating point operations in progress. + */ + uint32_t fsr; + +#if defined(SPARC_USE_LAZY_FP_SWITCH) + /** + * @brief The current floating point owner. + */ + struct _Thread_Control *fp_owner; +#else + /* See Per_CPU_Control::Interrupt_frame */ + uint32_t reserved_for_alignment_of_interrupt_frame; +#endif +#endif +} CPU_Per_CPU_control; + +/** + * @brief The pointer to the current per-CPU control is available via register + * g6. + */ +register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); + +#define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current + +#define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing ) + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sparc/include/rtems/score/sparc.h b/cpukit/score/cpu/sparc/include/rtems/score/sparc.h new file mode 100644 index 0000000000..747d013559 --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/score/sparc.h @@ -0,0 +1,418 @@ +/** + * @file + * + * @brief Information Required to Build RTEMS for a Particular Member + * of the SPARC Family + * + * This file contains the information required to build + * RTEMS for a particular member of the SPARC family. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SPARC_H +#define _RTEMS_SCORE_SPARC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * + * Currently recognized feature flags: + * + * + SPARC_HAS_FPU + * 0 - no HW FPU + * 1 - has HW FPU (assumed to be compatible w/90C602) + * + * + SPARC_HAS_BITSCAN + * 0 - does not have scan instructions + * 1 - has scan instruction (not currently implemented) + * + * + SPARC_NUMBER_OF_REGISTER_WINDOWS + * 8 is the most common number supported by SPARC implementations. + * SPARC_PSR_CWP_MASK is derived from this value. + */ + +/** + * Some higher end SPARCs have a bitscan instructions. It would + * be nice to take advantage of them. Right now, there is no + * port to a CPU model with this feature and no (untested) code + * that is based on this feature flag. + */ +#define SPARC_HAS_BITSCAN 0 + +/** + * This should be OK until a port to a higher end SPARC processor + * is made that has more than 8 register windows. If this cannot + * be determined based on multilib settings (v7/v8/v9), then the + * cpu_asm.S code that depends on this will have to move to libcpu. + */ +#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 + +/** + * See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with + * Data Tag Parity Error" + */ +#if defined(__FIX_LEON3FT_B2BST) + #define SPARC_LEON3FT_B2BST_NOP nop +#else + #define SPARC_LEON3FT_B2BST_NOP +#endif + +/** + * This macro indicates whether this multilib variation has hardware + * floating point or not. We use the gcc cpp predefine _SOFT_FLOAT + * to determine that. + */ +#if defined(_SOFT_FLOAT) + #define SPARC_HAS_FPU 0 +#else + #define SPARC_HAS_FPU 1 +#endif + +/** + * This macro contains a string describing the multilib variant being + * build. + */ +#if SPARC_HAS_FPU + #define CPU_MODEL_NAME "w/FPU" +#else + #define CPU_MODEL_NAME "w/soft-float" +#endif + +/** + * Define the name of the CPU family. + */ +#define CPU_NAME "SPARC" + +/* + * Miscellaneous constants + */ + +/** + * PSR masks and starting bit positions + * + * NOTE: Reserved bits are ignored. + */ +#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) + #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ +#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) + #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ +#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) + #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ +#else + #error "Unsupported number of register windows for this cpu" +#endif + +/** This constant is a mask for the ET bits in the PSR. */ +#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ +/** This constant is a mask for the PS bits in the PSR. */ +#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ +/** This constant is a mask for the S bits in the PSR. */ +#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ +/** This constant is a mask for the PIL bits in the PSR. */ +#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ +/** This constant is a mask for the EF bits in the PSR. */ +#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ +/** This constant is a mask for the EC bits in the PSR. */ +#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ +/** This constant is a mask for the ICC bits in the PSR. */ +#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ +/** This constant is a mask for the VER bits in the PSR. */ +#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ +/** This constant is a mask for the IMPL bits in the PSR. */ +#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ + +/** This constant is the starting bit position of the CWP in the PSR. */ +#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ +/** This constant is the starting bit position of the ET in the PSR. */ +#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ +/** This constant is the starting bit position of the PS in the PSR. */ +#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ +/** This constant is the starting bit position of the S in the PSR. */ +#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ +/** This constant is the starting bit position of the PIL in the PSR. */ +#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ +/** This constant is the starting bit position of the EF in the PSR. */ +#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ +/** This constant is the starting bit position of the EC in the PSR. */ +#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ +/** This constant is the starting bit position of the ICC in the PSR. */ +#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ +/** This constant is the starting bit position of the VER in the PSR. */ +#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ +/** This constant is the starting bit position of the IMPL in the PSR. */ +#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ + +#define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28 + +/* SPARC Software Trap number definitions */ +#define SPARC_SWTRAP_SYSCALL 0 +#define SPARC_SWTRAP_IRQDIS 9 +#define SPARC_SWTRAP_IRQEN 10 +#if SPARC_HAS_FPU == 1 +#define SPARC_SWTRAP_IRQDIS_FP 11 +#endif + +#ifndef ASM + +/** + * This macro is a standard nop instruction. + */ +#define nop() \ + do { \ + __asm__ volatile ( "nop" ); \ + } while ( 0 ) + +/** + * @brief Macro to obtain the PSR. + * + * This macro returns the current contents of the PSR register in @a _psr. + */ +#if defined(RTEMS_PARAVIRT) + +uint32_t _SPARC_Get_PSR( void ); + +#define sparc_get_psr( _psr ) \ + (_psr) = _SPARC_Get_PSR() + +#else /* RTEMS_PARAVIRT */ + +#define sparc_get_psr( _psr ) \ + do { \ + (_psr) = 0; \ + __asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ + } while ( 0 ) + +#endif /* RTEMS_PARAVIRT */ + +/** + * @brief Macro to set the PSR. + * + * This macro sets the PSR register to the value in @a _psr. + */ +#if defined(RTEMS_PARAVIRT) + +void _SPARC_Set_PSR( uint32_t new_psr ); + +#define sparc_set_psr( _psr ) \ + _SPARC_Set_PSR( _psr ) + +#else /* RTEMS_PARAVIRT */ + +#define sparc_set_psr( _psr ) \ + do { \ + __asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ + nop(); \ + nop(); \ + nop(); \ + } while ( 0 ) + +#endif /* RTEMS_PARAVIRT */ + +/** + * @brief Macro to obtain the TBR. + * + * This macro returns the current contents of the TBR register in @a _tbr. + */ +#if defined(RTEMS_PARAVIRT) + +uint32_t _SPARC_Get_TBR( void ); + +#define sparc_get_tbr( _tbr ) \ + (_tbr) = _SPARC_Get_TBR() + +#else /* RTEMS_PARAVIRT */ + +#define sparc_get_tbr( _tbr ) \ + do { \ + (_tbr) = 0; /* to avoid unitialized warnings */ \ + __asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ + } while ( 0 ) + +#endif /* RTEMS_PARAVIRT */ + +/** + * @brief Macro to set the TBR. + * + * This macro sets the TBR register to the value in @a _tbr. + */ +#if defined(RTEMS_PARAVIRT) + +void _SPARC_Set_TBR( uint32_t new_tbr ); + +#define sparc_set_tbr( _tbr ) \ + _SPARC_Set_TBR((_tbr)) + +#else /* RTEMS_PARAVIRT */ + +#define sparc_set_tbr( _tbr ) \ + do { \ + __asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ + } while ( 0 ) + +#endif /* RTEMS_PARAVIRT */ + +/** + * @brief Macro to obtain the WIM. + * + * This macro returns the current contents of the WIM field in @a _wim. + */ +#define sparc_get_wim( _wim ) \ + do { \ + __asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ + } while ( 0 ) + +/** + * @brief Macro to set the WIM. + * + * This macro sets the WIM field to the value in @a _wim. + */ +#define sparc_set_wim( _wim ) \ + do { \ + __asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ + nop(); \ + nop(); \ + nop(); \ + } while ( 0 ) + +/** + * @brief Macro to obtain the Y register. + * + * This macro returns the current contents of the Y register in @a _y. + */ +#define sparc_get_y( _y ) \ + do { \ + __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ + } while ( 0 ) + +/** + * @brief Macro to set the Y register. + * + * This macro sets the Y register to the value in @a _y. + */ +#define sparc_set_y( _y ) \ + do { \ + __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ + } while ( 0 ) + +/** + * @brief SPARC disable processor interrupts. + * + * This method is invoked to disable all maskable interrupts. + * + * @return This method returns the entire PSR contents. + */ +static inline uint32_t sparc_disable_interrupts(void) +{ + register uint32_t psr __asm__("g1"); /* return value of trap handler */ + __asm__ volatile ( "ta %1\n\t" : "=r" (psr) : "i" (SPARC_SWTRAP_IRQDIS)); + return psr; +} + +/** + * @brief SPARC enable processor interrupts. + * + * This method is invoked to enable all maskable interrupts. + * + * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts. + */ +static inline void sparc_enable_interrupts(uint32_t psr) +{ + register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */ + + /* + * The trap instruction has a higher trap priority than the interrupts + * according to "The SPARC Architecture Manual: Version 8", Table 7-1 + * "Exception and Interrupt Request Priority and tt Values". Add a nop to + * prevent a trap instruction right after the interrupt enable trap. + */ + __asm__ volatile ( "ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr)); +} + +/** + * @brief SPARC exit through system call 1 + * + * This method is invoked to go into system error halt. The optional + * arguments can be given to hypervisor, hardware debugger, simulator or + * similar. + * + * System error mode is entered when taking a trap when traps have been + * disabled. What happens when error mode is entered depends on the motherboard. + * In a typical development systems the CPU relingish control to the debugger, + * simulator, hypervisor or similar. The following steps are taken: + * + * 1. Going into system error mode by Software Trap 0 + * 2. %g1=1 (syscall 1 - Exit) + * 3. %g2=Primary exit code + * 4. %g3=Secondary exit code. Dependends on %g2 exit type. + * + * This function never returns. + * + * @param[in] exitcode1 Primary exit code stored in CPU g2 register after exit + * @param[in] exitcode2 Primary exit code stored in CPU g3 register after exit + */ +void sparc_syscall_exit(uint32_t exitcode1, uint32_t exitcode2) + RTEMS_NO_RETURN; + +/** + * @brief SPARC flash processor interrupts. + * + * This method is invoked to temporarily enable all maskable interrupts. + * + * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts. + */ +#define sparc_flash_interrupts( _psr ) \ + do { \ + sparc_enable_interrupts( (_psr) ); \ + _psr = sparc_disable_interrupts(); \ + } while ( 0 ) + +/** + * @brief SPARC obtain interrupt level. + * + * This method is invoked to obtain the current interrupt disable level. + * + * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts. + */ +#define sparc_get_interrupt_level( _level ) \ + do { \ + register uint32_t _psr_level = 0; \ + \ + sparc_get_psr( _psr_level ); \ + (_level) = \ + (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ + } while ( 0 ) + +static inline uint32_t _LEON3_Get_current_processor( void ) +{ + uint32_t asr17; + + __asm__ volatile ( + "rd %%asr17, %0" + : "=&r" (asr17) + ); + + return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT; +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_SPARC_H */ diff --git a/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h new file mode 100644 index 0000000000..9f9999b063 --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SPARCIMPL_H +#define _RTEMS_SCORE_SPARCIMPL_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Provides a mutable alias to _SPARC_Counter for use in + * _SPARC_Counter_initialize(). The _SPARC_Counter and _SPARC_Counter_mutable + * are defined via the SPARC_COUNTER_DEFINITION define. + */ +extern SPARC_Counter _SPARC_Counter_mutable; + +CPU_Counter_ticks _SPARC_Counter_read_address( void ); + +CPU_Counter_ticks _SPARC_Counter_read_asr23( void ); + +CPU_Counter_ticks _SPARC_Counter_difference_normal( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +CPU_Counter_ticks _SPARC_Counter_difference_clock_period( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +/* + * Returns always a value of one regardless of the parameters. This prevents + * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe + * default. + */ +CPU_Counter_ticks _SPARC_Counter_difference_one( + CPU_Counter_ticks second, + CPU_Counter_ticks first +); + +static inline void _SPARC_Counter_initialize( + SPARC_Counter_read counter_read, + SPARC_Counter_difference counter_difference, + volatile const CPU_Counter_ticks *counter_address +) +{ + _SPARC_Counter_mutable.counter_read = counter_read; + _SPARC_Counter_mutable.counter_difference = counter_difference; + _SPARC_Counter_mutable.counter_address = counter_address; +} + +/* + * Defines the _SPARC_Counter and _SPARC_Counter_mutable global variables. + * Place this define in the global file scope of the CPU counter support file + * of the BSP. + */ +#define SPARC_COUNTER_DEFINITION \ + __asm__ ( \ + "\t.global\t_SPARC_Counter\n" \ + "\t.global\t_SPARC_Counter_mutable\n" \ + "\t.section\t.data._SPARC_Counter,\"aw\",@progbits\n" \ + "\t.align\t4\n" \ + "\t.type\t_SPARC_Counter, #object\n" \ + "\t.size\t_SPARC_Counter, 12\n" \ + "_SPARC_Counter:\n" \ + "_SPARC_Counter_mutable:\n" \ + "\t.long\t_SPARC_Counter_read_address\n" \ + "\t.long\t_SPARC_Counter_difference_one\n" \ + "\t.long\t_SPARC_Counter\n" \ + ) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _RTEMS_SCORE_SPARCIMPL_H */ diff --git a/cpukit/score/cpu/sparc/include/rtems/score/types.h b/cpukit/score/cpu/sparc/include/rtems/score/types.h new file mode 100644 index 0000000000..6419c9f15f --- /dev/null +++ b/cpukit/score/cpu/sparc/include/rtems/score/types.h @@ -0,0 +1,53 @@ +/** + * @file + * + * @brief SPARC CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * SPARC processor family. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +/** + * @brief SPARC ISR handler return type. + * + * This is the type which SPARC ISR Handlers return. + */ +typedef void sparc_isr; + +/** + * @brief SPARC ISR handler prototype. + * + * This is the prototype for SPARC ISR Handlers. + */ +typedef void ( *sparc_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/sparc/preinstall.am b/cpukit/score/cpu/sparc/preinstall.am deleted file mode 100644 index 13caf27e22..0000000000 --- a/cpukit/score/cpu/sparc/preinstall.am +++ /dev/null @@ -1,62 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/byteorder.h: include/libcpu/byteorder.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/byteorder.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/byteorder.h - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/sparc.h: rtems/score/sparc.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sparc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/sparc.h - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/sparcimpl.h: rtems/score/sparcimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sparcimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/sparcimpl.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/sparc/rtems/asm.h b/cpukit/score/cpu/sparc/rtems/asm.h deleted file mode 100644 index a2b11f63fc..0000000000 --- a/cpukit/score/cpu/sparc/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Entry for traps which jump to a programmer-specified trap handler. - */ - -#define TRAP(_vector, _handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -/* - * Used for the reset trap to avoid a supervisor instruction - */ - -#define RTRAP(_vector, _handler) \ - mov %g0, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h deleted file mode 100644 index 2b50592e08..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ /dev/null @@ -1,1202 +0,0 @@ -/** - * @file - * - * @brief SPARC CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC processor. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * The SPARC ABI is a bit special with respect to the floating point context. - * The complete floating point context is volatile. Thus, from an ABI point - * of view nothing needs to be saved and restored during a context switch. - * Instead the floating point context must be saved and restored during - * interrupt processing. Historically, the deferred floating point switch was - * used for SPARC and the complete floating point context is saved and - * restored during a context switch to the new floating point unit owner. - * This is a bit dangerous since post-switch actions (e.g. signal handlers) - * and context switch extensions may silently corrupt the floating point - * context. - * - * The floating point unit is disabled for interrupt handlers. Thus, in case - * an interrupt handler uses the floating point unit then this will result in a - * trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). - * - * In uniprocessor configurations, a lazy floating point context switch is - * used. In case an active floating point thread is interrupted (PSR[EF] == 1) - * and a thread dispatch is carried out, then this thread is registered as the - * floating point owner. When a floating point owner is present during a - * context switch, the floating point unit is disabled for the heir thread - * (PSR[EF] == 0). The floating point disabled trap checks that the use of the - * floating point unit is allowed and saves/restores the floating point context - * on demand. - * - * In SMP configurations, the deferred floating point switch is not supported - * in principle. So, use here a synchronous floating point switching. - * Synchronous means that the volatile floating point context is saved and - * restored around a thread dispatch issued during interrupt processing. Thus - * post-switch actions and context switch extensions may safely use the - * floating point unit. - */ -#if SPARC_HAS_FPU == 1 - #if defined(RTEMS_SMP) - #define SPARC_USE_SYNCHRONOUS_FP_SWITCH - #else - #define SPARC_USE_LAZY_FP_SWITCH - #endif -#endif - -/** - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * - If TRUE, then RTEMS allocates the vector table it internally manages. - * - If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * THe SPARC is a simple vectored architecture. Usually there is no - * PIC and the CPU directly vectors the interrupts. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * - If TRUE, then it must be installed during initialization. - * - If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * - If TRUE, then the memory is allocated during initialization. - * - If FALSE, then the memory is allocated during initialization. - * - * The SPARC does not have hardware support for switching to a - * dedicated interrupt stack. The port includes support for doing this - * in software. - * - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * The SPARC port does not pass an Interrupt Stack Frame pointer to - * interrupt handlers. - */ -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/** - * Does the CPU have hardware floating point? - * - * - If TRUE, then the FLOATING_POINT task attribute is supported. - * - If FALSE, then the FLOATING_POINT task attribute is ignored. - * - * This is set based upon the multilib settings. - */ -#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH) - #define CPU_HARDWARE_FP TRUE -#else - #define CPU_HARDWARE_FP FALSE -#endif - -/** - * The SPARC GCC port does not have a software floating point library - * that requires RTEMS assistance. - */ -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks FLOATING_POINT tasks implicitly? - * - * - If TRUE, then the FLOATING_POINT task attribute is assumed. - * - If FALSE, then the FLOATING_POINT task attribute is followed. - * - * The SPARC GCC port does not implicitly use floating point registers. - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * - If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * - If FALSE, then the IDLE task does not have a floating point context. - * - * The IDLE task does not have to be floating point on the SPARC. - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * - If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * - If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * The SPARC architecture does not have a low power or halt instruction. - * It is left to the BSP and/or CPU specific code to provide an IDLE - * thread body which is aware of low power modes. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * - If TRUE, then the grows upward. - * - If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ -#define CPU_STACK_GROWS_UP FALSE - -/* LEON3 systems may use a cache line size of 64 */ -#define CPU_CACHE_LINE_BYTES 64 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/** - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC has 16 interrupt levels in the PIL field of the PSR. - */ -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#ifndef ASM -/** - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ -typedef struct { - /** This is the offset of the l0 register. */ - uint32_t l0; - /** This is the offset of the l1 register. */ - uint32_t l1; - /** This is the offset of the l2 register. */ - uint32_t l2; - /** This is the offset of the l3 register. */ - uint32_t l3; - /** This is the offset of the l4 register. */ - uint32_t l4; - /** This is the offset of the l5 register. */ - uint32_t l5; - /** This is the offset of the l6 register. */ - uint32_t l6; - /** This is the offset of the l7 register. */ - uint32_t l7; - /** This is the offset of the l0 register. */ - uint32_t i0; - /** This is the offset of the i1 register. */ - uint32_t i1; - /** This is the offset of the i2 register. */ - uint32_t i2; - /** This is the offset of the i3 register. */ - uint32_t i3; - /** This is the offset of the i4 register. */ - uint32_t i4; - /** This is the offset of the i5 register. */ - uint32_t i5; - /** This is the offset of the i6 register. */ - uint32_t i6_fp; - /** This is the offset of the i7 register. */ - uint32_t i7; - /** This is the offset of the register used to return structures. */ - void *structure_return_address; - - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - /** This is the offset of the register for saved argument 0. */ - uint32_t saved_arg0; - /** This is the offset of the register for saved argument 1. */ - uint32_t saved_arg1; - /** This is the offset of the register for saved argument 2. */ - uint32_t saved_arg2; - /** This is the offset of the register for saved argument 3. */ - uint32_t saved_arg3; - /** This is the offset of the register for saved argument 4. */ - uint32_t saved_arg4; - /** This is the offset of the register for saved argument 5. */ - uint32_t saved_arg5; - /** This field pads the structure so ldd and std instructions can be used. */ - uint32_t pad0; -} SPARC_Minimum_stack_frame; - -#endif /* ASM */ - -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L1_OFFSET 0x04 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L2_OFFSET 0x08 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L3_OFFSET 0x0c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L4_OFFSET 0x10 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L5_OFFSET 0x14 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L6_OFFSET 0x18 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L7_OFFSET 0x1c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I0_OFFSET 0x20 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I1_OFFSET 0x24 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I2_OFFSET 0x28 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I3_OFFSET 0x2c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I4_OFFSET 0x30 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I5_OFFSET 0x34 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I7_OFFSET 0x3c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c - -#define CPU_MAXIMUM_PROCESSORS 32 - -/** - * @defgroup Contexts SPARC Context Structures - * - * @ingroup Score - * - * Generally there are 2 types of context to save. - * + Interrupt registers to save - * + Task level registers to save - * - * This means we have the following 3 context items: - * + task level context stuff:: Context_Control - * + floating point task stuff:: Context_Control_fp - * + special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ -/**@{**/ - -#ifndef ASM -typedef struct Context_Control_fp Context_Control_fp; - -/** - * @brief SPARC basic context. - * - * This structure defines the non-volatile integer and processor state context - * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY - * INTERFACE - SPARC Processor Supplement", Third Edition. - * - * The registers g2 through g4 are reserved for applications. GCC uses them as - * volatile registers by default. So they are treated like volatile registers - * in RTEMS as well. - * - * The register g6 contains the per-CPU control of the current processor. It - * is an invariant of the processor context. This register must not be saved - * and restored during context switches or interrupt services. - */ -typedef struct { - /** This will contain the contents of the g5 register. */ - uint32_t g5; - /** This will contain the contents of the g7 register. */ - uint32_t g7; - - /** - * This will contain the contents of the l0 and l1 registers. - * - * Using a double l0_and_l1 will put everything in this structure on a double - * word boundary which allows us to use double word loads and stores safely - * in the context switch. - */ - double l0_and_l1; - /** This will contain the contents of the l2 register. */ - uint32_t l2; - /** This will contain the contents of the l3 register. */ - uint32_t l3; - /** This will contain the contents of the l4 register. */ - uint32_t l4; - /** This will contain the contents of the l5 registeer.*/ - uint32_t l5; - /** This will contain the contents of the l6 register. */ - uint32_t l6; - /** This will contain the contents of the l7 register. */ - uint32_t l7; - - /** This will contain the contents of the i0 register. */ - uint32_t i0; - /** This will contain the contents of the i1 register. */ - uint32_t i1; - /** This will contain the contents of the i2 register. */ - uint32_t i2; - /** This will contain the contents of the i3 register. */ - uint32_t i3; - /** This will contain the contents of the i4 register. */ - uint32_t i4; - /** This will contain the contents of the i5 register. */ - uint32_t i5; - /** This will contain the contents of the i6 (e.g. frame pointer) register. */ - uint32_t i6_fp; - /** This will contain the contents of the i7 register. */ - uint32_t i7; - - /** This will contain the contents of the o6 (e.g. frame pointer) register. */ - uint32_t o6_sp; - /** - * This will contain the contents of the o7 (e.g. address of CALL - * instruction) register. - */ - uint32_t o7; - - /** This will contain the contents of the processor status register. */ - uint32_t psr; - /** - * This field is used to prevent heavy nesting of calls to _Thread_Dispatch - * on an interrupted task's stack. This is problematic on the slower - * SPARC CPU models at high interrupt rates. - */ - uint32_t isr_dispatch_disable; - -#if defined(SPARC_USE_LAZY_FP_SWITCH) - Context_Control_fp *fp_context; -#endif - -#if defined(RTEMS_SMP) - volatile uint32_t is_executing; -#endif -} Context_Control; - -/** - * This macro provides a CPU independent way for RTEMS to access the - * stack pointer in a context structure. The actual name and offset is - * CPU architecture dependent. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -/** This macro defines an offset into the context for use in assembly. */ -#define G5_OFFSET 0x00 -/** This macro defines an offset into the context for use in assembly. */ -#define G7_OFFSET 0x04 - -/** This macro defines an offset into the context for use in assembly. */ -#define L0_OFFSET 0x08 -/** This macro defines an offset into the context for use in assembly. */ -#define L1_OFFSET 0x0C -/** This macro defines an offset into the context for use in assembly. */ -#define L2_OFFSET 0x10 -/** This macro defines an offset into the context for use in assembly. */ -#define L3_OFFSET 0x14 -/** This macro defines an offset into the context for use in assembly. */ -#define L4_OFFSET 0x18 -/** This macro defines an offset into the context for use in assembly. */ -#define L5_OFFSET 0x1C -/** This macro defines an offset into the context for use in assembly. */ -#define L6_OFFSET 0x20 -/** This macro defines an offset into the context for use in assembly. */ -#define L7_OFFSET 0x24 - -/** This macro defines an offset into the context for use in assembly. */ -#define I0_OFFSET 0x28 -/** This macro defines an offset into the context for use in assembly. */ -#define I1_OFFSET 0x2C -/** This macro defines an offset into the context for use in assembly. */ -#define I2_OFFSET 0x30 -/** This macro defines an offset into the context for use in assembly. */ -#define I3_OFFSET 0x34 -/** This macro defines an offset into the context for use in assembly. */ -#define I4_OFFSET 0x38 -/** This macro defines an offset into the context for use in assembly. */ -#define I5_OFFSET 0x3C -/** This macro defines an offset into the context for use in assembly. */ -#define I6_FP_OFFSET 0x40 -/** This macro defines an offset into the context for use in assembly. */ -#define I7_OFFSET 0x44 - -/** This macro defines an offset into the context for use in assembly. */ -#define O6_SP_OFFSET 0x48 -/** This macro defines an offset into the context for use in assembly. */ -#define O7_OFFSET 0x4C - -/** This macro defines an offset into the context for use in assembly. */ -#define PSR_OFFSET 0x50 -/** This macro defines an offset into the context for use in assembly. */ -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 - -#if defined(RTEMS_SMP) - #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 -#endif - -#ifndef ASM -/** - * @brief SPARC basic context. - * - * This structure defines floating point context area. - */ -struct Context_Control_fp { - /** This will contain the contents of the f0 and f1 register. */ - double f0_f1; - /** This will contain the contents of the f2 and f3 register. */ - double f2_f3; - /** This will contain the contents of the f4 and f5 register. */ - double f4_f5; - /** This will contain the contents of the f6 and f7 register. */ - double f6_f7; - /** This will contain the contents of the f8 and f9 register. */ - double f8_f9; - /** This will contain the contents of the f10 and f11 register. */ - double f10_f11; - /** This will contain the contents of the f12 and f13 register. */ - double f12_f13; - /** This will contain the contents of the f14 and f15 register. */ - double f14_f15; - /** This will contain the contents of the f16 and f17 register. */ - double f16_f17; - /** This will contain the contents of the f18 and f19 register. */ - double f18_f19; - /** This will contain the contents of the f20 and f21 register. */ - double f20_f21; - /** This will contain the contents of the f22 and f23 register. */ - double f22_f23; - /** This will contain the contents of the f24 and f25 register. */ - double f24_f25; - /** This will contain the contents of the f26 and f27 register. */ - double f26_f27; - /** This will contain the contents of the f28 and f29 register. */ - double f28_f29; - /** This will contain the contents of the f30 and f31 register. */ - double f30_f31; - /** This will contain the contents of the floating point status register. */ - uint32_t fsr; -}; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -/** This macro defines an offset into the FPU context for use in assembly. */ -#define FO_F1_OFFSET 0x00 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F2_F3_OFFSET 0x08 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F4_F5_OFFSET 0x10 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F6_F7_OFFSET 0x18 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F8_F9_OFFSET 0x20 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F1O_F11_OFFSET 0x28 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F12_F13_OFFSET 0x30 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F14_F15_OFFSET 0x38 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F16_F17_OFFSET 0x40 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F18_F19_OFFSET 0x48 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F2O_F21_OFFSET 0x50 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F22_F23_OFFSET 0x58 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F24_F25_OFFSET 0x60 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F26_F27_OFFSET 0x68 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F28_F29_OFFSET 0x70 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F3O_F31_OFFSET 0x78 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define FSR_OFFSET 0x80 - -/** This defines the size of the FPU context area for use in assembly. */ -#define CONTEXT_CONTROL_FP_SIZE 0x84 - -#ifndef ASM - -/** @} */ - -/** - * @brief Interrupt stack frame (ISF). - * - * Context saved on stack for an interrupt. - * - * NOTE: The PSR, PC, and NPC are only saved in this structure for the - * benefit of the user's handler. - */ -typedef struct { - /** On an interrupt, we must save the minimum stack frame. */ - SPARC_Minimum_stack_frame Stack_frame; - /** This is the offset of the PSR on an ISF. */ - uint32_t psr; - /** This is the offset of the XXX on an ISF. */ - uint32_t pc; - /** This is the offset of the XXX on an ISF. */ - uint32_t npc; - /** This is the offset of the g1 register on an ISF. */ - uint32_t g1; - /** This is the offset of the g2 register on an ISF. */ - uint32_t g2; - /** This is the offset of the g3 register on an ISF. */ - uint32_t g3; - /** This is the offset of the g4 register on an ISF. */ - uint32_t g4; - /** This is the offset of the g5 register on an ISF. */ - uint32_t g5; - /** This is the offset is reserved for alignment on an ISF. */ - uint32_t reserved_for_alignment; - /** This is the offset of the g7 register on an ISF. */ - uint32_t g7; - /** This is the offset of the i0 register on an ISF. */ - uint32_t i0; - /** This is the offset of the i1 register on an ISF. */ - uint32_t i1; - /** This is the offset of the i2 register on an ISF. */ - uint32_t i2; - /** This is the offset of the i3 register on an ISF. */ - uint32_t i3; - /** This is the offset of the i4 register on an ISF. */ - uint32_t i4; - /** This is the offset of the i5 register on an ISF. */ - uint32_t i5; - /** This is the offset of the i6 register on an ISF. */ - uint32_t i6_fp; - /** This is the offset of the i7 register on an ISF. */ - uint32_t i7; - /** This is the offset of the y register on an ISF. */ - uint32_t y; - /** This is the offset of the tpc register on an ISF. */ - uint32_t tpc; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -#ifndef ASM -/** - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -typedef struct { - /** This will contain a "mov %psr, %l0" instruction. */ - uint32_t mov_psr_l0; - /** This will contain a "sethi %hi(_handler), %l4" instruction. */ - uint32_t sethi_of_handler_to_l4; - /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ - uint32_t jmp_to_low_of_handler_plus_l4; - /** This will contain a " mov _vector, %l3" instruction. */ - uint32_t mov_vector_l3; -} CPU_Trap_table_entry; - -/** - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/** - * The size of the floating point context area. - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/** - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 - -/** - * The SPARC has 256 vectors but the port treats 256-512 as synchronous - * traps. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 - -/** - * This is the bit step in a vector number to indicate it is being installed - * as a synchronous trap. - */ -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 - -/** - * This macro indicates that @a _trap as an asynchronous trap. - */ -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) - -/** - * This macro indicates that @a _trap as a synchronous trap. - */ -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) - -/** - * This macro returns the real hardware vector number associated with @a _trap. - */ -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/** - * What is the size of a pointer on this architecture? - */ -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * Stack frames must be doubleword aligned according to the System V ABI for - * SPARC. - */ -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -#ifndef ASM - -/* - * ISR handler macros - */ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ -#define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/** - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -#define _CPU_ISR_Is_enabled( _isr_cookie ) \ - sparc_interrupt_is_enabled( _isr_cookie ) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & SPARC_PSR_PIL_MASK ) == 0; -} - -/** - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel << 8) - -/** - * @brief Obtain the current interrupt disable level. - * - * This method is invoked to return the current interrupt disable level. - * - * @return This method returns the current interrupt disable level. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * @param[in] the_context points to the context area - * @param[in] stack_base is the low address of the allocated stack area - * @param[in] size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to TRUE if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/** - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @brief Nothing to do due to the synchronous or lazy floating point switch. - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - do { } while ( 0 ) - -/** - * @brief Nothing to do due to the synchronous or lazy floating point switch. - */ -#define _CPU_Context_save_fp( _fp_context_ptr ) \ - do { } while ( 0 ) - -/** - * @brief Nothing to do due to the synchronous or lazy floating point switch. - */ -#define _CPU_Context_restore_fp( _fp_context_ptr ) \ - do { } while ( 0 ) -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ -extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) - RTEMS_NO_RETURN; - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -#if ( SPARC_HAS_BITSCAN == 0 ) - /** - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - #define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#else - #error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* functions */ - -/** - * @brief SPARC specific initialization. - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -/** - * @brief SPARC specific raw ISR installer. - * - * This routine installs @a new_handler to be directly called from the trap - * table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the new ISR handler - * @param[in] old_handler will contain the old ISR handler - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief SPARC specific RTEMS ISR installer. - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the new ISR handler - * @param[in] old_handler will contain the old ISR handler - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief SPARC specific context switch. - * - * This routine switches from the run context to the heir context. - * - * @param[in] run is the currently executing thread - * @param[in] heir will become the currently executing thread - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @brief SPARC specific context restore. - * - * This routine is generally used only to restart self in an - * efficient manner. - * - * @param[in] new_context is the context to restore - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -#if defined(RTEMS_SMP) - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - #if defined(__leon__) && !defined(RTEMS_PARAVIRT) - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - return _LEON3_Get_current_processor(); - } - #else - uint32_t _CPU_SMP_Get_current_processor( void ); - #endif - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -#if defined(SPARC_USE_LAZY_FP_SWITCH) -#define _CPU_Context_Destroy( _the_thread, _the_context ) \ - do { \ - Per_CPU_Control *cpu_self = _Per_CPU_Get(); \ - Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \ - if ( _fp_owner == _the_thread ) { \ - cpu_self->cpu_per_cpu.fp_owner = NULL; \ - } \ - } while ( 0 ) -#endif - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -typedef struct { - uint32_t trap; - CPU_Interrupt_frame *isf; -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @brief SPARC specific method to endian swap an uint32_t. - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * @param[in] value is the value to endian swap - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * - swap least significant two bytes with 16-bit rotate - * - swap upper and lower 16-bits - * - swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @brief SPARC specific method to endian swap an uint16_t. - * - * The following routine swaps the endian format of a uint16_t. - * - * @param[in] value is the value to endian swap - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void ); - -typedef CPU_Counter_ticks ( *SPARC_Counter_difference )( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -/* - * The SPARC processors supported by RTEMS have no built-in CPU counter - * support. We have to use some hardware counter module for this purpose, for - * example the GPTIMER instance used by the clock driver. The BSP must provide - * an implementation of the CPU counter read and difference functions. This - * allows the use of dynamic hardware enumeration. - */ -typedef struct { - SPARC_Counter_read counter_read; - SPARC_Counter_difference counter_difference; - volatile const CPU_Counter_ticks *counter_address; -} SPARC_Counter; - -extern const SPARC_Counter _SPARC_Counter; - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - return ( *_SPARC_Counter.counter_read )(); -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return ( *_SPARC_Counter.counter_difference )( second, first ); -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/cpuatomic.h b/cpukit/score/cpu/sparc/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h deleted file mode 100644 index 4f2311e755..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR) - * Copyright (c) 2013, 2016 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -/** This defines the size of the minimum stack frame. */ -#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60 - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c - -/** This defines the size of the ISF area for use in assembly. */ -#define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50 - -#define SPARC_FP_CONTEXT_OFFSET_F0_F1 0 -#define SPARC_FP_CONTEXT_OFFSET_F2_F3 8 -#define SPARC_FP_CONTEXT_OFFSET_F4_F5 16 -#define SPARC_FP_CONTEXT_OFFSET_F6_F7 24 -#define SPARC_FP_CONTEXT_OFFSET_F8_F9 32 -#define SPARC_FP_CONTEXT_OFFSET_F10_F11 40 -#define SPARC_FP_CONTEXT_OFFSET_F12_F13 48 -#define SPARC_FP_CONTEXT_OFFSET_F14_F15 56 -#define SPARC_FP_CONTEXT_OFFSET_F16_F17 64 -#define SPARC_FP_CONTEXT_OFFSET_F18_F19 72 -#define SPARC_FP_CONTEXT_OFFSET_F20_F21 80 -#define SPARC_FP_CONTEXT_OFFSET_F22_F23 88 -#define SPARC_FP_CONTEXT_OFFSET_F24_F25 96 -#define SPARC_FP_CONTEXT_OFFSET_F26_F27 104 -#define SPARC_FP_CONTEXT_OFFSET_F28_F29 112 -#define SPARC_FP_CONTEXT_OFFSET_F30_F31 120 -#define SPARC_FP_CONTEXT_OFFSET_FSR 128 - -#if ( SPARC_HAS_FPU == 1 ) - #define CPU_PER_CPU_CONTROL_SIZE 8 -#else - #define CPU_PER_CPU_CONTROL_SIZE 0 -#endif - -#if ( SPARC_HAS_FPU == 1 ) - /** - * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the - * Per_CPU_Control begin. - */ - #define SPARC_PER_CPU_FSR_OFFSET 0 - - #if defined(SPARC_USE_LAZY_FP_SWITCH) - /** - * @brief Offset of the CPU_Per_CPU_control::fp_owner field relative to the - * Per_CPU_Control begin. - */ - #define SPARC_PER_CPU_FP_OWNER_OFFSET 4 - #endif -#endif - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { -#if ( SPARC_HAS_FPU == 1 ) - /** - * @brief Memory location to store the FSR register during interrupt - * processing. - * - * This is a write-only field. The FSR is written to force a completion of - * floating point operations in progress. - */ - uint32_t fsr; - -#if defined(SPARC_USE_LAZY_FP_SWITCH) - /** - * @brief The current floating point owner. - */ - struct _Thread_Control *fp_owner; -#else - /* See Per_CPU_Control::Interrupt_frame */ - uint32_t reserved_for_alignment_of_interrupt_frame; -#endif -#endif -} CPU_Per_CPU_control; - -/** - * @brief The pointer to the current per-CPU control is available via register - * g6. - */ -register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); - -#define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current - -#define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing ) - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h b/cpukit/score/cpu/sparc/rtems/score/sparc.h deleted file mode 100644 index 747d013559..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/sparc.h +++ /dev/null @@ -1,418 +0,0 @@ -/** - * @file - * - * @brief Information Required to Build RTEMS for a Particular Member - * of the SPARC Family - * - * This file contains the information required to build - * RTEMS for a particular member of the SPARC family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SPARC_H -#define _RTEMS_SCORE_SPARC_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * - * Currently recognized feature flags: - * - * + SPARC_HAS_FPU - * 0 - no HW FPU - * 1 - has HW FPU (assumed to be compatible w/90C602) - * - * + SPARC_HAS_BITSCAN - * 0 - does not have scan instructions - * 1 - has scan instruction (not currently implemented) - * - * + SPARC_NUMBER_OF_REGISTER_WINDOWS - * 8 is the most common number supported by SPARC implementations. - * SPARC_PSR_CWP_MASK is derived from this value. - */ - -/** - * Some higher end SPARCs have a bitscan instructions. It would - * be nice to take advantage of them. Right now, there is no - * port to a CPU model with this feature and no (untested) code - * that is based on this feature flag. - */ -#define SPARC_HAS_BITSCAN 0 - -/** - * This should be OK until a port to a higher end SPARC processor - * is made that has more than 8 register windows. If this cannot - * be determined based on multilib settings (v7/v8/v9), then the - * cpu_asm.S code that depends on this will have to move to libcpu. - */ -#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 - -/** - * See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with - * Data Tag Parity Error" - */ -#if defined(__FIX_LEON3FT_B2BST) - #define SPARC_LEON3FT_B2BST_NOP nop -#else - #define SPARC_LEON3FT_B2BST_NOP -#endif - -/** - * This macro indicates whether this multilib variation has hardware - * floating point or not. We use the gcc cpp predefine _SOFT_FLOAT - * to determine that. - */ -#if defined(_SOFT_FLOAT) - #define SPARC_HAS_FPU 0 -#else - #define SPARC_HAS_FPU 1 -#endif - -/** - * This macro contains a string describing the multilib variant being - * build. - */ -#if SPARC_HAS_FPU - #define CPU_MODEL_NAME "w/FPU" -#else - #define CPU_MODEL_NAME "w/soft-float" -#endif - -/** - * Define the name of the CPU family. - */ -#define CPU_NAME "SPARC" - -/* - * Miscellaneous constants - */ - -/** - * PSR masks and starting bit positions - * - * NOTE: Reserved bits are ignored. - */ -#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) - #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ -#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) - #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ -#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) - #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ -#else - #error "Unsupported number of register windows for this cpu" -#endif - -/** This constant is a mask for the ET bits in the PSR. */ -#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ -/** This constant is a mask for the PS bits in the PSR. */ -#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ -/** This constant is a mask for the S bits in the PSR. */ -#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ -/** This constant is a mask for the PIL bits in the PSR. */ -#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ -/** This constant is a mask for the EF bits in the PSR. */ -#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ -/** This constant is a mask for the EC bits in the PSR. */ -#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ -/** This constant is a mask for the ICC bits in the PSR. */ -#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ -/** This constant is a mask for the VER bits in the PSR. */ -#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ -/** This constant is a mask for the IMPL bits in the PSR. */ -#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ - -/** This constant is the starting bit position of the CWP in the PSR. */ -#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ -/** This constant is the starting bit position of the ET in the PSR. */ -#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ -/** This constant is the starting bit position of the PS in the PSR. */ -#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ -/** This constant is the starting bit position of the S in the PSR. */ -#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ -/** This constant is the starting bit position of the PIL in the PSR. */ -#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ -/** This constant is the starting bit position of the EF in the PSR. */ -#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ -/** This constant is the starting bit position of the EC in the PSR. */ -#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ -/** This constant is the starting bit position of the ICC in the PSR. */ -#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ -/** This constant is the starting bit position of the VER in the PSR. */ -#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ -/** This constant is the starting bit position of the IMPL in the PSR. */ -#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ - -#define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28 - -/* SPARC Software Trap number definitions */ -#define SPARC_SWTRAP_SYSCALL 0 -#define SPARC_SWTRAP_IRQDIS 9 -#define SPARC_SWTRAP_IRQEN 10 -#if SPARC_HAS_FPU == 1 -#define SPARC_SWTRAP_IRQDIS_FP 11 -#endif - -#ifndef ASM - -/** - * This macro is a standard nop instruction. - */ -#define nop() \ - do { \ - __asm__ volatile ( "nop" ); \ - } while ( 0 ) - -/** - * @brief Macro to obtain the PSR. - * - * This macro returns the current contents of the PSR register in @a _psr. - */ -#if defined(RTEMS_PARAVIRT) - -uint32_t _SPARC_Get_PSR( void ); - -#define sparc_get_psr( _psr ) \ - (_psr) = _SPARC_Get_PSR() - -#else /* RTEMS_PARAVIRT */ - -#define sparc_get_psr( _psr ) \ - do { \ - (_psr) = 0; \ - __asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ - } while ( 0 ) - -#endif /* RTEMS_PARAVIRT */ - -/** - * @brief Macro to set the PSR. - * - * This macro sets the PSR register to the value in @a _psr. - */ -#if defined(RTEMS_PARAVIRT) - -void _SPARC_Set_PSR( uint32_t new_psr ); - -#define sparc_set_psr( _psr ) \ - _SPARC_Set_PSR( _psr ) - -#else /* RTEMS_PARAVIRT */ - -#define sparc_set_psr( _psr ) \ - do { \ - __asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ - nop(); \ - nop(); \ - nop(); \ - } while ( 0 ) - -#endif /* RTEMS_PARAVIRT */ - -/** - * @brief Macro to obtain the TBR. - * - * This macro returns the current contents of the TBR register in @a _tbr. - */ -#if defined(RTEMS_PARAVIRT) - -uint32_t _SPARC_Get_TBR( void ); - -#define sparc_get_tbr( _tbr ) \ - (_tbr) = _SPARC_Get_TBR() - -#else /* RTEMS_PARAVIRT */ - -#define sparc_get_tbr( _tbr ) \ - do { \ - (_tbr) = 0; /* to avoid unitialized warnings */ \ - __asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ - } while ( 0 ) - -#endif /* RTEMS_PARAVIRT */ - -/** - * @brief Macro to set the TBR. - * - * This macro sets the TBR register to the value in @a _tbr. - */ -#if defined(RTEMS_PARAVIRT) - -void _SPARC_Set_TBR( uint32_t new_tbr ); - -#define sparc_set_tbr( _tbr ) \ - _SPARC_Set_TBR((_tbr)) - -#else /* RTEMS_PARAVIRT */ - -#define sparc_set_tbr( _tbr ) \ - do { \ - __asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ - } while ( 0 ) - -#endif /* RTEMS_PARAVIRT */ - -/** - * @brief Macro to obtain the WIM. - * - * This macro returns the current contents of the WIM field in @a _wim. - */ -#define sparc_get_wim( _wim ) \ - do { \ - __asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ - } while ( 0 ) - -/** - * @brief Macro to set the WIM. - * - * This macro sets the WIM field to the value in @a _wim. - */ -#define sparc_set_wim( _wim ) \ - do { \ - __asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ - nop(); \ - nop(); \ - nop(); \ - } while ( 0 ) - -/** - * @brief Macro to obtain the Y register. - * - * This macro returns the current contents of the Y register in @a _y. - */ -#define sparc_get_y( _y ) \ - do { \ - __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -/** - * @brief Macro to set the Y register. - * - * This macro sets the Y register to the value in @a _y. - */ -#define sparc_set_y( _y ) \ - do { \ - __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -/** - * @brief SPARC disable processor interrupts. - * - * This method is invoked to disable all maskable interrupts. - * - * @return This method returns the entire PSR contents. - */ -static inline uint32_t sparc_disable_interrupts(void) -{ - register uint32_t psr __asm__("g1"); /* return value of trap handler */ - __asm__ volatile ( "ta %1\n\t" : "=r" (psr) : "i" (SPARC_SWTRAP_IRQDIS)); - return psr; -} - -/** - * @brief SPARC enable processor interrupts. - * - * This method is invoked to enable all maskable interrupts. - * - * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts. - */ -static inline void sparc_enable_interrupts(uint32_t psr) -{ - register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */ - - /* - * The trap instruction has a higher trap priority than the interrupts - * according to "The SPARC Architecture Manual: Version 8", Table 7-1 - * "Exception and Interrupt Request Priority and tt Values". Add a nop to - * prevent a trap instruction right after the interrupt enable trap. - */ - __asm__ volatile ( "ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr)); -} - -/** - * @brief SPARC exit through system call 1 - * - * This method is invoked to go into system error halt. The optional - * arguments can be given to hypervisor, hardware debugger, simulator or - * similar. - * - * System error mode is entered when taking a trap when traps have been - * disabled. What happens when error mode is entered depends on the motherboard. - * In a typical development systems the CPU relingish control to the debugger, - * simulator, hypervisor or similar. The following steps are taken: - * - * 1. Going into system error mode by Software Trap 0 - * 2. %g1=1 (syscall 1 - Exit) - * 3. %g2=Primary exit code - * 4. %g3=Secondary exit code. Dependends on %g2 exit type. - * - * This function never returns. - * - * @param[in] exitcode1 Primary exit code stored in CPU g2 register after exit - * @param[in] exitcode2 Primary exit code stored in CPU g3 register after exit - */ -void sparc_syscall_exit(uint32_t exitcode1, uint32_t exitcode2) - RTEMS_NO_RETURN; - -/** - * @brief SPARC flash processor interrupts. - * - * This method is invoked to temporarily enable all maskable interrupts. - * - * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts. - */ -#define sparc_flash_interrupts( _psr ) \ - do { \ - sparc_enable_interrupts( (_psr) ); \ - _psr = sparc_disable_interrupts(); \ - } while ( 0 ) - -/** - * @brief SPARC obtain interrupt level. - * - * This method is invoked to obtain the current interrupt disable level. - * - * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts. - */ -#define sparc_get_interrupt_level( _level ) \ - do { \ - register uint32_t _psr_level = 0; \ - \ - sparc_get_psr( _psr_level ); \ - (_level) = \ - (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ - } while ( 0 ) - -static inline uint32_t _LEON3_Get_current_processor( void ) -{ - uint32_t asr17; - - __asm__ volatile ( - "rd %%asr17, %0" - : "=&r" (asr17) - ); - - return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT; -} - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_SPARC_H */ diff --git a/cpukit/score/cpu/sparc/rtems/score/sparcimpl.h b/cpukit/score/cpu/sparc/rtems/score/sparcimpl.h deleted file mode 100644 index 9f9999b063..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/sparcimpl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2016 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SPARCIMPL_H -#define _RTEMS_SCORE_SPARCIMPL_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* - * Provides a mutable alias to _SPARC_Counter for use in - * _SPARC_Counter_initialize(). The _SPARC_Counter and _SPARC_Counter_mutable - * are defined via the SPARC_COUNTER_DEFINITION define. - */ -extern SPARC_Counter _SPARC_Counter_mutable; - -CPU_Counter_ticks _SPARC_Counter_read_address( void ); - -CPU_Counter_ticks _SPARC_Counter_read_asr23( void ); - -CPU_Counter_ticks _SPARC_Counter_difference_normal( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -CPU_Counter_ticks _SPARC_Counter_difference_clock_period( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -/* - * Returns always a value of one regardless of the parameters. This prevents - * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe - * default. - */ -CPU_Counter_ticks _SPARC_Counter_difference_one( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -static inline void _SPARC_Counter_initialize( - SPARC_Counter_read counter_read, - SPARC_Counter_difference counter_difference, - volatile const CPU_Counter_ticks *counter_address -) -{ - _SPARC_Counter_mutable.counter_read = counter_read; - _SPARC_Counter_mutable.counter_difference = counter_difference; - _SPARC_Counter_mutable.counter_address = counter_address; -} - -/* - * Defines the _SPARC_Counter and _SPARC_Counter_mutable global variables. - * Place this define in the global file scope of the CPU counter support file - * of the BSP. - */ -#define SPARC_COUNTER_DEFINITION \ - __asm__ ( \ - "\t.global\t_SPARC_Counter\n" \ - "\t.global\t_SPARC_Counter_mutable\n" \ - "\t.section\t.data._SPARC_Counter,\"aw\",@progbits\n" \ - "\t.align\t4\n" \ - "\t.type\t_SPARC_Counter, #object\n" \ - "\t.size\t_SPARC_Counter, 12\n" \ - "_SPARC_Counter:\n" \ - "_SPARC_Counter_mutable:\n" \ - "\t.long\t_SPARC_Counter_read_address\n" \ - "\t.long\t_SPARC_Counter_difference_one\n" \ - "\t.long\t_SPARC_Counter\n" \ - ) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _RTEMS_SCORE_SPARCIMPL_H */ diff --git a/cpukit/score/cpu/sparc/rtems/score/types.h b/cpukit/score/cpu/sparc/rtems/score/types.h deleted file mode 100644 index 6419c9f15f..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/types.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * - * @brief SPARC CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * SPARC processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** - * @brief SPARC ISR handler return type. - * - * This is the type which SPARC ISR Handlers return. - */ -typedef void sparc_isr; - -/** - * @brief SPARC ISR handler prototype. - * - * This is the prototype for SPARC ISR Handlers. - */ -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sparc64/Makefile.am b/cpukit/score/cpu/sparc64/Makefile.am index 491c197b81..2afd3edead 100644 --- a/cpukit/score/cpu/sparc64/Makefile.am +++ b/cpukit/score/cpu/sparc64/Makefile.am @@ -1,23 +1,13 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - #include_rtems_sparc64dir = $(includedir)/rtems/sparc64 #include_rtems_sparc64_HEADERS = -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/sparc64.h -include_rtems_score_HEADERS += rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = context.S cpu.c libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += sparc64-exception-frame-print.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/sparc64/headers.am b/cpukit/score/cpu/sparc64/headers.am new file mode 100644 index 0000000000..9b54d09ece --- /dev/null +++ b/cpukit/score/cpu/sparc64/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/sparc64.h +include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/sparc64/include/rtems/asm.h b/cpukit/score/cpu/sparc64/include/rtems/asm.h new file mode 100644 index 0000000000..f4448b03a5 --- /dev/null +++ b/cpukit/score/cpu/sparc64/include/rtems/asm.h @@ -0,0 +1,103 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#ifndef __ASM__ +#define __ASM__ +#endif + +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ +/* XXX The following ifdef magic fixes the problem but results in a warning */ +/* XXX when compiling assembly code. */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h new file mode 100644 index 0000000000..47041e7d5e --- /dev/null +++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h @@ -0,0 +1,1051 @@ +/** + * @file + * + * @brief SPARC64 CPU Department Source + * + * This include file contains information pertaining to the port of + * the executive to the SPARC64 processor. + */ + +/* + * + * + * COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR). + * + * This file is based on the SPARC cpu.h file. Modifications are made + * to support the SPARC64 processor. + * COPYRIGHT (c) 2010. Gedare Bloom. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/* + * Does the executive manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * The SPARC does not have a dedicated HW interrupt stack and one has + * been implemented in SW. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * SPARC Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * The SPARC does not have a dedicated HW interrupt stack. + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Do we allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the FLOATING_POINT task attribute is supported. + * If FALSE, then the FLOATING_POINT task attribute is ignored. + */ + +#if ( SPARC_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif +#define CPU_SOFTWARE_FP FALSE + +/* + * Are all tasks FLOATING_POINT tasks implicitly? + * + * If TRUE, then the FLOATING_POINT task attribute is assumed. + * If FALSE, then the FLOATING_POINT task attribute is followed. + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * The stack grows to lower addresses on the SPARC. + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +/* + * The following is the variable attribute used to force alignment + * of critical data structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The SPARC does not appear to have particularly strict alignment + * requirements. This value (16) was chosen to take advantages of caches. + * + * SPARC 64 requirements on floating point alignment is at least 8, + * and is 16 if quad-word fp instructions are available (e.g. LDQF). + */ + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 ) + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * + * The SPARC v9 has 16 interrupt levels in the PIL field of the PSR. + */ + +#define CPU_MODES_INTERRUPT_MASK 0x0000000F + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * This structure represents the organization of the minimum stack frame + * for the SPARC. More framing information is required in certain situaions + * such as when there are a large number of out parameters or when the callee + * must save floating point registers. + */ + +#ifndef ASM + +typedef struct { + uint64_t l0; + uint64_t l1; + uint64_t l2; + uint64_t l3; + uint64_t l4; + uint64_t l5; + uint64_t l6; + uint64_t l7; + uint64_t i0; + uint64_t i1; + uint64_t i2; + uint64_t i3; + uint64_t i4; + uint64_t i5; + uint64_t i6_fp; + uint64_t i7; + void *structure_return_address; + /* + * The following are for the callee to save the register arguments in + * should this be necessary. + */ + uint64_t saved_arg0; + uint64_t saved_arg1; + uint64_t saved_arg2; + uint64_t saved_arg3; + uint64_t saved_arg4; + uint64_t saved_arg5; + uint64_t pad0; +} SPARC64_Minimum_stack_frame; + +#endif /* !ASM */ + +#define CPU_STACK_FRAME_L0_OFFSET 0x00 +#define CPU_STACK_FRAME_L1_OFFSET 0x08 +#define CPU_STACK_FRAME_L2_OFFSET 0x10 +#define CPU_STACK_FRAME_L3_OFFSET 0x18 +#define CPU_STACK_FRAME_L4_OFFSET 0x20 +#define CPU_STACK_FRAME_L5_OFFSET 0x28 +#define CPU_STACK_FRAME_L6_OFFSET 0x30 +#define CPU_STACK_FRAME_L7_OFFSET 0x38 +#define CPU_STACK_FRAME_I0_OFFSET 0x40 +#define CPU_STACK_FRAME_I1_OFFSET 0x48 +#define CPU_STACK_FRAME_I2_OFFSET 0x50 +#define CPU_STACK_FRAME_I3_OFFSET 0x58 +#define CPU_STACK_FRAME_I4_OFFSET 0x60 +#define CPU_STACK_FRAME_I5_OFFSET 0x68 +#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70 +#define CPU_STACK_FRAME_I7_OFFSET 0x78 +#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 +#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 +#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 +#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 +#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 +#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 +#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 +#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8 + +#define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0 + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On the SPARC, we are relatively conservative in that we save most + * of the CPU state in the context area. The ET (enable trap) bit and + * the CWP (current window pointer) fields of the PSR are considered + * system wide resources and are not maintained on a per-thread basis. + */ + +#ifndef ASM + +typedef struct { + uint64_t g1; + uint64_t g2; + uint64_t g3; + uint64_t g4; + uint64_t g5; + uint64_t g6; + uint64_t g7; + + uint64_t l0; + uint64_t l1; + uint64_t l2; + uint64_t l3; + uint64_t l4; + uint64_t l5; + uint64_t l6; + uint64_t l7; + + uint64_t i0; + uint64_t i1; + uint64_t i2; + uint64_t i3; + uint64_t i4; + uint64_t i5; + uint64_t i6_fp; + uint64_t i7; + + uint64_t o0; + uint64_t o1; + uint64_t o2; + uint64_t o3; + uint64_t o4; + uint64_t o5; + uint64_t o6_sp; + uint64_t o7; + + uint32_t isr_dispatch_disable; + uint32_t pad; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->o6_sp + +#endif /* ASM */ + +/* + * Offsets of fields with Context_Control for assembly routines. + */ + +#define G1_OFFSET 0x00 +#define G2_OFFSET 0x08 +#define G3_OFFSET 0x10 +#define G4_OFFSET 0x18 +#define G5_OFFSET 0x20 +#define G6_OFFSET 0x28 +#define G7_OFFSET 0x30 + +#define L0_OFFSET 0x38 +#define L1_OFFSET 0x40 +#define L2_OFFSET 0x48 +#define L3_OFFSET 0x50 +#define L4_OFFSET 0x58 +#define L5_OFFSET 0x60 +#define L6_OFFSET 0x68 +#define L7_OFFSET 0x70 + +#define I0_OFFSET 0x78 +#define I1_OFFSET 0x80 +#define I2_OFFSET 0x88 +#define I3_OFFSET 0x90 +#define I4_OFFSET 0x98 +#define I5_OFFSET 0xA0 +#define I6_FP_OFFSET 0xA8 +#define I7_OFFSET 0xB0 + +#define O0_OFFSET 0xB8 +#define O1_OFFSET 0xC0 +#define O2_OFFSET 0xC8 +#define O3_OFFSET 0xD0 +#define O4_OFFSET 0xD8 +#define O5_OFFSET 0xE0 +#define O6_SP_OFFSET 0xE8 +#define O7_OFFSET 0xF0 + +#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 +#define ISR_PAD_OFFSET 0xFC + +/* + * The floating point context area. + */ + +#ifndef ASM + +typedef struct { + double f0; /* f0-f1 */ + double f2; /* f2-f3 */ + double f4; /* f4-f5 */ + double f6; /* f6-f7 */ + double f8; /* f8-f9 */ + double f10; /* f10-f11 */ + double f12; /* f12-f13 */ + double f14; /* f14-f15 */ + double f16; /* f16-f17 */ + double f18; /* f18-f19 */ + double f20; /* f20-f21 */ + double f22; /* f22-f23 */ + double f24; /* f24-f25 */ + double f26; /* f26-f27 */ + double f28; /* f28-f29 */ + double f30; /* f30-f31 */ + double f32; + double f34; + double f36; + double f38; + double f40; + double f42; + double f44; + double f46; + double f48; + double f50; + double f52; + double f54; + double f56; + double f58; + double f60; + double f62; + uint64_t fsr; +} Context_Control_fp; + +#endif /* !ASM */ + +/* + * Offsets of fields with Context_Control_fp for assembly routines. + */ + +#define FO_OFFSET 0x00 +#define F2_OFFSET 0x08 +#define F4_OFFSET 0x10 +#define F6_OFFSET 0x18 +#define F8_OFFSET 0x20 +#define F1O_OFFSET 0x28 +#define F12_OFFSET 0x30 +#define F14_OFFSET 0x38 +#define F16_OFFSET 0x40 +#define F18_OFFSET 0x48 +#define F2O_OFFSET 0x50 +#define F22_OFFSET 0x58 +#define F24_OFFSET 0x60 +#define F26_OFFSET 0x68 +#define F28_OFFSET 0x70 +#define F3O_OFFSET 0x78 +#define F32_OFFSET 0x80 +#define F34_OFFSET 0x88 +#define F36_OFFSET 0x90 +#define F38_OFFSET 0x98 +#define F4O_OFFSET 0xA0 +#define F42_OFFSET 0xA8 +#define F44_OFFSET 0xB0 +#define F46_OFFSET 0xB8 +#define F48_OFFSET 0xC0 +#define F5O_OFFSET 0xC8 +#define F52_OFFSET 0xD0 +#define F54_OFFSET 0xD8 +#define F56_OFFSET 0xE0 +#define F58_OFFSET 0xE8 +#define F6O_OFFSET 0xF0 +#define F62_OFFSET 0xF8 +#define FSR_OFFSET 0x100 + +#define CONTEXT_CONTROL_FP_SIZE 0x108 + +#ifndef ASM + +/* + * Context saved on stack for an interrupt. + * + * NOTE: The tstate, tpc, and tnpc are saved in this structure + * to allow resetting the TL while still being able to return + * from a trap later. The PIL is saved because + * if this is an external interrupt, we will mask lower + * priority interrupts until finishing. Even though the y register + * is deprecated, gcc still uses it. + */ + +typedef struct { + SPARC64_Minimum_stack_frame Stack_frame; + uint64_t tstate; + uint64_t tpc; + uint64_t tnpc; + uint64_t pil; + uint64_t y; + uint64_t g1; + uint64_t g2; + uint64_t g3; + uint64_t g4; + uint64_t g5; + uint64_t g6; + uint64_t g7; + uint64_t o0; + uint64_t o1; + uint64_t o2; + uint64_t o3; + uint64_t o4; + uint64_t o5; + uint64_t o6_sp; + uint64_t o7; + uint64_t tvec; +} CPU_Interrupt_frame; + +#endif /* ASM */ + +/* + * Offsets of fields with CPU_Interrupt_frame for assembly routines. + */ + +#define ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00 +#define ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08 +#define ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10 +#define ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18 +#define ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20 +#define ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28 +#define ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30 +#define ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38 +#define ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40 +#define ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48 +#define ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50 +#define ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58 +#define ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60 +#define ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68 +#define ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70 +#define ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78 +#define ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80 +#define ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88 +#define ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90 +#define ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98 +#define ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0 + +#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8 +#ifndef ASM +/* + * This variable is contains the initialize context for the FP unit. + * It is filled in by _CPU_Initialize and copied into the task's FP + * context area during _CPU_Context_Initialize. + */ + +extern Context_Control_fp _CPU_Null_fp_context; + +/* + * This flag is context switched with each thread. It indicates + * that THIS thread has an _ISR_Dispatch stack frame on its stack. + * By using this flag, we can avoid nesting more interrupt dispatching + * attempts on a previously interrupted thread's stack. + */ + +extern volatile uint32_t _CPU_ISR_Dispatch_disable; + +/* + * The following type defines an entry in the SPARC's trap table. + * + * NOTE: The instructions chosen are RTEMS dependent although one is + * obligated to use two of the four instructions to perform a + * long jump. The other instructions load one register with the + * trap type (a.k.a. vector) and another with the psr. + */ +/* For SPARC V9, we must use 6 of these instructions to perform a long + * jump, because the _handler value is now 64-bits. We also need to store + * temporary values in the global register set at this trap level. Because + * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3 + * to pass parameters to ISR_Handler. + * + * The instruction sequence is now more like: + * rdpr %tstate, %g4 + * setx _handler, %g2, %g3 + * jmp %g3+0 + * mov _vector, %g2 + */ +typedef struct { + uint32_t rdpr_tstate_g4; /* rdpr %tstate, %g4 */ + uint32_t sethi_of_hh_handler_to_g2; /* sethi %hh(_handler), %g2 */ + uint32_t or_g2_hm_handler_to_g2; /* or %l3, %hm(_handler), %g2 */ + uint32_t sllx_g2_by_32_to_g2; /* sllx %g2, 32, %g2 */ + uint32_t sethi_of_handler_to_g3; /* sethi %hi(_handler), %g3 */ + uint32_t or_g3_g2_to_g3; /* or %g3, %g2, %g3 */ + uint32_t jmp_to_low_of_handler_plus_g3; /* jmp %g3 + %lo(_handler) */ + uint32_t mov_vector_g2; /* mov _vector, %g2 */ +} CPU_Trap_table_entry; + +/* + * This is the set of opcodes for the instructions loaded into a trap + * table entry. The routine which installs a handler is responsible + * for filling in the fields for the _handler address and the _vector + * trap type. + * + * The constants following this structure are masks for the fields which + * must be filled in when the handler is installed. + */ + +extern const CPU_Trap_table_entry _CPU_Trap_slot_template; + +/* + * The size of the floating point context area. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#endif + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by the executive. + * + * On the SPARC, there are really only 256 vectors. However, the executive + * has no easy, fast, reliable way to determine which traps are synchronous + * and which are asynchronous. By default, synchronous traps return to the + * instruction which caused the interrupt. So if you install a software + * trap handler as an executive interrupt handler (which is desirable since + * RTEMS takes care of window and register issues), then the executive needs + * to know that the return address is to the trap rather than the instruction + * following the trap. + * + * So vectors 0 through 255 are treated as regular asynchronous traps which + * provide the "correct" return address. Vectors 256 through 512 are assumed + * by the executive to be synchronous and to require that the return address + * be fudged. + * + * If you use this mechanism to install a trap handler which must reexecute + * the instruction which caused the trap, then it should be installed as + * an asynchronous trap. This will avoid the executive changing the return + * address. + */ +/* On SPARC v9, there are 512 vectors. The same philosophy applies to + * vector installation and use, we just provide a larger table. + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 + +#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 +#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) +#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 ) + +#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512) + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * Should be large enough to run all tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * This appears to be a fairly generous number for the SPARC since + * represents a call depth of about 20 routines based on the minimum + * stack frame. + */ + +#define CPU_STACK_MINIMUM_SIZE (1024*8) + +#define CPU_SIZEOF_POINTER 8 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * On the SPARC, this is required for double word loads and stores. + * + * Note: quad-word loads/stores need alignment of 16, but currently supported + * architectures do not provide HW implemented quad-word operations. + */ + +#define CPU_ALIGNMENT 8 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * + * The alignment restrictions for the SPARC are not that strict but this + * should unsure that the stack is always sufficiently alignment that the + * window overflow, underflow, and flush routines can use double word loads + * and stores. + */ + +#define CPU_STACK_ALIGNMENT 16 + +#ifndef ASM + +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for a critical section. The previous + * level is returned in _level. + */ + + #define _CPU_ISR_Disable( _level ) \ + (_level) = sparc_disable_interrupts() + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of a critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _level ) \ + sparc_enable_interrupts( _level ) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _level ) \ + sparc_flash_interrupts( _level ) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & SPARC_PSTATE_IE_MASK ) != 0; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a straight fashion are undefined. + */ + +#define _CPU_ISR_Set_level( _newlevel ) \ + sparc_enable_interrupts( _newlevel) + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * NOTE: Implemented as a subroutine for the SPARC port. + */ + +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/* + * This macro is invoked from _Thread_Handler to do whatever CPU + * specific magic is required that must be done in the context of + * the thread when it starts. + * + * On the SPARC, this is setting the frame pointer so GDB is happy. + * Make GDB stop unwinding at _Thread_Handler, previous register window + * Frame pointer is 0 and calling address must be a function with starting + * with a SAVE instruction. If return address is leaf-function (no SAVE) + * GDB will not look at prev reg window fp. + * + * _Thread_Handler is known to start with SAVE. + */ + +#define _CPU_Context_Initialization_at_thread_begin() \ + do { \ + __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ + } while (0) + +/* + * This routine is responsible for somehow restarting the currently + * executing task. + * + * On the SPARC, this is is relatively painless but requires a small + * amount of wrapper code before using the regular restore code in + * of the context switch. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * This routine initializes the FP context area passed to it to. + * + * The SPARC allows us to use the simple initialization model + * in which an "initial" FP context was saved into _CPU_Null_fp_context + * at CPU initialization and it is simply copied into the destination + * context. + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } while (0) + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ + +#define _CPU_Fatal_halt( _source, _error ) \ + do { \ + uint32_t level; \ + \ + level = sparc_disable_interrupts(); \ + __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ + while (1); /* loop forever */ \ + } while (0) + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/* + * The SPARC port uses the generic C algorithm for bitfield scan if the + * CPU model does not have a scan instruction. + */ + +#if ( SPARC_HAS_BITSCAN == 0 ) +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#else +#error "scan instruction not currently supported by RTEMS!!" +#endif + +/* end of Bitfield handler macros */ + +/* Priority handler handler macros */ + +/* + * The SPARC port uses the generic C algorithm for bitfield scan if the + * CPU model does not have a scan instruction. + */ + +#if ( SPARC_HAS_BITSCAN == 1 ) +#error "scan instruction not currently supported by RTEMS!!" +#endif + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs new_handler to be directly called from the trap + * table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint64_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) + +/* + * _CPU_Thread_Idle_body + * + * Some SPARC implementations have low power, sleep, or idle modes. This + * tries to take advantage of those models. + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/* + * CPU_swap_u32 + * + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if you come across a better + * way for the SPARC PLEASE use it. The most common way to swap a 32-bit + * entity as shown below is not any more efficient on the SPARC. + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * It is not obvious how the SPARC can do significantly better than the + * generic code. gcc 2.7.0 only generates about 12 instructions for the + * following code at optimization level four (i.e. -O4). + */ + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h b/cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h new file mode 100644 index 0000000000..d20c2ff509 --- /dev/null +++ b/cpukit/score/cpu/sparc64/include/rtems/score/sparc64.h @@ -0,0 +1,342 @@ +/** + * @file + * + * @brief Information Required to Build RTEMS for a Particular Member + * of the SPARC Family + * + * This include file contains information pertaining to the SPARC + * processor family. + */ + +/* + * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). + * + * This file is based on the SPARC sparc.h file. Modifications are made + * to support the SPARC64 processor. + * COPYRIGHT (c) 2010. Gedare Bloom. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SPARC_H +#define _RTEMS_SCORE_SPARC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "sparc" family. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + * + * Currently recognized feature flags: + * + * + SPARC_HAS_FPU + * 0 - no HW FPU + * 1 - has HW FPU (assumed to be compatible w/90C602) + * + * + SPARC_HAS_BITSCAN + * 0 - does not have scan instructions + * 1 - has scan instruction (not currently implemented) + * + * + SPARC_NUMBER_OF_REGISTER_WINDOWS + * 8 is the most common number supported by SPARC implementations. + * SPARC_PSR_CWP_MASK is derived from this value. + */ + +/* + * Some higher end SPARCs have a bitscan instructions. It would + * be nice to take advantage of them. Right now, there is no + * port to a CPU model with this feature and no (untested) code + * that is based on this feature flag. + */ + +#define SPARC_HAS_BITSCAN 0 + +/* + * This should be OK until a port to a higher end SPARC processor + * is made that has more than 8 register windows. If this cannot + * be determined based on multilib settings (v7/v8/v9), then the + * cpu_asm.S code that depends on this will have to move to libcpu. + * + * SPARC v9 supports from 3 to 32 register windows. + * N_REG_WINDOWS = 8 on UltraSPARC T1 (impl. dep. #2-V8). + */ + +#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 + +/* + * This should be determined based on some soft float derived + * cpp predefine but gcc does not currently give us that information. + */ + + +#if defined(_SOFT_FLOAT) +#define SPARC_HAS_FPU 0 +#else +#define SPARC_HAS_FPU 1 +#endif + +#if SPARC_HAS_FPU +#define CPU_MODEL_NAME "w/FPU" +#else +#define CPU_MODEL_NAME "w/soft-float" +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "SPARC" + +/* + * Miscellaneous constants + */ + +/* + * The PSR is deprecated and deleted. + * + * The following registers represent fields of the PSR: + * PIL - Processor Interrupt Level register + * CWP - Current Window Pointer register + * VER - Version register + * CCR - Condition Codes Register + * PSTATE - Processor State register + */ + +/* + * PSTATE masks and starting bit positions + * + * NOTE: Reserved bits are ignored. + */ + +#define SPARC_PSTATE_AG_MASK 0x00000001 /* bit 0 */ +#define SPARC_PSTATE_IE_MASK 0x00000002 /* bit 1 */ +#define SPARC_PSTATE_PRIV_MASK 0x00000004 /* bit 2 */ +#define SPARC_PSTATE_AM_MASK 0x00000008 /* bit 3 */ +#define SPARC_PSTATE_PEF_MASK 0x00000010 /* bit 4 */ +#define SPARC_PSTATE_MM_MASK 0x00000040 /* bit 6 */ +#define SPARC_PSTATE_TLE_MASK 0x00000100 /* bit 8 */ +#define SPARC_PSTATE_CLE_MASK 0x00000200 /* bit 9 */ + +#define SPARC_PSTATE_AG_BIT_POSITION 0 /* bit 0 */ +#define SPARC_PSTATE_IE_BIT_POSITION 1 /* bit 1 */ +#define SPARC_PSTATE_PRIV_BIT_POSITION 2 /* bit 2 */ +#define SPARC_PSTATE_AM_BIT_POSITION 3 /* bit 3 */ +#define SPARC_PSTATE_PEF_BIT_POSITION 4 /* bit 4 */ +#define SPARC_PSTATE_MM_BIT_POSITION 6 /* bit 6 */ +#define SPARC_PSTATE_TLE_BIT_POSITION 8 /* bit 8 */ +#define SPARC_PSTATE_CLE_BIT_POSITION 9 /* bit 9 */ + +#define SPARC_FPRS_FEF_MASK 0x0100 /* bit 2 */ +#define SPARC_FPRS_FEF_BIT_POSITION 2 /* bit 2 */ + +#define SPARC_TSTATE_IE_MASK 0x00000200 /* bit 9 */ + +#define SPARC_SOFTINT_TM_MASK 0x00000001 /* bit 0 */ +#define SPARC_SOFTINT_SM_MASK 0x00010000 /* bit 16 */ +#define SPARC_SOFTINT_TM_BIT_POSITION 1 /* bit 0 */ +#define SPARC_SOFTINT_SM_BIT_POSITION 17 /* bit 16 */ + +#define STACK_BIAS (2047) + +#ifdef ASM + +/* + * To enable the FPU we need to set both PSTATE.pef and FPRS.fef + */ + +#define sparc64_enable_FPU(rtmp1) \ + rdpr %pstate, rtmp1; \ + or rtmp1, SPARC_PSTATE_PEF_MASK, rtmp1; \ + wrpr %g0, rtmp1, %pstate; \ + rd %fprs, rtmp1; \ + or rtmp1, SPARC_FPRS_FEF_MASK, rtmp1; \ + wr %g0, rtmp1, %fprs + + +#endif + +#ifndef ASM + +/* + * Standard nop + */ + +#define nop() \ + do { \ + __asm__ volatile ( "nop" ); \ + } while ( 0 ) + +/* + * Get and set the pstate + */ + +#define sparc64_get_pstate( _pstate ) \ + do { \ + (_pstate) = 0; \ + __asm__ volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \ + } while ( 0 ) + +#define sparc64_set_pstate( _pstate ) \ + do { \ + __asm__ volatile ( \ + "wrpr %%g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \ + } while ( 0 ) + +/* + * Get and set the PIL + */ + +#define sparc64_get_pil( _pil ) \ + do { \ + (_pil) = 0; \ + __asm__ volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \ + } while ( 0 ) + +#define sparc64_set_pil( _pil ) \ + do { \ + __asm__ volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \ + } while ( 0 ) + + +/* + * Get and set the TBA + */ + +#define sparc64_get_tba( _tba ) \ + do { \ + (_tba) = 0; /* to avoid unitialized warnings */ \ + __asm__ volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \ + } while ( 0 ) + +#define sparc64_set_tba( _tba ) \ + do { \ + __asm__ volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \ + } while ( 0 ) + +/* + * Get and set the TL (trap level) + */ + +#define sparc64_get_tl( _tl ) \ + do { \ + (_tl) = 0; /* to avoid unitialized warnings */ \ + __asm__ volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \ + } while ( 0 ) + +#define sparc64_set_tl( _tl ) \ + do { \ + __asm__ volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \ + } while ( 0 ) + + +/* + * read the stick register + * + * Note: + * stick asr=24, mnemonic=stick + * Note: stick does not appear to be a valid ASR for US3, although it is + * implemented in US3i. + */ +#define sparc64_read_stick( _stick ) \ + do { \ + (_stick) = 0; \ + __asm__ volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \ + } while ( 0 ) + +/* + * write the stick_cmpr register + * + * Note: + * stick_cmpr asr=25, mnemonic=stick_cmpr + * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is + * implemented in US3i. + */ +#define sparc64_write_stick_cmpr( _stick_cmpr ) \ + do { \ + __asm__ volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \ + : "0" (_stick_cmpr) ); \ + } while ( 0 ) + +/* + * read the Tick register + */ +#define sparc64_read_tick( _tick ) \ + do { \ + (_tick) = 0; \ + __asm__ volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \ + } while ( 0 ) + +/* + * write the tick_cmpr register + */ +#define sparc64_write_tick_cmpr( _tick_cmpr ) \ + do { \ + __asm__ volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \ + : "0" (_tick_cmpr) ); \ + } while ( 0 ) + +/* + * Clear the softint register. + * + * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint + */ +#define sparc64_clear_interrupt_bits( _bit_mask ) \ + do { \ + __asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \ + : "0" (_bit_mask)); \ + } while ( 0 ) + +/************* DEPRECATED ****************/ +/* Note: Although the y register is deprecated, gcc still uses it */ +/* + * Get and set the Y + */ + +#define sparc_get_y( _y ) \ + do { \ + __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ + } while ( 0 ) + +#define sparc_set_y( _y ) \ + do { \ + __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ + } while ( 0 ) + +/************* /DEPRECATED ****************/ + +/* + * Manipulate the interrupt level in the pstate + */ + +uint32_t sparc_disable_interrupts(void); +void sparc_enable_interrupts(uint32_t); + +#define sparc_flash_interrupts( _level ) \ + do { \ + uint32_t _ignored; \ + \ + sparc_enable_interrupts( (_level) ); \ + _ignored = sparc_disable_interrupts(); \ + (void) _ignored; \ + } while ( 0 ) + +#define sparc64_get_interrupt_level( _level ) \ + do { \ + _level = 0; \ + sparc64_get_pil( _level ); \ + } while ( 0 ) + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_SPARC_H */ diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/types.h b/cpukit/score/cpu/sparc64/include/rtems/score/types.h new file mode 100644 index 0000000000..faf50b7a55 --- /dev/null +++ b/cpukit/score/cpu/sparc64/include/rtems/score/types.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @brief SPARC64 CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * SPARC-v9 processor family. + */ + +/* + * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void sparc_isr; +typedef void ( *sparc_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/sparc64/preinstall.am b/cpukit/score/cpu/sparc64/preinstall.am deleted file mode 100644 index 8565c8a672..0000000000 --- a/cpukit/score/cpu/sparc64/preinstall.am +++ /dev/null @@ -1,49 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/sparc64.h: rtems/score/sparc64.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sparc64.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/sparc64.h - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/sparc64/rtems/asm.h b/cpukit/score/cpu/sparc64/rtems/asm.h deleted file mode 100644 index f4448b03a5..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/asm.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#ifndef __ASM__ -#define __ASM__ -#endif - -#include -#include - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/rtems/score/cpu.h deleted file mode 100644 index 47041e7d5e..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h +++ /dev/null @@ -1,1051 +0,0 @@ -/** - * @file - * - * @brief SPARC64 CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC64 processor. - */ - -/* - * - * - * COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC cpu.h file. Modifications are made - * to support the SPARC64 processor. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SPARC Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the FLOATING_POINT task attribute is supported. - * If FALSE, then the FLOATING_POINT task attribute is ignored. - */ - -#if ( SPARC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks FLOATING_POINT tasks implicitly? - * - * If TRUE, then the FLOATING_POINT task attribute is assumed. - * If FALSE, then the FLOATING_POINT task attribute is followed. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -/* - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value (16) was chosen to take advantages of caches. - * - * SPARC 64 requirements on floating point alignment is at least 8, - * and is 16 if quad-word fp instructions are available (e.g. LDQF). - */ - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 ) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC v9 has 16 interrupt levels in the PIL field of the PSR. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ - -#ifndef ASM - -typedef struct { - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - void *structure_return_address; - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - uint64_t saved_arg0; - uint64_t saved_arg1; - uint64_t saved_arg2; - uint64_t saved_arg3; - uint64_t saved_arg4; - uint64_t saved_arg5; - uint64_t pad0; -} SPARC64_Minimum_stack_frame; - -#endif /* !ASM */ - -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -#define CPU_STACK_FRAME_L1_OFFSET 0x08 -#define CPU_STACK_FRAME_L2_OFFSET 0x10 -#define CPU_STACK_FRAME_L3_OFFSET 0x18 -#define CPU_STACK_FRAME_L4_OFFSET 0x20 -#define CPU_STACK_FRAME_L5_OFFSET 0x28 -#define CPU_STACK_FRAME_L6_OFFSET 0x30 -#define CPU_STACK_FRAME_L7_OFFSET 0x38 -#define CPU_STACK_FRAME_I0_OFFSET 0x40 -#define CPU_STACK_FRAME_I1_OFFSET 0x48 -#define CPU_STACK_FRAME_I2_OFFSET 0x50 -#define CPU_STACK_FRAME_I3_OFFSET 0x58 -#define CPU_STACK_FRAME_I4_OFFSET 0x60 -#define CPU_STACK_FRAME_I5_OFFSET 0x68 -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70 -#define CPU_STACK_FRAME_I7_OFFSET 0x78 -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 -#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8 - -#define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0 - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ - -#ifndef ASM - -typedef struct { - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - - uint32_t isr_dispatch_disable; - uint32_t pad; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -#define G1_OFFSET 0x00 -#define G2_OFFSET 0x08 -#define G3_OFFSET 0x10 -#define G4_OFFSET 0x18 -#define G5_OFFSET 0x20 -#define G6_OFFSET 0x28 -#define G7_OFFSET 0x30 - -#define L0_OFFSET 0x38 -#define L1_OFFSET 0x40 -#define L2_OFFSET 0x48 -#define L3_OFFSET 0x50 -#define L4_OFFSET 0x58 -#define L5_OFFSET 0x60 -#define L6_OFFSET 0x68 -#define L7_OFFSET 0x70 - -#define I0_OFFSET 0x78 -#define I1_OFFSET 0x80 -#define I2_OFFSET 0x88 -#define I3_OFFSET 0x90 -#define I4_OFFSET 0x98 -#define I5_OFFSET 0xA0 -#define I6_FP_OFFSET 0xA8 -#define I7_OFFSET 0xB0 - -#define O0_OFFSET 0xB8 -#define O1_OFFSET 0xC0 -#define O2_OFFSET 0xC8 -#define O3_OFFSET 0xD0 -#define O4_OFFSET 0xD8 -#define O5_OFFSET 0xE0 -#define O6_SP_OFFSET 0xE8 -#define O7_OFFSET 0xF0 - -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 -#define ISR_PAD_OFFSET 0xFC - -/* - * The floating point context area. - */ - -#ifndef ASM - -typedef struct { - double f0; /* f0-f1 */ - double f2; /* f2-f3 */ - double f4; /* f4-f5 */ - double f6; /* f6-f7 */ - double f8; /* f8-f9 */ - double f10; /* f10-f11 */ - double f12; /* f12-f13 */ - double f14; /* f14-f15 */ - double f16; /* f16-f17 */ - double f18; /* f18-f19 */ - double f20; /* f20-f21 */ - double f22; /* f22-f23 */ - double f24; /* f24-f25 */ - double f26; /* f26-f27 */ - double f28; /* f28-f29 */ - double f30; /* f30-f31 */ - double f32; - double f34; - double f36; - double f38; - double f40; - double f42; - double f44; - double f46; - double f48; - double f50; - double f52; - double f54; - double f56; - double f58; - double f60; - double f62; - uint64_t fsr; -} Context_Control_fp; - -#endif /* !ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -#define FO_OFFSET 0x00 -#define F2_OFFSET 0x08 -#define F4_OFFSET 0x10 -#define F6_OFFSET 0x18 -#define F8_OFFSET 0x20 -#define F1O_OFFSET 0x28 -#define F12_OFFSET 0x30 -#define F14_OFFSET 0x38 -#define F16_OFFSET 0x40 -#define F18_OFFSET 0x48 -#define F2O_OFFSET 0x50 -#define F22_OFFSET 0x58 -#define F24_OFFSET 0x60 -#define F26_OFFSET 0x68 -#define F28_OFFSET 0x70 -#define F3O_OFFSET 0x78 -#define F32_OFFSET 0x80 -#define F34_OFFSET 0x88 -#define F36_OFFSET 0x90 -#define F38_OFFSET 0x98 -#define F4O_OFFSET 0xA0 -#define F42_OFFSET 0xA8 -#define F44_OFFSET 0xB0 -#define F46_OFFSET 0xB8 -#define F48_OFFSET 0xC0 -#define F5O_OFFSET 0xC8 -#define F52_OFFSET 0xD0 -#define F54_OFFSET 0xD8 -#define F56_OFFSET 0xE0 -#define F58_OFFSET 0xE8 -#define F6O_OFFSET 0xF0 -#define F62_OFFSET 0xF8 -#define FSR_OFFSET 0x100 - -#define CONTEXT_CONTROL_FP_SIZE 0x108 - -#ifndef ASM - -/* - * Context saved on stack for an interrupt. - * - * NOTE: The tstate, tpc, and tnpc are saved in this structure - * to allow resetting the TL while still being able to return - * from a trap later. The PIL is saved because - * if this is an external interrupt, we will mask lower - * priority interrupts until finishing. Even though the y register - * is deprecated, gcc still uses it. - */ - -typedef struct { - SPARC64_Minimum_stack_frame Stack_frame; - uint64_t tstate; - uint64_t tpc; - uint64_t tnpc; - uint64_t pil; - uint64_t y; - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - uint64_t tvec; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -#define ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00 -#define ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08 -#define ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10 -#define ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18 -#define ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20 -#define ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28 -#define ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30 -#define ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38 -#define ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40 -#define ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48 -#define ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50 -#define ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58 -#define ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60 -#define ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68 -#define ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70 -#define ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78 -#define ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80 -#define ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88 -#define ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90 -#define ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98 -#define ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0 - -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8 -#ifndef ASM -/* - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ - -extern Context_Control_fp _CPU_Null_fp_context; - -/* - * This flag is context switched with each thread. It indicates - * that THIS thread has an _ISR_Dispatch stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ - -extern volatile uint32_t _CPU_ISR_Dispatch_disable; - -/* - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -/* For SPARC V9, we must use 6 of these instructions to perform a long - * jump, because the _handler value is now 64-bits. We also need to store - * temporary values in the global register set at this trap level. Because - * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3 - * to pass parameters to ISR_Handler. - * - * The instruction sequence is now more like: - * rdpr %tstate, %g4 - * setx _handler, %g2, %g3 - * jmp %g3+0 - * mov _vector, %g2 - */ -typedef struct { - uint32_t rdpr_tstate_g4; /* rdpr %tstate, %g4 */ - uint32_t sethi_of_hh_handler_to_g2; /* sethi %hh(_handler), %g2 */ - uint32_t or_g2_hm_handler_to_g2; /* or %l3, %hm(_handler), %g2 */ - uint32_t sllx_g2_by_32_to_g2; /* sllx %g2, 32, %g2 */ - uint32_t sethi_of_handler_to_g3; /* sethi %hi(_handler), %g3 */ - uint32_t or_g3_g2_to_g3; /* or %g3, %g2, %g3 */ - uint32_t jmp_to_low_of_handler_plus_g3; /* jmp %g3 + %lo(_handler) */ - uint32_t mov_vector_g2; /* mov _vector, %g2 */ -} CPU_Trap_table_entry; - -/* - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/* - * The size of the floating point context area. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -/* On SPARC v9, there are 512 vectors. The same philosophy applies to - * vector installation and use, we just provide a larger table. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 - -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 ) - -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 8 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - * - * Note: quad-word loads/stores need alignment of 16, but currently supported - * architectures do not provide HW implemented quad-word operations. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ - -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ - - #define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & SPARC_PSTATE_IE_MASK ) != 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ - -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ - -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - uint32_t level; \ - \ - level = sparc_disable_interrupts(); \ - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 0 ) -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#else -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 1 ) -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs new_handler to be directly called from the trap - * table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint64_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -/* - * _CPU_Thread_Idle_body - * - * Some SPARC implementations have low power, sleep, or idle modes. This - * tries to take advantage of those models. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * CPU_swap_u32 - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpuatomic.h b/cpukit/score/cpu/sparc64/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sparc64/rtems/score/sparc64.h b/cpukit/score/cpu/sparc64/rtems/score/sparc64.h deleted file mode 100644 index d20c2ff509..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/sparc64.h +++ /dev/null @@ -1,342 +0,0 @@ -/** - * @file - * - * @brief Information Required to Build RTEMS for a Particular Member - * of the SPARC Family - * - * This include file contains information pertaining to the SPARC - * processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC sparc.h file. Modifications are made - * to support the SPARC64 processor. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SPARC_H -#define _RTEMS_SCORE_SPARC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "sparc" family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized feature flags: - * - * + SPARC_HAS_FPU - * 0 - no HW FPU - * 1 - has HW FPU (assumed to be compatible w/90C602) - * - * + SPARC_HAS_BITSCAN - * 0 - does not have scan instructions - * 1 - has scan instruction (not currently implemented) - * - * + SPARC_NUMBER_OF_REGISTER_WINDOWS - * 8 is the most common number supported by SPARC implementations. - * SPARC_PSR_CWP_MASK is derived from this value. - */ - -/* - * Some higher end SPARCs have a bitscan instructions. It would - * be nice to take advantage of them. Right now, there is no - * port to a CPU model with this feature and no (untested) code - * that is based on this feature flag. - */ - -#define SPARC_HAS_BITSCAN 0 - -/* - * This should be OK until a port to a higher end SPARC processor - * is made that has more than 8 register windows. If this cannot - * be determined based on multilib settings (v7/v8/v9), then the - * cpu_asm.S code that depends on this will have to move to libcpu. - * - * SPARC v9 supports from 3 to 32 register windows. - * N_REG_WINDOWS = 8 on UltraSPARC T1 (impl. dep. #2-V8). - */ - -#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 - -/* - * This should be determined based on some soft float derived - * cpp predefine but gcc does not currently give us that information. - */ - - -#if defined(_SOFT_FLOAT) -#define SPARC_HAS_FPU 0 -#else -#define SPARC_HAS_FPU 1 -#endif - -#if SPARC_HAS_FPU -#define CPU_MODEL_NAME "w/FPU" -#else -#define CPU_MODEL_NAME "w/soft-float" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "SPARC" - -/* - * Miscellaneous constants - */ - -/* - * The PSR is deprecated and deleted. - * - * The following registers represent fields of the PSR: - * PIL - Processor Interrupt Level register - * CWP - Current Window Pointer register - * VER - Version register - * CCR - Condition Codes Register - * PSTATE - Processor State register - */ - -/* - * PSTATE masks and starting bit positions - * - * NOTE: Reserved bits are ignored. - */ - -#define SPARC_PSTATE_AG_MASK 0x00000001 /* bit 0 */ -#define SPARC_PSTATE_IE_MASK 0x00000002 /* bit 1 */ -#define SPARC_PSTATE_PRIV_MASK 0x00000004 /* bit 2 */ -#define SPARC_PSTATE_AM_MASK 0x00000008 /* bit 3 */ -#define SPARC_PSTATE_PEF_MASK 0x00000010 /* bit 4 */ -#define SPARC_PSTATE_MM_MASK 0x00000040 /* bit 6 */ -#define SPARC_PSTATE_TLE_MASK 0x00000100 /* bit 8 */ -#define SPARC_PSTATE_CLE_MASK 0x00000200 /* bit 9 */ - -#define SPARC_PSTATE_AG_BIT_POSITION 0 /* bit 0 */ -#define SPARC_PSTATE_IE_BIT_POSITION 1 /* bit 1 */ -#define SPARC_PSTATE_PRIV_BIT_POSITION 2 /* bit 2 */ -#define SPARC_PSTATE_AM_BIT_POSITION 3 /* bit 3 */ -#define SPARC_PSTATE_PEF_BIT_POSITION 4 /* bit 4 */ -#define SPARC_PSTATE_MM_BIT_POSITION 6 /* bit 6 */ -#define SPARC_PSTATE_TLE_BIT_POSITION 8 /* bit 8 */ -#define SPARC_PSTATE_CLE_BIT_POSITION 9 /* bit 9 */ - -#define SPARC_FPRS_FEF_MASK 0x0100 /* bit 2 */ -#define SPARC_FPRS_FEF_BIT_POSITION 2 /* bit 2 */ - -#define SPARC_TSTATE_IE_MASK 0x00000200 /* bit 9 */ - -#define SPARC_SOFTINT_TM_MASK 0x00000001 /* bit 0 */ -#define SPARC_SOFTINT_SM_MASK 0x00010000 /* bit 16 */ -#define SPARC_SOFTINT_TM_BIT_POSITION 1 /* bit 0 */ -#define SPARC_SOFTINT_SM_BIT_POSITION 17 /* bit 16 */ - -#define STACK_BIAS (2047) - -#ifdef ASM - -/* - * To enable the FPU we need to set both PSTATE.pef and FPRS.fef - */ - -#define sparc64_enable_FPU(rtmp1) \ - rdpr %pstate, rtmp1; \ - or rtmp1, SPARC_PSTATE_PEF_MASK, rtmp1; \ - wrpr %g0, rtmp1, %pstate; \ - rd %fprs, rtmp1; \ - or rtmp1, SPARC_FPRS_FEF_MASK, rtmp1; \ - wr %g0, rtmp1, %fprs - - -#endif - -#ifndef ASM - -/* - * Standard nop - */ - -#define nop() \ - do { \ - __asm__ volatile ( "nop" ); \ - } while ( 0 ) - -/* - * Get and set the pstate - */ - -#define sparc64_get_pstate( _pstate ) \ - do { \ - (_pstate) = 0; \ - __asm__ volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \ - } while ( 0 ) - -#define sparc64_set_pstate( _pstate ) \ - do { \ - __asm__ volatile ( \ - "wrpr %%g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \ - } while ( 0 ) - -/* - * Get and set the PIL - */ - -#define sparc64_get_pil( _pil ) \ - do { \ - (_pil) = 0; \ - __asm__ volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \ - } while ( 0 ) - -#define sparc64_set_pil( _pil ) \ - do { \ - __asm__ volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \ - } while ( 0 ) - - -/* - * Get and set the TBA - */ - -#define sparc64_get_tba( _tba ) \ - do { \ - (_tba) = 0; /* to avoid unitialized warnings */ \ - __asm__ volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \ - } while ( 0 ) - -#define sparc64_set_tba( _tba ) \ - do { \ - __asm__ volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \ - } while ( 0 ) - -/* - * Get and set the TL (trap level) - */ - -#define sparc64_get_tl( _tl ) \ - do { \ - (_tl) = 0; /* to avoid unitialized warnings */ \ - __asm__ volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \ - } while ( 0 ) - -#define sparc64_set_tl( _tl ) \ - do { \ - __asm__ volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \ - } while ( 0 ) - - -/* - * read the stick register - * - * Note: - * stick asr=24, mnemonic=stick - * Note: stick does not appear to be a valid ASR for US3, although it is - * implemented in US3i. - */ -#define sparc64_read_stick( _stick ) \ - do { \ - (_stick) = 0; \ - __asm__ volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \ - } while ( 0 ) - -/* - * write the stick_cmpr register - * - * Note: - * stick_cmpr asr=25, mnemonic=stick_cmpr - * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is - * implemented in US3i. - */ -#define sparc64_write_stick_cmpr( _stick_cmpr ) \ - do { \ - __asm__ volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \ - : "0" (_stick_cmpr) ); \ - } while ( 0 ) - -/* - * read the Tick register - */ -#define sparc64_read_tick( _tick ) \ - do { \ - (_tick) = 0; \ - __asm__ volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \ - } while ( 0 ) - -/* - * write the tick_cmpr register - */ -#define sparc64_write_tick_cmpr( _tick_cmpr ) \ - do { \ - __asm__ volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \ - : "0" (_tick_cmpr) ); \ - } while ( 0 ) - -/* - * Clear the softint register. - * - * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint - */ -#define sparc64_clear_interrupt_bits( _bit_mask ) \ - do { \ - __asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \ - : "0" (_bit_mask)); \ - } while ( 0 ) - -/************* DEPRECATED ****************/ -/* Note: Although the y register is deprecated, gcc still uses it */ -/* - * Get and set the Y - */ - -#define sparc_get_y( _y ) \ - do { \ - __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -#define sparc_set_y( _y ) \ - do { \ - __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -/************* /DEPRECATED ****************/ - -/* - * Manipulate the interrupt level in the pstate - */ - -uint32_t sparc_disable_interrupts(void); -void sparc_enable_interrupts(uint32_t); - -#define sparc_flash_interrupts( _level ) \ - do { \ - uint32_t _ignored; \ - \ - sparc_enable_interrupts( (_level) ); \ - _ignored = sparc_disable_interrupts(); \ - (void) _ignored; \ - } while ( 0 ) - -#define sparc64_get_interrupt_level( _level ) \ - do { \ - _level = 0; \ - sparc64_get_pil( _level ); \ - } while ( 0 ) - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_SPARC_H */ diff --git a/cpukit/score/cpu/sparc64/rtems/score/types.h b/cpukit/score/cpu/sparc64/rtems/score/types.h deleted file mode 100644 index faf50b7a55..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/types.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @brief SPARC64 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * SPARC-v9 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void sparc_isr; -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/v850/Makefile.am b/cpukit/score/cpu/v850/Makefile.am index 7200f2a097..15867801a5 100644 --- a/cpukit/score/cpu/v850/Makefile.am +++ b/cpukit/score/cpu/v850/Makefile.am @@ -1,15 +1,5 @@ include $(top_srcdir)/automake/compile.am -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = rtems/asm.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = rtems/score/cpu.h -include_rtems_score_HEADERS += rtems/score/cpuimpl.h -include_rtems_score_HEADERS += rtems/score/v850.h -include_rtems_score_HEADERS += rtems/score/cpu_asm.h rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpuatomic.h - noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = cpu.c libscorecpu_a_SOURCES += cpu_asm.S @@ -17,5 +7,5 @@ libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c libscorecpu_a_SOURCES += v850-exception-frame-print.c libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/v850/headers.am b/cpukit/score/cpu/v850/headers.am new file mode 100644 index 0000000000..ea94e64aa2 --- /dev/null +++ b/cpukit/score/cpu/v850/headers.am @@ -0,0 +1,18 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/types.h +include_rtems_score_HEADERS += include/rtems/score/v850.h diff --git a/cpukit/score/cpu/v850/include/machine/elf_machdep.h b/cpukit/score/cpu/v850/include/machine/elf_machdep.h new file mode 100644 index 0000000000..b76d1491d6 --- /dev/null +++ b/cpukit/score/cpu/v850/include/machine/elf_machdep.h @@ -0,0 +1,74 @@ +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB + +#define ELF32_MACHDEP_ID_CASES \ + case EM_V850: \ + break; + +#define ELF32_MACHDEP_ID EM_V850 + + + +#define EF_V850_ARCH 0xf0000000 +#define E_V850_ARCH 0x00000000 +#define E_V850E_ARCH 0x10000000 +#define E_V850E1_ARCH 0x20000000 +#define E_V850E2_ARCH 0x30000000 +#define E_V850E2V3_ARCH 0x40000000 + +#define ARCH_ELFSIZE 32 + + +#define R_V850_NONE 0 +#define R_V850_9_PCREL 1 +#define R_V850_22_PCREL 2 +#define R_V850_HI16_S 3 +#define R_V850_HI16 4 +#define R_V850_LO16 5 +#define R_V850_ABS32 6 +#define R_V850_16 7 +#define R_V850_8 8 +#define R_V850_SDA_16_16_OFFSET 9 +#define R_V850_SDA_15_16_OFFSET 10 +#define R_V850_ZDA_16_16_OFFSET 11 +#define R_V850_ZDA_15_16_OFFSET 12 +#define R_V850_TDA_6_8_OFFSET 13 +#define R_V850_TDA_7_8_OFFSET 14 +#define R_V850_TDA_7_7_OFFSET 15 +#define R_V850_TDA_16_16_OFFSET 16 +#define R_V850_TDA_4_5_OFFSET 17 +#define R_V850_TDA_4_4_OFFSET 18 +#define R_V850_SDA_16_16_SPLIT_OFFSET 19 +#define R_V850_ZDA_16_16_SPLIT_OFFSET 20 +#define R_V850_CALLT_6_7_OFFSET 21 +#define R_V850_CALLT_16_16_OFFSET 22 +#define R_V850_GNU_VTINHERIT 23 +#define R_V850_GNU_VTENTRY 24 +#define R_V850_LONGCALL 25 +#define R_V850_LONGJUMP 26 +#define R_V850_ALIGN 27 +#define R_V850_REL32 28 +#define R_V850_LO16_SPLIT_OFFSET 29 +#define R_V850_16_PCREL 30 +#define R_V850_17_PCREL 31 +#define R_V850_23 32 +#define R_V850_32_PCREL 33 +#define R_V850_32_ABS 34 +#define R_V850_16_SPLIT_OFFSET 35 +#define R_V850_16_S1 36 +#define R_V850_LO16_S1 37 +#define R_V850_CALLT_15_16_OFFSET 38 +#define R_V850_32_GOTPCREL 39 +#define R_V850_16_GOT 40 +#define R_V850_32_GOT 41 +#define R_V850_22_PLT 42 +#define R_V850_32_PLT 43 +#define R_V850_COPY 44 +#define R_V850_GLOB_DAT 45 +#define R_V850_JMP_SLOT 46 +#define R_V850_RELATIVE 47 +#define R_V850_16_GOTOFF 48 +#define R_V850_32_GOTOFF 49 +#define R_V850_CODE 50 +#define R_V850_DATA 51 + +#define R_TYPE(name) __CONCAT(R_V850_,name) diff --git a/cpukit/score/cpu/v850/include/rtems/asm.h b/cpukit/score/cpu/v850/include/rtems/asm.h new file mode 100644 index 0000000000..265e4967ae --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/asm.h @@ -0,0 +1,127 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * @note The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-2012. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include +#include + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all register names. + */ +#define __REGISTER_PREFIX__ +#endif + +#include + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** This macro is used to denote the beginning of a data declaration section. */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** + * This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpu.h b/cpukit/score/cpu/v850/include/rtems/score/cpu.h new file mode 100644 index 0000000000..d3cdf0514a --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/score/cpu.h @@ -0,0 +1,951 @@ +/** + * @file + * + * @brief V850 CPU Department Source + * + * This include file contains information pertaining to the v850 + * processor. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* conditional compilation parameters */ + +/** + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * The v850 does not have support for a hardware interrupt stack. + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/** + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * Port Specific Information: + * + * This port uses the Progammable Interrupt Controller interrupt model. + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * The v850 does not have support for a hardware interrupt stack. + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/** + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * @def CPU_HARDWARE_FP + * + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "V850_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? + * + * This feature conditional is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Port Specific Information: + * + * Some v850 models do have IEEE hardware floating point support but + * they do not have any special registers to save or bit(s) which + * determine if the FPU is enabled. In short, there appears to be nothing + * related to the floating point operations which impact the RTEMS + * thread context switch. Thus from an RTEMS perspective, there is really + * no FPU to manage. + */ +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPUs in which this option has been used are the + * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and + * gcc both implicitly used the floating point registers to perform + * integer multiplies. Similarly, the PowerPC port of gcc has been + * seen to allocate floating point local variables and touch the FPU + * even when the flow through a subroutine (like vfprintf()) might + * not use floating point formats. + * + * If a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Port Specific Information: + * + * This should be false until it has been demonstrated that gcc for the + * v850 generates FPU code when it is unexpected. But even this would + * not matter since there are no FP specific registers or bits which + * would be corrupted if an FP operation occurred in an integer only + * thread. + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/** + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * Port Specific Information: + * + * The IDLE thread should not be using the FPU. Leave this off. + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Port Specific Information: + * + * See earlier comments. There is no FPU state to manage. + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine @ref _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * @ref _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) + * + * Port Specific Information: + * + * There does not appear to be a reason for the v850 port itself to provide + * a special idle task. + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * Port Specific Information: + * + * The v850 stack grows from high addresses to low addresses. + */ +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT + +/** + * @ingroup CPUInterrupt + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. + * + * Port Specific Information: + * + * The v850 only has a single bit in the CPU for interrupt disable/enable. + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#define CPU_MAXIMUM_PROCESSORS 32 + +/** + * @defgroup CPUContext Processor Dependent Context Management + * + * From the highest level viewpoint, there are 2 types of context to save. + * + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * Port Specific Information: + * + * On the v850, this port saves special registers and those that are + * callee saved. + */ +/**@{**/ + +/** + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ +typedef struct { + uint32_t r1; + /** This field is the stack pointer (e.g. r3). */ + uint32_t r3_stack_pointer; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t r26; + uint32_t r27; + uint32_t r28; + uint32_t r29; + uint32_t r31; + uint32_t psw; +} Context_Control; + +/** + * This macro returns the stack pointer associated with @a _context. + * + * @param[in] _context is the thread context area to access + * + * @return This method returns the stack pointer. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r3_stack_pointer + +/** + * This defines the complete set of floating point registers that must + * be saved during any context switch from one thread to another. + */ +typedef struct { + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +/** + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ +typedef struct { + /** This field is a hint that a port will have a number of integer + * registers that need to be saved when an interrupt occurs or + * when a context switch occurs at the end of an ISR. + */ + uint32_t special_interrupt_register; +} CPU_Interrupt_frame; + +/** @} */ + +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in @ref _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * @note These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +/**@{**/ + +/** + * @ingroup CPUContext + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Port Specific Information: + * + * The v850 does not need a floating point context but this needs to be + * defined so confdefs.h. + */ +/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */ +#define CPU_CONTEXT_FP_SIZE 0 + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + * Port Specific Information: + * + * There is no reason to think the v850 needs extra MPCI receive + * server stack. + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/** + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable @a _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** @} */ + +/** + * @ingroup CPUContext + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * Port Specific Information: + * + * This should be very conservative on the v850. + */ +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +#define CPU_SIZEOF_POINTER 4 + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * Port Specific Information: + * + * There is no apparent reason why this should be larger than 8. + */ +#define CPU_ALIGNMENT 8 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. + * + * @note This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + * Port Specific Information: + * + * There is no apparent reason why this should be larger than CPU_ALIGNMENT. + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. + * + * @note This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * There is no apparent reason why this should be larger than CPU_ALIGNMENT. + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by @ref CPU_ALIGNMENT. If the + * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be + * set to 0. + * + * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * The v850 has enough RAM where alignment to 16 may be desirable depending + * on the cache properties. But this remains to be demonstrated. + */ +#define CPU_STACK_ALIGNMENT 4 + +/* + * ISR handler macros + */ + +/** + * @addtogroup CPUInterrupt + */ +/**@{**/ + +/** + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in @a _isr_cookie. + * + * @param[out] _isr_cookie will contain the previous level cookie + * + * Port Specific Information: + * + * On the v850, we need to save the PSW and use "di" to disable interrupts. + */ +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + unsigned int _psw; \ + \ + v850_get_psw( _psw ); \ + __asm__ __volatile__( "di" ); \ + _isr_cookie = _psw; \ + } while (0) + +/** + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * @a _isr_cookie is not modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * On the v850, we simply need to restore the PSW. + */ +#define _CPU_ISR_Enable( _isr_cookie ) \ + do { \ + unsigned int _psw = (_isr_cookie); \ + \ + v850_set_psw( _psw ); \ + } while (0) + +/** + * This temporarily restores the interrupt to @a _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * This saves at least one instruction over using enable/disable back to back. + */ +#define _CPU_ISR_Flash( _isr_cookie ) \ + do { \ + unsigned int _psw = (_isr_cookie); \ + v850_set_psw( _psw ); \ + __asm__ __volatile__( "di" ); \ + } while (0) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & V850_PSW_INTERRUPT_DISABLE_MASK ) + != V850_PSW_INTERRUPT_DISABLE; +} + +/** + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * Port Specific Information: + * + * On the v850, level 0 is enabled. Non-zero is disabled. + */ +#define _CPU_ISR_Set_level( new_level ) \ + do { \ + if ( new_level ) \ + __asm__ __volatile__( "di" ); \ + else \ + __asm__ __volatile__( "ei" ); \ + } while (0) + +/** + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * @note This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * This method is implemented in C on the v850. + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/** @} */ + +/* Context handler macros */ + +/** + * @ingroup CPUContext + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * @param[in] _the_context is the context structure to be initialized + * @param[in] _stack_base is the lowest physical address of this task's stack + * @param[in] _size is the size of this task's stack + * @param[in] _isr is the interrupt disable level + * @param[in] _entry_point is the thread's entry point. This is + * always @a _Thread_Handler + * @param[in] _is_fp is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * @param[in] tls_area is the thread-local storage (TLS) area + * + * Port Specific Information: + * + * This method is implemented in C on the v850. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp, + void *tls_area +); + +/** + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. For many ports, simply adding a label to the restore path + * of @ref _CPU_Context_switch will work. On other ports, it may be + * possibly to load a few arguments and jump to the restore path. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * Port Specific Information: + * + * On the v850, we require a special entry point to restart a task. + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* XXX this should be possible to remove */ +#if 0 +/** + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * @a _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other floating point context save/restore models include: + * -# not doing anything, and + * -# putting a "null FP status word" in the correct place in the FP context. + * + * @param[in] _destination is the floating point context area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + } +#endif + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * Port Specific Information: + * + * Move the error code into r10, disable interrupts and halt. + */ +#define _CPU_Fatal_halt( _source, _error ) \ + do { \ + __asm__ __volatile__ ( "di" ); \ + __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \ + __asm__ __volatile__ ( "halt" ); \ + } while (0) + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/** + * @brief CPU initialize. + * This routine performs CPU dependent initialization. + * + * Port Specific Information: + * + * This is implemented in C. + * + * v850 CPU Dependent Source + */ +void _CPU_Initialize(void); + +/** + * @addtogroup CPUContext + */ +/**@{**/ + +/** + * This routine switches from the run context to the heir context. + * + * @param[in] run points to the context of the currently executing task + * @param[in] heir points to the context of the heir task + * + * Port Specific Information: + * + * This is implemented in assembly on the v850. + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. + * + * @param[in] new_context points to the context to be restored. + * + * @note May be unnecessary to reload some registers. + * + * Port Specific Information: + * + * This is implemented in assembly on the v850. + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* XXX this should be possible to remove */ +#if 0 +/** + * This routine saves the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_restore_fp to restore this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); +#endif + +/* XXX this should be possible to remove */ +#if 0 +/** + * This routine restores the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area to restore + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_save_fp to save this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); +#endif + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/** @} */ + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +/** + * @ingroup CPUEndian + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * The v850 has a single instruction to swap endianness on a 32 bit quantity. + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + unsigned int swapped; + + #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) + unsigned int v; + + v = value; + __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) ); + #else + uint32_t byte1, byte2, byte3, byte4; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + #endif + return swapped; +} + +/** + * @ingroup CPUEndian + * This routine swaps a 16 bir quantity. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * The v850 has a single instruction to swap endianness on a 16 bit quantity. + */ +static inline uint16_t CPU_swap_u16( uint16_t value ) +{ + unsigned int swapped; + + #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) + unsigned int v; + + v = value; + __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) ); + #else + swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff); + #endif + return swapped; +} + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/v850/include/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..8a74cc6410 --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/score/cpu_asm.h @@ -0,0 +1,70 @@ +/** + * @file + * + * @brief V850 Assembly File + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + +/* pull in the generated offsets */ + +#include + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/v850/include/rtems/score/types.h b/cpukit/score/cpu/v850/include/rtems/score/types.h new file mode 100644 index 0000000000..bfec49d284 --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/score/types.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @brief V850 CPU Type Definitions + * + * This include file contains type definitions pertaining to the + * v850 processor family. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/cpukit/score/cpu/v850/include/rtems/score/v850.h b/cpukit/score/cpu/v850/include/rtems/score/v850.h new file mode 100644 index 0000000000..26ab6c209d --- /dev/null +++ b/cpukit/score/cpu/v850/include/rtems/score/v850.h @@ -0,0 +1,137 @@ +/** + * @file + * + * @brief V850 Set up Basic CPU Dependency Settings Based on Compiler Settings + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specified to the Renesas v850 port. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_V850_H +#define _RTEMS_SCORE_V850_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the NO CPU family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +#if defined(rtems_multilib) +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ +#define CPU_MODEL_NAME "rtems_multilib" +#define V850_HAS_FPU 0 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 0 + +#elif defined(__v850e2v3__) +#define CPU_MODEL_NAME "v850e2v3" +#define V850_HAS_FPU 1 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 + +#elif defined(__v850e2__) +#define CPU_MODEL_NAME "v850e2" +#define V850_HAS_FPU 0 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 + +#elif defined(__v850es__) +#define CPU_MODEL_NAME "v850es" +#define V850_HAS_FPU 0 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 + +#elif defined(__v850e1__) +#define CPU_MODEL_NAME "v850e1" +#define V850_HAS_FPU 0 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 + +#elif defined(__v850e__) +#define CPU_MODEL_NAME "v850e" +#define V850_HAS_FPU 0 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 + +#else +#define CPU_MODEL_NAME "v850" +#define V850_HAS_FPU 0 +#define V850_HAS_BYTE_SWAP_INSTRUCTION 0 + +#endif + +/* + * Define the name of the CPU family. + */ +#define CPU_NAME "v850 CPU" + +/* + * Method to set the Program Status Word (PSW) + */ +#define v850_set_psw( _psw ) \ + __asm__ __volatile__( "ldsr %0, psw" : : "r" (_psw) ) + +/* + * Method to obtain the Program Status Word (PSW) + */ +#define v850_get_psw( _psw ) \ + __asm__ __volatile__( "stsr psw, %0" : "=&r" (_psw) ) + +/* + * Masks and bits in the Program Status Word (PSW) + */ +#define V850_PSW_ZERO_MASK 0x01 +#define V850_PSW_IS_ZERO 0x01 +#define V850_PSW_IS_NOT 0x00 + +#define V850_PSW_SIGN_MASK 0x02 +#define V850_PSW_SIGN_IS_NEGATIVE 0x02 +#define V850_PSW_SIGN_IS_ZERO_OR_POSITIVE 0x00 + +#define V850_PSW_OVERFLOW_MASK 0x02 +#define V850_PSW_OVERFLOW_OCCURRED 0x02 +#define V850_PSW_OVERFLOW_DID_NOT_OCCUR 0x00 + +#define V850_PSW_CARRY_OR_BORROW_MASK 0x04 +#define V850_PSW_CARRY_OR_BORROW_OCCURRED 0x04 +#define V850_PSW_CARRY_OR_BORROW_DID_NOT_OCCUR 0x00 + +#define V850_PSW_SATURATION_MASK 0x10 +#define V850_PSW_SATURATION_OCCURRED 0x10 +#define V850_PSW_SATURATION_DID_NOT_OCCUR 0x00 + +#define V850_PSW_INTERRUPT_DISABLE_MASK 0x20 +#define V850_PSW_INTERRUPT_DISABLE 0x20 +#define V850_PSW_INTERRUPT_ENABLE 0x00 + +#define V850_PSW_EXCEPTION_IN_PROCESS_MASK 0x40 +#define V850_PSW_EXCEPTION_IN_PROCESS 0x40 +#define V850_PSW_EXCEPTION_NOT_IN_PROCESS 0x00 + +#define V850_PSW_NMI_IN_PROCESS_MASK 0x80 +#define V850_PSW_NMI_IN_PROCESS 0x80 +#define V850_PSW_NMI_NOT_IN_PROCESS 0x00 + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_V850_H */ diff --git a/cpukit/score/cpu/v850/preinstall.am b/cpukit/score/cpu/v850/preinstall.am deleted file mode 100644 index 5acf6a3db5..0000000000 --- a/cpukit/score/cpu/v850/preinstall.am +++ /dev/null @@ -1,53 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/score/cpuimpl.h: rtems/score/cpuimpl.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuimpl.h - -$(PROJECT_INCLUDE)/rtems/score/v850.h: rtems/score/v850.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/v850.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/v850.h - -$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h - -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h - -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h - diff --git a/cpukit/score/cpu/v850/rtems/asm.h b/cpukit/score/cpu/v850/rtems/asm.h deleted file mode 100644 index 265e4967ae..0000000000 --- a/cpukit/score/cpu/v850/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2012. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h deleted file mode 100644 index d3cdf0514a..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpu.h +++ /dev/null @@ -1,951 +0,0 @@ -/** - * @file - * - * @brief V850 CPU Department Source - * - * This include file contains information pertaining to the v850 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * The v850 does not have support for a hardware interrupt stack. - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * This port uses the Progammable Interrupt Controller interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * The v850 does not have support for a hardware interrupt stack. - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "V850_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * Some v850 models do have IEEE hardware floating point support but - * they do not have any special registers to save or bit(s) which - * determine if the FPU is enabled. In short, there appears to be nothing - * related to the floating point operations which impact the RTEMS - * thread context switch. Thus from an RTEMS perspective, there is really - * no FPU to manage. - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * This should be false until it has been demonstrated that gcc for the - * v850 generates FPU code when it is unexpected. But even this would - * not matter since there are no FP specific registers or bits which - * would be corrupted if an FP operation occurred in an integer only - * thread. - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * The IDLE thread should not be using the FPU. Leave this off. - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * See earlier comments. There is no FPU state to manage. - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * There does not appear to be a reason for the v850 port itself to provide - * a special idle task. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * The v850 stack grows from high addresses to low addresses. - */ -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * The v850 only has a single bit in the CPU for interrupt disable/enable. - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * On the v850, this port saves special registers and those that are - * callee saved. - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r1; - /** This field is the stack pointer (e.g. r3). */ - uint32_t r3_stack_pointer; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t r28; - uint32_t r29; - uint32_t r31; - uint32_t psw; -} Context_Control; - -/** - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r3_stack_pointer - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * The v850 does not need a floating point context but this needs to be - * defined so confdefs.h. - */ -/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */ -#define CPU_CONTEXT_FP_SIZE 0 - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * There is no reason to think the v850 needs extra MPCI receive - * server stack. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * This should be very conservative on the v850. - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than 8. - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than CPU_ALIGNMENT. - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than CPU_ALIGNMENT. - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * The v850 has enough RAM where alignment to 16 may be desirable depending - * on the cache properties. But this remains to be demonstrated. - */ -#define CPU_STACK_ALIGNMENT 4 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * On the v850, we need to save the PSW and use "di" to disable interrupts. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned int _psw; \ - \ - v850_get_psw( _psw ); \ - __asm__ __volatile__( "di" ); \ - _isr_cookie = _psw; \ - } while (0) - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * On the v850, we simply need to restore the PSW. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned int _psw = (_isr_cookie); \ - \ - v850_set_psw( _psw ); \ - } while (0) - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * This saves at least one instruction over using enable/disable back to back. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned int _psw = (_isr_cookie); \ - v850_set_psw( _psw ); \ - __asm__ __volatile__( "di" ); \ - } while (0) - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & V850_PSW_INTERRUPT_DISABLE_MASK ) - != V850_PSW_INTERRUPT_DISABLE; -} - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * On the v850, level 0 is enabled. Non-zero is disabled. - */ -#define _CPU_ISR_Set_level( new_level ) \ - do { \ - if ( new_level ) \ - __asm__ __volatile__( "di" ); \ - else \ - __asm__ __volatile__( "ei" ); \ - } while (0) - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * This method is implemented in C on the v850. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * This method is implemented in C on the v850. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * On the v850, we require a special entry point to restart a task. - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * Move the error code into r10, disable interrupts and halt. - */ -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - __asm__ __volatile__ ( "di" ); \ - __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \ - __asm__ __volatile__ ( "halt" ); \ - } while (0) - -/* end of Fatal Error manager macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * This is implemented in C. - * - * v850 CPU Dependent Source - */ -void _CPU_Initialize(void); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * This is implemented in assembly on the v850. - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * This is implemented in assembly on the v850. - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * The v850 has a single instruction to swap endianness on a 32 bit quantity. - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - unsigned int swapped; - - #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) - unsigned int v; - - v = value; - __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) ); - #else - uint32_t byte1, byte2, byte3, byte4; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - #endif - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * The v850 has a single instruction to swap endianness on a 16 bit quantity. - */ -static inline uint16_t CPU_swap_u16( uint16_t value ) -{ - unsigned int swapped; - - #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) - unsigned int v; - - v = value; - __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) ); - #else - swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff); - #endif - return swapped; -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h deleted file mode 100644 index 8a74cc6410..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * @brief V850 Assembly File - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/v850/rtems/score/cpuatomic.h b/cpukit/score/cpu/v850/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/v850/rtems/score/cpuimpl.h b/cpukit/score/cpu/v850/rtems/score/cpuimpl.h deleted file mode 100644 index 789f2badd9..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpuimpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/v850/rtems/score/types.h b/cpukit/score/cpu/v850/rtems/score/types.h deleted file mode 100644 index bfec49d284..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/types.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * - * @brief V850 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * v850 processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/v850.h b/cpukit/score/cpu/v850/rtems/score/v850.h deleted file mode 100644 index 26ab6c209d..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/v850.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * - * @brief V850 Set up Basic CPU Dependency Settings Based on Compiler Settings - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the Renesas v850 port. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_V850_H -#define _RTEMS_SCORE_V850_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ -#define CPU_MODEL_NAME "rtems_multilib" -#define V850_HAS_FPU 0 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 0 - -#elif defined(__v850e2v3__) -#define CPU_MODEL_NAME "v850e2v3" -#define V850_HAS_FPU 1 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 - -#elif defined(__v850e2__) -#define CPU_MODEL_NAME "v850e2" -#define V850_HAS_FPU 0 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 - -#elif defined(__v850es__) -#define CPU_MODEL_NAME "v850es" -#define V850_HAS_FPU 0 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 - -#elif defined(__v850e1__) -#define CPU_MODEL_NAME "v850e1" -#define V850_HAS_FPU 0 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 - -#elif defined(__v850e__) -#define CPU_MODEL_NAME "v850e" -#define V850_HAS_FPU 0 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 1 - -#else -#define CPU_MODEL_NAME "v850" -#define V850_HAS_FPU 0 -#define V850_HAS_BYTE_SWAP_INSTRUCTION 0 - -#endif - -/* - * Define the name of the CPU family. - */ -#define CPU_NAME "v850 CPU" - -/* - * Method to set the Program Status Word (PSW) - */ -#define v850_set_psw( _psw ) \ - __asm__ __volatile__( "ldsr %0, psw" : : "r" (_psw) ) - -/* - * Method to obtain the Program Status Word (PSW) - */ -#define v850_get_psw( _psw ) \ - __asm__ __volatile__( "stsr psw, %0" : "=&r" (_psw) ) - -/* - * Masks and bits in the Program Status Word (PSW) - */ -#define V850_PSW_ZERO_MASK 0x01 -#define V850_PSW_IS_ZERO 0x01 -#define V850_PSW_IS_NOT 0x00 - -#define V850_PSW_SIGN_MASK 0x02 -#define V850_PSW_SIGN_IS_NEGATIVE 0x02 -#define V850_PSW_SIGN_IS_ZERO_OR_POSITIVE 0x00 - -#define V850_PSW_OVERFLOW_MASK 0x02 -#define V850_PSW_OVERFLOW_OCCURRED 0x02 -#define V850_PSW_OVERFLOW_DID_NOT_OCCUR 0x00 - -#define V850_PSW_CARRY_OR_BORROW_MASK 0x04 -#define V850_PSW_CARRY_OR_BORROW_OCCURRED 0x04 -#define V850_PSW_CARRY_OR_BORROW_DID_NOT_OCCUR 0x00 - -#define V850_PSW_SATURATION_MASK 0x10 -#define V850_PSW_SATURATION_OCCURRED 0x10 -#define V850_PSW_SATURATION_DID_NOT_OCCUR 0x00 - -#define V850_PSW_INTERRUPT_DISABLE_MASK 0x20 -#define V850_PSW_INTERRUPT_DISABLE 0x20 -#define V850_PSW_INTERRUPT_ENABLE 0x00 - -#define V850_PSW_EXCEPTION_IN_PROCESS_MASK 0x40 -#define V850_PSW_EXCEPTION_IN_PROCESS 0x40 -#define V850_PSW_EXCEPTION_NOT_IN_PROCESS 0x00 - -#define V850_PSW_NMI_IN_PROCESS_MASK 0x80 -#define V850_PSW_NMI_IN_PROCESS 0x80 -#define V850_PSW_NMI_NOT_IN_PROCESS 0x00 - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_V850_H */ -- cgit v1.2.3