From 2433a8ab1c451e47f39c3414ad1e46074b6b7607 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 7 Mar 2017 14:32:42 +0100 Subject: arm: Remove legacy execption support --- cpukit/score/cpu/arm/Makefile.am | 2 - cpukit/score/cpu/arm/arm_exc_handler_high.c | 127 --------------------- cpukit/score/cpu/arm/arm_exc_handler_low.S | 166 ---------------------------- cpukit/score/cpu/arm/rtems/score/cpu.h | 6 - 4 files changed, 301 deletions(-) delete mode 100644 cpukit/score/cpu/arm/arm_exc_handler_high.c delete mode 100644 cpukit/score/cpu/arm/arm_exc_handler_low.S (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/arm/Makefile.am b/cpukit/score/cpu/arm/Makefile.am index 33372a235d..6e98ed5cac 100644 --- a/cpukit/score/cpu/arm/Makefile.am +++ b/cpukit/score/cpu/arm/Makefile.am @@ -23,8 +23,6 @@ libscorecpu_a_SOURCES += arm-context-validate.S libscorecpu_a_SOURCES += arm-context-volatile-clobber.S libscorecpu_a_SOURCES += arm_exc_abort.S libscorecpu_a_SOURCES += arm_exc_interrupt.S -libscorecpu_a_SOURCES += arm_exc_handler_low.S -libscorecpu_a_SOURCES += arm_exc_handler_high.c libscorecpu_a_SOURCES += arm-exception-frame-print.c libscorecpu_a_SOURCES += arm-exception-default.c libscorecpu_a_SOURCES += armv4-exception-default.S diff --git a/cpukit/score/cpu/arm/arm_exc_handler_high.c b/cpukit/score/cpu/arm/arm_exc_handler_high.c deleted file mode 100644 index 493d99329a..0000000000 --- a/cpukit/score/cpu/arm/arm_exc_handler_high.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @ingroup ScoreCPU - * - * @brief ARM exception support implementation. - */ - -/* - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc - * Jay Monkman - * - * Copyright (c) 2007 Ray xu - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Moved from file 'cpukit/score/cpu/arm/cpu.c'. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#ifdef ARM_MULTILIB_ARCH_V4 - -static void _defaultExcHandler (CPU_Exception_frame *ctx) -{ - printk("\n\r"); - printk("----------------------------------------------------------\n\r"); -#if 1 - printk("Exception 0x%x caught at PC 0x%" PRIxPTR - " by thread 0x%" PRIx32 "\n", - ctx->vector, (uintptr_t) ctx->register_lr - 4, - _Thread_Executing->Object.id); -#endif - printk("----------------------------------------------------------\n\r"); - printk("Processor execution context at time of the fault was :\n\r"); - printk("----------------------------------------------------------\n\r"); -#if 0 - printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", - ctx->register_r0, ctx->register_r1, - ctx->register_r2, ctx->register_r3); - printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", - ctx->register_r4, ctx->register_r5, - ctx->register_r6, ctx->register_r7); - printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", - ctx->register_r8, ctx->register_r9, ctx->register_r10); - printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", - ctx->register_fp, ctx->register_ip, - ctx->register_sp, ctx->register_lr - 4); - printk("----------------------------------------------------------\n\r"); -#endif - if (_ISR_Nest_level > 0) { - /* - * In this case we shall not delete the task interrupted as - * it has nothing to do with the fault. We cannot return either - * because the eip points to the faulty instruction so... - */ - printk("Exception while executing ISR!!!. System locked\n\r"); - while(1); - } - else { - printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); - rtems_task_delete(_Thread_Executing->Object.id); - } -} - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); - -cpuExcHandlerType _currentExcHandler = _defaultExcHandler; - -extern void _Exception_Handler_Undef_Swi(void); -extern void _Exception_Handler_Abort(void); -extern void _exc_data_abort(void); - - - -/* FIXME: put comments here */ -void rtems_exception_init_mngt(void) -{ - ISR_Level level; - - _CPU_ISR_Disable(level); - _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, - _exc_data_abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_Enable(level); -} - -#endif /* ARM_MULTILIB_ARCH_V4 */ diff --git a/cpukit/score/cpu/arm/arm_exc_handler_low.S b/cpukit/score/cpu/arm/arm_exc_handler_low.S deleted file mode 100644 index e7ce507591..0000000000 --- a/cpukit/score/cpu/arm/arm_exc_handler_low.S +++ /dev/null @@ -1,166 +0,0 @@ -/** - * @file - * - * @ingroup ScoreCPU - * - * @brief ARM exception support implementation. - */ - -/* - * Copyright (c) 2007 by Ray Xu, - * Thumb support added. - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Moved from file 'cpukit/score/cpu/arm/cpu_asm.S'. - * - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include - -#ifdef ARM_MULTILIB_ARCH_V4 - - .text - -/* FIXME: _Exception_Handler_Undef_Swi is untested */ -DEFINE_FUNCTION_ARM(_Exception_Handler_Undef_Swi) -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str r11, [r13, #REG_R11] - str sp, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in r0 (C arg 1) */ - - ldr r1, =SWI_Handler - ldr lr, =_go_back_1 - ldr pc,[r1] /* call handler */ -_go_back_1: - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr r11, [r13, #REG_R11] - ldr sp, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - movs pc,r14 /* return */ - -/* FIXME: _Exception_Handler_Abort is untested */ -DEFINE_FUNCTION_ARM(_Exception_Handler_Abort) -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str sp, [r13, #REG_R11] - str lr, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in ro (C arg 1) */ - - ldr r1, =_currentExcHandler - ldr lr, =_go_back_2 - ldr pc,[r1] /* call handler */ -_go_back_2: - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr sp, [r13, #REG_R11] - ldr lr, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS -#ifdef __thumb__ - subs r11, r14,#4 - bx r11 - nop -#else - subs pc,r14,#4 /* return */ -#endif - -#define ABORT_REGS_OFFS 32-REG_R4 -#define ABORT_SIZE_REGS SIZE_REGS+ABORT_REGS_OFFS - -DEFINE_FUNCTION_ARM(_exc_data_abort) - sub sp, sp, #ABORT_SIZE_REGS /* reserve register frame */ - stmia sp, {r0-r11} - add sp, sp, #ABORT_REGS_OFFS /* the Context_Control structure starts by CPSR, R4, ... */ - - str ip, [sp, #REG_PC] /* store R12 (ip) somewhere, oh hackery, hackery, hack */ - str lr, [sp, #REG_LR] - - mov r1, lr - ldr r0, [r1, #-8] /* r0 = bad instruction */ - mrs r1, spsr /* r1 = spsr */ - mov r2, r13 /* r2 = exception frame of Context_Control type */ -#if defined(__thumb__) - .code 32 - /*arm to thumb*/ - adr r5, to_thumb + 1 - bx r5 - .code 16 -to_thumb: -#endif - bl do_data_abort -#if defined(__thumb__) -/*back to arm*/ - .code 16 -thumb_to_arm: - .align 2 - adr r5, arm_code - bx r5 - nop - .code 32 -arm_code: -#endif - - ldr lr, [sp, #REG_LR] - ldr ip, [sp, #REG_PC] /* restore R12 (ip) */ - - sub sp, sp, #ABORT_REGS_OFFS - ldmia sp, {r0-r11} - add sp, sp, #ABORT_SIZE_REGS -#ifdef __thumb__ - subs r11, r14, #4 /* return to the instruction */ - bx r11 - nop -#else - subs pc, r14, #4 -#endif - /* _AFTER_ the aborted one */ - -#endif /* ARM_MULTILIB_ARCH_V4 */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 9f321acc0a..b10bc7195c 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -704,12 +704,6 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); void _ARM_Exception_default( CPU_Exception_frame *frame ); -/* - * FIXME: In case your BSP uses this function, then convert it to use - * the shared start.S file for ARM. - */ -void rtems_exception_init_mngt( void ); - /** @} */ #ifdef __cplusplus -- cgit v1.2.3