From 10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9 Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Thu, 14 Jul 2022 18:10:45 -0500 Subject: aarch64: Use page table level 0 This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports. --- cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h | 1 - 1 file changed, 1 deletion(-) (limited to 'cpukit/score/cpu') diff --git a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h index 6b6296bb7a..0d65004f88 100644 --- a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h +++ b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h @@ -60,7 +60,6 @@ extern "C" { #define MMU_PAGE_BITS 12 #define MMU_PAGE_SIZE ( 1 << MMU_PAGE_BITS ) #define MMU_BITS_PER_LEVEL 9 -#define MMU_TOP_LEVEL_PAGE_BITS ( 2 * MMU_BITS_PER_LEVEL + MMU_PAGE_BITS ) #define AARCH64_MMU_FLAGS_BASE \ ( MMU_DESC_VALID | MMU_DESC_SH_INNER | MMU_DESC_AF ) -- cgit v1.2.3