From 80f77327f3fbd95710cb44e308b3a3fe062ce220 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Wed, 2 Dec 2009 09:48:25 +0000 Subject: Whitespace removal. --- cpukit/score/cpu/sparc/cpu.c | 38 +++++++++++----------- cpukit/score/cpu/sparc/cpu_asm.S | 48 +++++++++++++-------------- cpukit/score/cpu/sparc/rtems/asm.h | 4 +-- cpukit/score/cpu/sparc/rtems/score/cpu.h | 52 +++++++++++++++--------------- cpukit/score/cpu/sparc/rtems/score/sparc.h | 22 ++++++------- cpukit/score/cpu/sparc/rtems/score/types.h | 2 +- 6 files changed, 83 insertions(+), 83 deletions(-) (limited to 'cpukit/score/cpu/sparc') diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index 4db94537cf..b29620414f 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -16,7 +16,7 @@ #include /* - * This initializes the set of opcodes placed in each trap + * This initializes the set of opcodes placed in each trap * table entry. The routine which installs a handler is responsible * for filling in the fields for the _handler address and the _vector * trap type. @@ -41,7 +41,7 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = { * INPUT PARAMETERS: NONE * * Output Parameters: NONE - * + * * NOTE: There is no need to save the pointer to the thread dispatch routine. * The SPARC's assembly code can reference it directly with no problems. */ @@ -78,13 +78,13 @@ void _CPU_Initialize(void) * Output Parameters: * returns the current interrupt level (PIL field of the PSR) */ - + uint32_t _CPU_ISR_Get_level( void ) { uint32_t level; - + sparc_get_interrupt_level( level ); - + return level; } @@ -96,15 +96,15 @@ uint32_t _CPU_ISR_Get_level( void ) * supported trap handler (a.k.a. interrupt service routine). * * Input Parameters: - * vector - trap table entry number plus synchronous + * vector - trap table entry number plus synchronous * vs. asynchronous information * new_handler - address of the handler to be installed * old_handler - pointer to an address of the handler previously installed * * Output Parameters: NONE * *new_handler - address of the handler previously installed - * - * NOTE: + * + * NOTE: * * On the SPARC, there are really only 256 vectors. However, the executive * has no easy, fast, reliable way to determine which traps are synchronous @@ -125,7 +125,7 @@ uint32_t _CPU_ISR_Get_level( void ) * an asynchronous trap. This will avoid the executive changing the return * address. */ - + void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, @@ -170,7 +170,7 @@ void _CPU_ISR_install_raw_handler( #define LOW_BITS_MASK 0x000003FF if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { - u32_handler = + u32_handler = (slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) | (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); *old_handler = (proc_ptr) u32_handler; @@ -186,7 +186,7 @@ void _CPU_ISR_install_raw_handler( u32_handler = (uint32_t) new_handler; slot->mov_vector_l3 |= vector; - slot->sethi_of_handler_to_l4 |= + slot->sethi_of_handler_to_l4 |= (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); @@ -208,7 +208,7 @@ void _CPU_ISR_install_raw_handler( * new_handler - replacement ISR for this vector number * old_handler - pointer to former ISR for this vector number * - * Output parameters: + * Output parameters: * *old_handler - former ISR for this vector number * */ @@ -279,21 +279,21 @@ void _CPU_Context_Initialize( uint32_t stack_high; /* highest "stack aligned" address */ uint32_t the_size; uint32_t tmp_psr; - + /* * On CPUs with stacks which grow down (i.e. SPARC), we build the stack - * based on the stack_high address. + * based on the stack_high address. */ - + stack_high = ((uint32_t)(stack_base) + size); stack_high &= ~(CPU_STACK_ALIGNMENT - 1); - + the_size = size & ~(CPU_STACK_ALIGNMENT - 1); - + /* * See the README in this directory for a diagram of the stack. */ - + the_context->o7 = ((uint32_t) entry_point) - 8; the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; the_context->i6_fp = 0; @@ -311,7 +311,7 @@ void _CPU_Context_Initialize( tmp_psr &= ~SPARC_PSR_PIL_MASK; tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ - + #if (SPARC_HAS_FPU == 1) /* * If this bit is not set, then a task gets a fault when it accesses diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S index 119d3b0228..90711378a2 100644 --- a/cpukit/score/cpu/sparc/cpu_asm.S +++ b/cpukit/score/cpu/sparc/cpu_asm.S @@ -2,7 +2,7 @@ * * This file contains the basic algorithms for all assembly code used * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language. + * in assembly language. * * COPYRIGHT (c) 1989-2007. * On-Line Applications Research Corporation (OAR). @@ -12,10 +12,10 @@ * http://www.rtems.com/license/LICENSE. * * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space + * Research Corporation (OAR) under contract to the European Space * Agency (ESA). * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. * European Space Agency. * * $Id$ @@ -34,7 +34,7 @@ * at *fp_context_ptr. If the point to load the FP context * from is changed then the pointer is modified by this routine. * - * NOTE: See the README in this directory for information on the + * NOTE: See the README in this directory for information on the * management of the "EF" bit in the PSR. */ @@ -46,13 +46,13 @@ SYM(_CPU_Context_save_fp): /* * The following enables the floating point unit. */ - + mov %psr, %l0 sethi %hi(SPARC_PSR_EF_MASK), %l1 or %l1, %lo(SPARC_PSR_EF_MASK), %l1 or %l0, %l1, %l0 mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** - nop; nop; nop; ! Need three nops before EF is + nop; nop; nop; ! Need three nops before EF is ld [%i0], %l0 ! active due to pipeline delay!!! std %f0, [%l0 + FO_F1_OFFSET] std %f2, [%l0 + F2_F3_OFFSET] @@ -83,7 +83,7 @@ SYM(_CPU_Context_save_fp): * at *fp_context_ptr. If the point to load the FP context * from is changed then the pointer is modified by this routine. * - * NOTE: See the README in this directory for information on the + * NOTE: See the README in this directory for information on the * management of the "EF" bit in the PSR. */ @@ -95,13 +95,13 @@ SYM(_CPU_Context_restore_fp): /* * The following enables the floating point unit. */ - + mov %psr, %l0 sethi %hi(SPARC_PSR_EF_MASK), %l1 or %l1, %lo(SPARC_PSR_EF_MASK), %l1 or %l0, %l1, %l0 mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** - nop; nop; nop; ! Need three nops before EF is + nop; nop; nop; ! Need three nops before EF is ld [%i0], %l0 ! active due to pipeline delay!!! ldd [%l0 + FO_F1_OFFSET], %f0 ldd [%l0 + F2_F3_OFFSET], %f2 @@ -181,9 +181,9 @@ SYM(_CPU_Context_restore_heir): * Flush all windows with valid contents except the current one. * In examining the set register windows, one may logically divide * the windows into sets (some of which may be empty) based on their - * current status: + * current status: * - * + current (i.e. in use), + * + current (i.e. in use), * + used (i.e. a restore would not trap) * + invalid (i.e. 1 in corresponding bit in WIM) * + unused @@ -202,9 +202,9 @@ SYM(_CPU_Context_restore_heir): * * In this case, we only would save the used windows -- 6 and 7. * - * Traps are disabled for the same logical period as in a + * Traps are disabled for the same logical period as in a * flush all windows trap handler. - * + * * Register Usage while saving the windows: * g1 = current PSR * g2 = current wim @@ -238,17 +238,17 @@ save_frame_loop: bnz done_flushing ! No, then continue nop - restore ! back one window + restore ! back one window /* * Now save the window just as if we overflowed to it. */ - + std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] - + std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] @@ -262,7 +262,7 @@ done_flushing: add %g3, 1, %g3 ! calculate desired WIM and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3 mov 1, %g4 - sll %g4, %g3, %g4 ! g4 = new WIM + sll %g4, %g3, %g4 ! g4 = new WIM mov %g4, %wim or %g1, SPARC_PSR_ET_MASK, %g1 @@ -559,9 +559,9 @@ fpu_revb: bne,a dont_fix_pil2 wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** ba,a simple_return - + enable_irq: - or %g5, SPARC_PSR_PIL_MASK, %g4 + or %g5, SPARC_PSR_PIL_MASK, %g4 wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** nop; nop; nop fmovs %f0, %f0 @@ -658,7 +658,7 @@ dont_fix_pil2: bnz simple_return ! Yes, then do a "simple" exit ! NOTE: Use the delay slot sethi %hi(SYM(_Context_Switch_necessary)), %l4 - + /* * If a context switch is necessary, then do fudge stack to @@ -685,7 +685,7 @@ dont_fix_pil2: ! use the delay slot to clear the signals ! to the currently executing task flag st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))] - + /* * Invoke interrupt dispatcher. @@ -707,7 +707,7 @@ SYM(_ISR_Dispatch): sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp - or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1 + or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1 mov %l7, %psr ! **** ENABLE TRAPS **** nop nop @@ -719,7 +719,7 @@ isr_dispatch: /* * We invoked _Thread_Dispatch in a state similar to the interrupted * task. In order to safely be able to tinker with the register - * windows and get the task back to its pre-interrupt state, + * windows and get the task back to its pre-interrupt state, * we need to disable interrupts disabled so we can safely tinker * with the register windowing. In particular, the CWP in the PSR * is fragile during this period. (See PR578.) @@ -788,7 +788,7 @@ simple_return: and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task or %l3, %l0, %l0 ! install it later... - andn %l0, SPARC_PSR_ET_MASK, %l0 + andn %l0, SPARC_PSR_ET_MASK, %l0 /* * Restore tasks global and out registers diff --git a/cpukit/score/cpu/sparc/rtems/asm.h b/cpukit/score/cpu/sparc/rtems/asm.h index dafc584a64..1da25f8c26 100644 --- a/cpukit/score/cpu/sparc/rtems/asm.h +++ b/cpukit/score/cpu/sparc/rtems/asm.h @@ -99,7 +99,7 @@ /* * Entry for traps which jump to a programmer-specified trap handler. */ - + #define TRAP(_vector, _handler) \ mov %psr, %l0 ; \ sethi %hi(_handler), %l4 ; \ @@ -109,7 +109,7 @@ /* * Used for the reset trap to avoid a supervisor instruction */ - + #define RTRAP(_vector, _handler) \ mov %g0, %l0 ; \ sethi %hi(_handler), %l4 ; \ diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index b88de1ca8f..3e30e9a7f8 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -3,7 +3,7 @@ */ /* - * This include file contains information pertaining to the port of + * This include file contains information pertaining to the port of * the executive to the SPARC processor. * * COPYRIGHT (c) 1989-2006. @@ -103,7 +103,7 @@ extern "C" { /* * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? */ @@ -191,7 +191,7 @@ extern "C" { * the minimum requirements of the compiler in order to have as * much of the critical data area as possible in a cache line. * - * The SPARC does not appear to have particularly strict alignment + * The SPARC does not appear to have particularly strict alignment * requirements. This value was chosen to take advantages of caches. */ @@ -216,7 +216,7 @@ extern "C" { #define CPU_MODES_INTERRUPT_MASK 0x0000000F /* - * This structure represents the organization of the minimum stack frame + * This structure represents the organization of the minimum stack frame * for the SPARC. More framing information is required in certain situaions * such as when there are a large number of out parameters or when the callee * must save floating point registers. @@ -306,7 +306,7 @@ typedef struct { typedef struct { /* - * Using a double g0_g1 will put everything in this structure on a + * Using a double g0_g1 will put everything in this structure on a * double word boundary which allows us to use double word loads * and stores safely in the context switch. */ @@ -512,11 +512,11 @@ typedef struct { #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 +#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 #ifndef ASM /* * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP + * It is filled in by _CPU_Initialize and copied into the task's FP * context area during _CPU_Context_Initialize. */ @@ -555,14 +555,14 @@ SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable; * long jump. The other instructions load one register with the * trap type (a.k.a. vector) and another with the psr. */ - + typedef struct { uint32_t mov_psr_l0; /* mov %psr, %l0 */ uint32_t sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ uint32_t jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ uint32_t mov_vector_l3; /* mov _vector, %l3 */ } CPU_Trap_table_entry; - + /* * This is the set of opcodes for the instructions loaded into a trap * table entry. The routine which installs a handler is responsible @@ -572,11 +572,11 @@ typedef struct { * The constants following this structure are masks for the fields which * must be filled in when the handler is installed. */ - + extern const CPU_Trap_table_entry _CPU_Trap_slot_template; /* - * The size of the floating point context area. + * The size of the floating point context area. */ #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) @@ -714,7 +714,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template; #define _CPU_ISR_Disable( _level ) \ (_level) = sparc_disable_interrupts() - + /* * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). * This indicates the end of a critical section. The parameter @@ -733,18 +733,18 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template; #define _CPU_ISR_Flash( _level ) \ sparc_flash_interrupts( _level ) - + /* * Map interrupt level in task mode onto the hardware that the CPU * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. + * map onto the CPU in a straight fashion are undefined. */ #define _CPU_ISR_Set_level( _newlevel ) \ sparc_enable_interrupts( _newlevel << 8) - + uint32_t _CPU_ISR_Get_level( void ); - + /* end of ISR handler macros */ /* Context handler macros */ @@ -780,7 +780,7 @@ void _CPU_Context_Initialize( * On the SPARC, this is setting the frame pointer so GDB is happy. * Make GDB stop unwinding at _Thread_Handler, previous register window * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) + * with a SAVE instruction. If return address is leaf-function (no SAVE) * GDB will not look at prev reg window fp. * * _Thread_Handler is known to start with SAVE. @@ -793,7 +793,7 @@ void _CPU_Context_Initialize( /* * This routine is responsible for somehow restarting the currently - * executing task. + * executing task. * * On the SPARC, this is is relatively painless but requires a small * amount of wrapper code before using the regular restore code in @@ -815,7 +815,7 @@ void _CPU_Context_Initialize( * This routine initializes the FP context area passed to it to. * * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context + * in which an "initial" FP context was saved into _CPU_Null_fp_context * at CPU initialization and it is simply copied into the destination * context. */ @@ -891,7 +891,7 @@ void _CPU_Initialize(void); * This routine installs new_handler to be directly called from the trap * table. */ - + void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, @@ -911,14 +911,14 @@ void _CPU_ISR_install_vector( ); #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - + /* * _CPU_Thread_Idle_body * * Some SPARC implementations have low power, sleep, or idle modes. This * tries to take advantage of those models. */ - + void *_CPU_Thread_Idle_body( uintptr_t ignored ); #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ @@ -972,7 +972,7 @@ void _CPU_Context_restore_fp( * It must be static because it is referenced indirectly. * * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit + * way for the SPARC PLEASE use it. The most common way to swap a 32-bit * entity as shown below is not any more efficient on the SPARC. * * swap least significant two bytes with 16-bit rotate @@ -983,18 +983,18 @@ void _CPU_Context_restore_fp( * generic code. gcc 2.7.0 only generates about 12 instructions for the * following code at optimization level four (i.e. -O4). */ - + static inline uint32_t CPU_swap_u32( uint32_t value ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return( swapped ); } diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h b/cpukit/score/cpu/sparc/rtems/score/sparc.h index bd2fb697e6..f13470e0ac 100644 --- a/cpukit/score/cpu/sparc/rtems/score/sparc.h +++ b/cpukit/score/cpu/sparc/rtems/score/sparc.h @@ -3,7 +3,7 @@ */ /* - * This include file contains information pertaining to the SPARC + * This include file contains information pertaining to the SPARC * processor family. * * COPYRIGHT (c) 1989-1999. @@ -32,19 +32,19 @@ extern "C" { * * Currently recognized feature flags: * - * + SPARC_HAS_FPU + * + SPARC_HAS_FPU * 0 - no HW FPU * 1 - has HW FPU (assumed to be compatible w/90C602) * - * + SPARC_HAS_BITSCAN + * + SPARC_HAS_BITSCAN * 0 - does not have scan instructions * 1 - has scan instruction (not currently implemented) - * + * * + SPARC_NUMBER_OF_REGISTER_WINDOWS * 8 is the most common number supported by SPARC implementations. * SPARC_PSR_CWP_MASK is derived from this value. */ - + /* * Some higher end SPARCs have a bitscan instructions. It would * be nice to take advantage of them. Right now, there is no @@ -62,9 +62,9 @@ extern "C" { */ #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 - + /* - * This should be determined based on some soft float derived + * This should be determined based on some soft float derived * cpp predefine but gcc does not currently give us that information. */ @@ -192,24 +192,24 @@ extern "C" { /* * Get and set the Y */ - + #define sparc_get_y( _y ) \ do { \ asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ } while ( 0 ) - + #define sparc_set_y( _y ) \ do { \ asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ } while ( 0 ) /* - * Manipulate the interrupt level in the psr + * Manipulate the interrupt level in the psr */ uint32_t sparc_disable_interrupts(void); void sparc_enable_interrupts(uint32_t); - + #define sparc_flash_interrupts( _level ) \ do { \ register uint32_t _ignored = 0; \ diff --git a/cpukit/score/cpu/sparc/rtems/score/types.h b/cpukit/score/cpu/sparc/rtems/score/types.h index fa5c9d39ba..6368b39ccc 100644 --- a/cpukit/score/cpu/sparc/rtems/score/types.h +++ b/cpukit/score/cpu/sparc/rtems/score/types.h @@ -3,7 +3,7 @@ */ /* - * This include file contains type definitions pertaining to the + * This include file contains type definitions pertaining to the * SPARC processor family. * * COPYRIGHT (c) 1989-1999. -- cgit v1.2.3