From 022851aba54d32831feaff13deb3d9943e130eee Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 28 Jan 2014 12:10:08 +0100
Subject: Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC.  Other
architectures need more work.
---
 cpukit/score/cpu/sparc64/cpu.c             | 10 +++++++++-
 cpukit/score/cpu/sparc64/rtems/score/cpu.h |  3 ++-
 2 files changed, 11 insertions(+), 2 deletions(-)

(limited to 'cpukit/score/cpu/sparc64')

diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index 94f9340614..d7c2f47904 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -20,6 +20,7 @@
 #include <rtems/system.h>
 #include <rtems/asm.h>
 #include <rtems/score/isr.h>
+#include <rtems/score/tls.h>
 #include <rtems/rtems/cache.h>
 
 /*
@@ -65,7 +66,8 @@ void _CPU_Context_Initialize(
   uint32_t          size,
   uint32_t          new_level,
   void             *entry_point,
-  bool              is_fp
+  bool              is_fp,
+  void             *tls_area
 )
 {
     uint64_t     stack_high;  /* highest "stack aligned" address */
@@ -99,4 +101,10 @@ void _CPU_Context_Initialize(
    *  thread can have an _ISR_Dispatch stack frame on its stack.
    */
     the_context->isr_dispatch_disable = 0;
+
+  if ( tls_area != NULL ) {
+    void *tcb = _TLS_TCB_after_tls_block_initialize( tls_area );
+
+    the_context->g7 = (uintptr_t) tcb;
+  }
 }
diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
index 8d3e27318b..22ec97d17a 100644
--- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
@@ -838,7 +838,8 @@ void _CPU_Context_Initialize(
   uint32_t          size,
   uint32_t          new_level,
   void             *entry_point,
-  bool              is_fp
+  bool              is_fp,
+  void             *tls_area
 );
 
 /*
-- 
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