From a8865f8b415788c4e9bb7f68e38d41aec0e485db Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 25 Jan 2016 10:20:28 +0100 Subject: score: Introduce CPU_CACHE_LINE_BYTES Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size. --- cpukit/score/cpu/sparc/rtems/score/cpu.h | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'cpukit/score/cpu/sparc/rtems/score') diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 9b4db13b96..4170cb9946 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -210,17 +210,10 @@ extern "C" { */ #define CPU_STACK_GROWS_UP FALSE -/** - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value was chosen to take advantages of caches. - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 32 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) /** * Define what is required to specify how the network to host conversion -- cgit v1.2.3